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Searched refs:MPU_RASR_XN_Pos (Results 1 - 7 of 7) sorted by relevance

/third_party/cmsis/CMSIS/Core/Include/m-profile/
H A Darmv7m_mpu.h102 ((((DisableExec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \
/third_party/cmsis/CMSIS/Core/Include/
H A Dcore_sc000.h590 #define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ macro
591 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
H A Dcore_cm0plus.h574 #define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ macro
575 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
H A Dcore_cm4.h1265 #define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ macro
1266 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
H A Dcore_sc300.h1183 #define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ macro
1184 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
H A Dcore_cm3.h1200 #define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ macro
1201 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
H A Dcore_cm7.h1484 #define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ macro
1485 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */

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