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/kernel/linux/linux-5.10/arch/arm/mach-omap1/
H A Dclock_data.c113 .set_rate = &omap1_set_sossi_rate,
123 .set_rate = omap1_clk_set_rate_ckctl_arm,
137 .set_rate = omap1_clk_set_rate_ckctl_arm,
217 .set_rate = omap1_clk_set_rate_ckctl_arm,
227 .set_rate = omap1_clk_set_rate_ckctl_arm,
239 .set_rate = &omap1_clk_set_rate_dsp_domain,
269 .set_rate = omap1_clk_set_rate_ckctl_arm,
390 .set_rate = omap1_clk_set_rate_ckctl_arm,
404 .set_rate = omap1_clk_set_rate_ckctl_arm,
424 .set_rate
[all...]
/kernel/linux/linux-6.6/arch/arm/mach-omap1/
H A Dclock_data.c113 .set_rate = &omap1_set_sossi_rate,
121 .set_rate = omap1_clk_set_rate_ckctl_arm,
135 .set_rate = omap1_clk_set_rate_ckctl_arm,
205 .set_rate = omap1_clk_set_rate_ckctl_arm,
213 .set_rate = omap1_clk_set_rate_ckctl_arm,
224 .set_rate = &omap1_clk_set_rate_dsp_domain,
248 .set_rate = omap1_clk_set_rate_ckctl_arm,
340 .set_rate = omap1_clk_set_rate_ckctl_arm,
353 .set_rate = omap1_clk_set_rate_ckctl_arm,
372 .set_rate
[all...]
/kernel/linux/linux-5.10/arch/arm/mach-ep93xx/
H A Dclock.c36 int (*set_rate)(struct clk *clk, unsigned long rate); member
96 .set_rate = set_keytchclk_rate,
103 .set_rate = set_keytchclk_rate,
118 .set_rate = set_div_rate,
125 .set_rate = set_div_rate,
133 .set_rate = set_i2s_sclk_rate,
141 .set_rate = set_i2s_lrclk_rate,
476 if (clk->set_rate) in clk_set_rate()
477 return clk->set_rate(clk, rate); in clk_set_rate()
/kernel/linux/linux-6.6/drivers/clk/starfive/
H A Dclk-starfive-jh71x0.c236 .set_rate = jh71x0_clk_set_rate,
243 .set_rate = jh71x0_clk_frac_set_rate,
253 .set_rate = jh71x0_clk_set_rate,
279 .set_rate = jh71x0_clk_set_rate,
291 .set_rate = jh71x0_clk_set_rate,
/kernel/linux/linux-5.10/drivers/clk/ti/
H A Ddpll.c37 .set_rate = &omap3_noncore_dpll_set_rate,
62 .set_rate = &omap3_noncore_dpll_set_rate,
75 .set_rate = &omap3_noncore_dpll_set_rate,
94 .set_rate = &omap2_reprogram_dpllcore,
116 .set_rate = &omap3_noncore_dpll_set_rate,
128 .set_rate = &omap3_dpll5_set_rate,
140 .set_rate = &omap3_dpll4_set_rate,
/kernel/linux/linux-5.10/drivers/clk/actions/
H A Dowl-composite.c157 .set_rate = owl_comp_div_set_rate,
174 .set_rate = owl_comp_fact_set_rate,
186 .set_rate = owl_comp_fix_fact_set_rate,
/kernel/linux/linux-6.6/drivers/clk/actions/
H A Dowl-composite.c169 .set_rate = owl_comp_div_set_rate,
186 .set_rate = owl_comp_fact_set_rate,
198 .set_rate = owl_comp_fix_fact_set_rate,
/kernel/linux/linux-5.10/drivers/clk/
H A Dclk-composite.c139 return rate_ops->set_rate(rate_hw, rate, parent_rate); in clk_composite_set_rate()
159 rate_ops->set_rate(rate_hw, rate, parent_rate); in clk_composite_set_rate_and_parent()
163 rate_ops->set_rate(rate_hw, rate, parent_rate); in clk_composite_set_rate_and_parent()
260 /* .set_rate requires either .round_rate or .determine_rate */ in __clk_hw_register_composite()
261 if (rate_ops->set_rate) { in __clk_hw_register_composite()
263 clk_composite_ops->set_rate = in __clk_hw_register_composite()
275 if (mux_ops->set_parent && rate_ops->set_rate) in __clk_hw_register_composite()
/kernel/linux/linux-6.6/drivers/clk/
H A Dclk-composite.c174 return rate_ops->set_rate(rate_hw, rate, parent_rate); in clk_composite_set_rate()
194 rate_ops->set_rate(rate_hw, rate, parent_rate); in clk_composite_set_rate_and_parent()
198 rate_ops->set_rate(rate_hw, rate, parent_rate); in clk_composite_set_rate_and_parent()
295 /* .set_rate requires either .round_rate or .determine_rate */ in __clk_hw_register_composite()
296 if (rate_ops->set_rate) { in __clk_hw_register_composite()
298 clk_composite_ops->set_rate = in __clk_hw_register_composite()
310 if (mux_ops->set_parent && rate_ops->set_rate) in __clk_hw_register_composite()
/kernel/linux/linux-6.6/drivers/clk/ti/
H A Ddpll.c29 .set_rate = &omap3_noncore_dpll_set_rate,
54 .set_rate = &omap3_noncore_dpll_set_rate,
67 .set_rate = &omap3_noncore_dpll_set_rate,
86 .set_rate = &omap2_reprogram_dpllcore,
108 .set_rate = &omap3_noncore_dpll_set_rate,
120 .set_rate = &omap3_dpll5_set_rate,
132 .set_rate = &omap3_dpll4_set_rate,
/kernel/linux/linux-5.10/drivers/clk/mvebu/
H A Dclk-corediv.c203 .set_rate = clk_corediv_set_rate,
219 .set_rate = clk_corediv_set_rate,
232 .set_rate = clk_corediv_set_rate,
244 .set_rate = clk_corediv_set_rate,
/kernel/linux/linux-6.6/drivers/clk/mvebu/
H A Dclk-corediv.c203 .set_rate = clk_corediv_set_rate,
219 .set_rate = clk_corediv_set_rate,
232 .set_rate = clk_corediv_set_rate,
244 .set_rate = clk_corediv_set_rate,
/kernel/linux/linux-5.10/drivers/clk/st/
H A Dclk-flexgen.c177 clk_divider_ops.set_rate(pdiv_hw, parent_rate, parent_rate); in flexgen_set_rate()
178 ret = clk_divider_ops.set_rate(fdiv_hw, rate, rate * div); in flexgen_set_rate()
180 clk_divider_ops.set_rate(fdiv_hw, parent_rate, parent_rate); in flexgen_set_rate()
181 ret = clk_divider_ops.set_rate(pdiv_hw, rate, rate * div); in flexgen_set_rate()
195 .set_rate = flexgen_set_rate,
/kernel/linux/linux-5.10/drivers/sh/clk/
H A Dcpg.c182 .set_rate = sh_clk_div_set_rate,
188 .set_rate = sh_clk_div_set_rate,
315 .set_rate = sh_clk_div_set_rate,
367 .set_rate = sh_clk_div_set_rate,
447 .set_rate = fsidiv_set_rate,
/kernel/linux/linux-6.6/drivers/sh/clk/
H A Dcpg.c182 .set_rate = sh_clk_div_set_rate,
188 .set_rate = sh_clk_div_set_rate,
315 .set_rate = sh_clk_div_set_rate,
367 .set_rate = sh_clk_div_set_rate,
447 .set_rate = fsidiv_set_rate,
/kernel/linux/linux-5.10/arch/sh/kernel/cpu/sh4/
H A Dclock-sh4-202.c81 if (clk->ops->set_rate(clk, clk->parent->rate / divisor) == 0) in shoc_clk_init()
133 .set_rate = shoc_clk_set_rate,
/kernel/linux/linux-5.10/drivers/clk/mxs/
H A Dclk-div.c57 ret = div->ops->set_rate(&div->divider.hw, rate, parent_rate); in clk_div_set_rate()
67 .set_rate = clk_div_set_rate,
/kernel/linux/linux-6.6/arch/sh/kernel/cpu/sh4/
H A Dclock-sh4-202.c81 if (clk->ops->set_rate(clk, clk->parent->rate / divisor) == 0) in shoc_clk_init()
133 .set_rate = shoc_clk_set_rate,
/kernel/linux/linux-6.6/drivers/clk/mxs/
H A Dclk-div.c57 ret = div->ops->set_rate(&div->divider.hw, rate, parent_rate); in clk_div_set_rate()
67 .set_rate = clk_div_set_rate,
/kernel/linux/linux-5.10/include/linux/phy/
H A Dphy-dp.h67 * @set_rate:
73 u8 set_rate : 1; member
/kernel/linux/linux-6.6/include/linux/phy/
H A Dphy-dp.h67 * @set_rate:
73 u8 set_rate : 1; member
/kernel/linux/linux-5.10/drivers/clk/samsung/
H A Dclk-pll.c256 .set_rate = samsung_pll35xx_set_rate,
372 .set_rate = samsung_pll36xx_set_rate,
511 .set_rate = samsung_pll45xx_set_rate,
670 .set_rate = samsung_pll46xx_set_rate,
899 .set_rate = samsung_s3c2410_pll_set_rate,
907 .set_rate = samsung_s3c2410_pll_set_rate,
915 .set_rate = samsung_s3c2410_pll_set_rate,
1051 .set_rate = samsung_pll2550xx_set_rate,
1147 .set_rate = samsung_pll2650x_set_rate,
1241 .set_rate
[all...]
/kernel/linux/linux-6.6/drivers/clk/qcom/
H A Dclk-alpha-pll.c1034 .set_rate = clk_alpha_pll_set_rate,
1044 .set_rate = alpha_pll_huayra_set_rate,
1054 .set_rate = clk_alpha_pll_hwfsm_set_rate,
1149 .set_rate = clk_alpha_pll_postdiv_set_rate,
1394 .set_rate = alpha_pll_fabia_set_rate,
1489 .set_rate = clk_trion_pll_postdiv_set_rate,
1509 * If the PLL is in FSM mode, then treat set_rate callback as a in clk_alpha_pll_postdiv_fabia_set_rate()
1535 .set_rate = clk_alpha_pll_postdiv_fabia_set_rate,
1687 .set_rate = alpha_pll_trion_set_rate,
1698 .set_rate
[all...]
/kernel/linux/linux-5.10/drivers/clk/tegra/
H A Dclk-tegra-super-cclk.c44 return tegra_clk_super_ops.set_rate(hw, rate, parent_rate); in cclk_super_set_rate()
100 .set_rate = cclk_super_set_rate,
/kernel/linux/linux-6.6/drivers/clk/tegra/
H A Dclk-tegra-super-cclk.c46 return tegra_clk_super_ops.set_rate(hw, rate, parent_rate); in cclk_super_set_rate()
121 .set_rate = cclk_super_set_rate,

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