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Searched refs:reg_layout (Results 1 - 13 of 13) sorted by relevance

/kernel/linux/linux-6.6/drivers/soundwire/
H A Dqcom.c181 const unsigned int *reg_layout; member
221 const unsigned int *reg_layout; member
240 .reg_layout = swrm_v1_3_reg_layout,
247 .reg_layout = swrm_v1_3_reg_layout,
255 .reg_layout = swrm_v1_3_reg_layout,
275 .reg_layout = swrm_v2_0_reg_layout,
359 ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS], in swrm_wait_for_rd_fifo_avail()
385 ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS], in swrm_wait_for_wr_fifo_avail()
410 ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS], &value); in swrm_wait_for_wr_fifo_done()
416 ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATU in swrm_wait_for_wr_fifo_done()
[all...]
/kernel/linux/linux-6.6/drivers/tty/serial/8250/
H A D8250_dfl.c55 u64 fifo_len, clk_freq, reg_layout; in dfl_uart_get_params() local
86 ret = dfh_get_u64_param_val(dfl_dev, DFHv1_PARAM_ID_REG_LAYOUT, &reg_layout); in dfl_uart_get_params()
90 uart->port.regshift = FIELD_GET(DFHv1_PARAM_REG_LAYOUT_SHIFT, reg_layout); in dfl_uart_get_params()
91 reg_width = FIELD_GET(DFHv1_PARAM_REG_LAYOUT_WIDTH, reg_layout); in dfl_uart_get_params()
/kernel/linux/linux-5.10/drivers/clk/renesas/
H A Drenesas-cpg-mssr.c127 * @reg_layout: CPG/MSSR register layout
148 enum clk_reg_layout reg_layout; member
201 if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) { in cpg_mstp_clock_endisable()
223 if (!enable || priv->reg_layout == CLK_REG_LAYOUT_RZ_A) in cpg_mstp_clock_endisable()
257 if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) in cpg_mstp_clock_is_enabled()
296 if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) { in cpg_mssr_clk_src_twocell_get()
856 priv->reg_layout == CLK_REG_LAYOUT_RZ_A ? in cpg_mssr_suspend_noirq()
886 if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) in cpg_mssr_resume_noirq()
895 if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) { in cpg_mssr_resume_noirq()
966 priv->reg_layout in cpg_mssr_common_init()
[all...]
H A Drenesas-cpg-mssr.h114 * @reg_layout: CPG/MSSR register layout from enum clk_reg_layout
136 enum clk_reg_layout reg_layout; member
H A Dr7s9210-cpg-mssr.c217 .reg_layout = CLK_REG_LAYOUT_RZ_A,
H A Dr8a779a0-cpg-mssr.c281 .reg_layout = CLK_REG_LAYOUT_RCAR_V3U,
/kernel/linux/linux-6.6/drivers/dma/
H A Dhisi_dma.c164 enum hisi_dma_reg_layout reg_layout; member
369 if (hdma_dev->reg_layout == HISI_DMA_REG_LAYOUT_HIP08) in hisi_dma_mask_irq()
385 if (hdma_dev->reg_layout == HISI_DMA_REG_LAYOUT_HIP08) { in hisi_dma_unmask_irq()
638 if (hdma_dev->reg_layout == HISI_DMA_REG_LAYOUT_HIP08) { in hisi_dma_init_hw_qp()
803 if (hdma_dev->reg_layout == HISI_DMA_REG_LAYOUT_HIP08) in hisi_dma_set_mode()
813 if (hdma_dev->reg_layout == HISI_DMA_REG_LAYOUT_HIP09) { in hisi_dma_init_hw()
851 if (hdma_dev->reg_layout == HISI_DMA_REG_LAYOUT_HIP08) in hisi_dma_get_ch_regs()
862 if (hdma_dev->reg_layout == HISI_DMA_REG_LAYOUT_HIP08) in hisi_dma_get_ch_regs()
928 if (hdma_dev->reg_layout == HISI_DMA_REG_LAYOUT_HIP08) { in hisi_dma_create_debugfs()
952 enum hisi_dma_reg_layout reg_layout; in hisi_dma_probe() local
[all...]
/kernel/linux/linux-6.6/drivers/clk/renesas/
H A Drenesas-cpg-mssr.c132 * @reg_layout: CPG/MSSR register layout
153 enum clk_reg_layout reg_layout; member
206 if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) { in cpg_mstp_clock_endisable()
228 if (!enable || priv->reg_layout == CLK_REG_LAYOUT_RZ_A) in cpg_mstp_clock_endisable()
256 if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) in cpg_mstp_clock_is_enabled()
295 if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) { in cpg_mssr_clk_src_twocell_get()
879 priv->reg_layout == CLK_REG_LAYOUT_RZ_A ? in cpg_mssr_suspend_noirq()
910 if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) in cpg_mssr_resume_noirq()
919 if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) { in cpg_mssr_resume_noirq()
985 priv->reg_layout in cpg_mssr_common_init()
[all...]
H A Drenesas-cpg-mssr.h114 * @reg_layout: CPG/MSSR register layout from enum clk_reg_layout
136 enum clk_reg_layout reg_layout; member
H A Dr7s9210-cpg-mssr.c217 .reg_layout = CLK_REG_LAYOUT_RZ_A,
H A Dr8a779f0-cpg-mssr.c237 .reg_layout = CLK_REG_LAYOUT_RCAR_GEN4,
H A Dr8a779a0-cpg-mssr.c300 .reg_layout = CLK_REG_LAYOUT_RCAR_GEN4,
H A Dr8a779g0-cpg-mssr.c301 .reg_layout = CLK_REG_LAYOUT_RCAR_GEN4,

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