Lines Matching refs:reg_layout
181 const unsigned int *reg_layout;
221 const unsigned int *reg_layout;
240 .reg_layout = swrm_v1_3_reg_layout,
247 .reg_layout = swrm_v1_3_reg_layout,
255 .reg_layout = swrm_v1_3_reg_layout,
275 .reg_layout = swrm_v2_0_reg_layout,
359 ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS],
385 ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS],
410 ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS], &value);
416 ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS], &value);
454 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_WR_CMD], val);
494 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_RD_CMD], val);
502 ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_RD_FIFO_ADDR],
514 ctrl->reg_layout[SWRM_REG_CMD_FIFO_RD_CMD],
674 ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_STATUS],
714 ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN],
719 ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS],
727 ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS],
735 ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS],
744 ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS],
757 ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN],
767 ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN],
787 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CLEAR],
789 ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_STATUS],
836 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_MASK_ADDR],
873 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CLEAR],
878 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN],
1515 ctrl->reg_layout = data->reg_layout;
1710 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CLEAR],
1716 ctrl->reg_layout[SWRM_REG_INTERRUPT_MASK_ADDR],
1718 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN],
1744 ctrl->reg_layout[SWRM_REG_INTERRUPT_MASK_ADDR],
1746 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN],