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Searched refs:pll2 (Results 1 - 25 of 28) sorted by relevance

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/kernel/linux/linux-5.10/drivers/mfd/
H A Dsm501.c116 static unsigned long decode_div(unsigned long pll2, unsigned long val, in decode_div() argument
121 pll2 = 288 * MHZ; in decode_div()
123 return pll2 / div_tab[(val >> lshft) & mask]; in decode_div()
140 unsigned long pll2 = 0; in sm501_dump_clk() local
144 pll2 = 336 * MHZ; in sm501_dump_clk()
147 pll2 = 288 * MHZ; in sm501_dump_clk()
150 pll2 = 240 * MHZ; in sm501_dump_clk()
153 pll2 = 192 * MHZ; in sm501_dump_clk()
157 sdclk0 = (misct & (1<<12)) ? pll2 : 288 * MHZ; in sm501_dump_clk()
160 sdclk1 = (misct & (1<<20)) ? pll2 in sm501_dump_clk()
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/kernel/linux/linux-6.6/drivers/mfd/
H A Dsm501.c116 static unsigned long decode_div(unsigned long pll2, unsigned long val, in decode_div() argument
121 pll2 = 288 * MHZ; in decode_div()
123 return pll2 / div_tab[(val >> lshft) & mask]; in decode_div()
140 unsigned long pll2 = 0; in sm501_dump_clk() local
144 pll2 = 336 * MHZ; in sm501_dump_clk()
147 pll2 = 288 * MHZ; in sm501_dump_clk()
150 pll2 = 240 * MHZ; in sm501_dump_clk()
153 pll2 = 192 * MHZ; in sm501_dump_clk()
157 sdclk0 = (misct & (1<<12)) ? pll2 : 288 * MHZ; in sm501_dump_clk()
160 sdclk1 = (misct & (1<<20)) ? pll2 in sm501_dump_clk()
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/kernel/linux/linux-5.10/drivers/gpu/drm/hisilicon/hibmc/
H A Dhibmc_drm_de.c285 u32 *pll1, u32 *pll2) in get_pll_config()
294 *pll2 = hibmc_pll_table[i].pll2_config_value; in get_pll_config()
301 *pll2 = CRT_PLL2_HS_25MHZ; in get_pll_config()
317 u32 pll2; /* bit[63:32] of PLL */ in display_ctrl_adjust() local
323 get_pll_config(x, y, &pll1, &pll2); in display_ctrl_adjust()
324 writel(pll2, priv->mmio + CRT_PLL2_HS); in display_ctrl_adjust()
284 get_pll_config(unsigned long x, unsigned long y, u32 *pll1, u32 *pll2) get_pll_config() argument
/kernel/linux/linux-6.6/drivers/gpu/drm/hisilicon/hibmc/
H A Dhibmc_drm_de.c284 static void get_pll_config(u64 x, u64 y, u32 *pll1, u32 *pll2) in get_pll_config() argument
293 *pll2 = hibmc_pll_table[i].pll2_config_value; in get_pll_config()
300 *pll2 = CRT_PLL2_HS_25MHZ; in get_pll_config()
316 u32 pll2; /* bit[63:32] of PLL */ in display_ctrl_adjust() local
322 get_pll_config(x, y, &pll1, &pll2); in display_ctrl_adjust()
323 writel(pll2, priv->mmio + CRT_PLL2_HS); in display_ctrl_adjust()
/kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/
H A Dnv04.c208 uint32_t pll2 = (oldpll2 & 0x7fff0000) | 1 << 31 | pv->NM2; in setPLL_double_highregs() local
214 /* model specific additions to generic pll1 and pll2 set up above */ in setPLL_double_highregs()
218 pll2 = 0; in setPLL_double_highregs()
227 pll2 |= 0x011f; in setPLL_double_highregs()
233 if (oldpll1 == pll1 && oldpll2 == pll2) in setPLL_double_highregs()
266 nvkm_wr32(device, reg2, pll2); in setPLL_double_highregs()
/kernel/linux/linux-6.6/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/
H A Dnv04.c208 uint32_t pll2 = (oldpll2 & 0x7fff0000) | 1 << 31 | pv->NM2; in setPLL_double_highregs() local
214 /* model specific additions to generic pll1 and pll2 set up above */ in setPLL_double_highregs()
218 pll2 = 0; in setPLL_double_highregs()
227 pll2 |= 0x011f; in setPLL_double_highregs()
233 if (oldpll1 == pll1 && oldpll2 == pll2) in setPLL_double_highregs()
266 nvkm_wr32(device, reg2, pll2); in setPLL_double_highregs()
/kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/dispnv04/
H A Dhw.c133 uint32_t pll2, struct nvkm_pll_vals *pllvals) in nouveau_hw_decode_pll()
137 /* to force parsing as single stage (i.e. nv40 vplls) pass pll2 as 0 */ in nouveau_hw_decode_pll()
144 pllvals->NM1 = pll2 & 0xffff; in nouveau_hw_decode_pll()
147 pllvals->NM2 = pll2 >> 16; in nouveau_hw_decode_pll()
150 if (nv_two_reg_pll(dev) && pll2 & NV31_RAMDAC_ENABLE_VCO2) in nouveau_hw_decode_pll()
151 pllvals->NM2 = pll2 & 0xffff; in nouveau_hw_decode_pll()
170 uint32_t reg1, pll1, pll2 = 0; in nouveau_hw_get_pllvals() local
180 pll2 = nvif_rd32(device, reg1 + 4); in nouveau_hw_get_pllvals()
184 pll2 = nvif_rd32(device, reg2); in nouveau_hw_get_pllvals()
193 pll2 in nouveau_hw_get_pllvals()
132 nouveau_hw_decode_pll(struct drm_device *dev, uint32_t reg1, uint32_t pll1, uint32_t pll2, struct nvkm_pll_vals *pllvals) nouveau_hw_decode_pll() argument
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/kernel/linux/linux-6.6/drivers/gpu/drm/nouveau/dispnv04/
H A Dhw.c133 uint32_t pll2, struct nvkm_pll_vals *pllvals) in nouveau_hw_decode_pll()
137 /* to force parsing as single stage (i.e. nv40 vplls) pass pll2 as 0 */ in nouveau_hw_decode_pll()
144 pllvals->NM1 = pll2 & 0xffff; in nouveau_hw_decode_pll()
147 pllvals->NM2 = pll2 >> 16; in nouveau_hw_decode_pll()
150 if (nv_two_reg_pll(dev) && pll2 & NV31_RAMDAC_ENABLE_VCO2) in nouveau_hw_decode_pll()
151 pllvals->NM2 = pll2 & 0xffff; in nouveau_hw_decode_pll()
170 uint32_t reg1, pll1, pll2 = 0; in nouveau_hw_get_pllvals() local
180 pll2 = nvif_rd32(device, reg1 + 4); in nouveau_hw_get_pllvals()
184 pll2 = nvif_rd32(device, reg2); in nouveau_hw_get_pllvals()
193 pll2 in nouveau_hw_get_pllvals()
132 nouveau_hw_decode_pll(struct drm_device *dev, uint32_t reg1, uint32_t pll1, uint32_t pll2, struct nvkm_pll_vals *pllvals) nouveau_hw_decode_pll() argument
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/kernel/linux/linux-5.10/drivers/gpu/drm/tegra/
H A Dsor.c367 unsigned int pll2; member
1450 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_power_down()
1452 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_power_down()
1460 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_power_down()
1463 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_power_down()
2286 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_hdmi_enable()
2288 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_hdmi_enable()
2301 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_hdmi_enable()
2303 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_hdmi_enable()
2307 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_hdmi_enable()
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/kernel/linux/linux-6.6/drivers/gpu/drm/tegra/
H A Dsor.c367 unsigned int pll2; member
1451 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_power_down()
1453 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_power_down()
1461 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_power_down()
1464 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_power_down()
2282 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_hdmi_enable()
2284 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_hdmi_enable()
2297 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_hdmi_enable()
2299 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_hdmi_enable()
2303 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_hdmi_enable()
[all...]
/kernel/linux/linux-5.10/drivers/clk/mxs/
H A Dclk-imx28.c133 ref_xtal, pll0, pll1, pll2, ref_cpu, ref_emi, ref_io0, ref_io1, enumerator
170 clks[pll2] = mxs_clk_pll("pll2", "ref_xtal", PLL2CTRL0, 23, 50000000); in mx28_clocks_init()
231 clks[enet_out] = clk_register_gate(NULL, "enet_out", "pll2", 0, ENET, 18, 0, &mxs_lock); in mx28_clocks_init()
/kernel/linux/linux-6.6/drivers/clk/mxs/
H A Dclk-imx28.c133 ref_xtal, pll0, pll1, pll2, ref_cpu, ref_emi, ref_io0, ref_io1, enumerator
170 clks[pll2] = mxs_clk_pll("pll2", "ref_xtal", PLL2CTRL0, 23, 50000000); in mx28_clocks_init()
231 clks[enet_out] = clk_register_gate(NULL, "enet_out", "pll2", 0, ENET, 18, 0, &mxs_lock); in mx28_clocks_init()
/kernel/linux/linux-6.6/drivers/gpu/drm/i915/display/
H A Dintel_dpll_mgr.h207 u32 ebb0, ebb4, pll0, pll1, pll2, pll3, pll6, pll8, pll9, pll10, pcsdw12; member
H A Dintel_dpll_mgr.c1958 PORT_PLL_M2_FRAC_MASK, pll->state.hw_state.pll2); in bxt_ddi_pll_enable()
2073 hw_state->pll2 = intel_de_read(dev_priv, BXT_PORT_PLL(phy, ch, 2)); in bxt_ddi_pll_get_hw_state()
2074 hw_state->pll2 &= PORT_PLL_M2_FRAC_MASK; in bxt_ddi_pll_get_hw_state()
2213 dpll_hw_state->pll2 = PORT_PLL_M2_FRAC(clk_div->m2 & 0x3fffff); in bxt_ddi_set_dpll_hw_state()
2245 clock.m2 |= REG_FIELD_GET(PORT_PLL_M2_FRAC_MASK, pll_state->pll2); in bxt_ddi_pll_get_freq()
2333 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, " in bxt_dump_hw_state()
2339 hw_state->pll2, in bxt_dump_hw_state()
/kernel/linux/linux-6.6/drivers/media/i2c/
H A Dov7251.c109 const struct ov7251_pll2_cfg *pll2; member
218 .pll2 = &ov7251_pll2_cfg_19_2_mhz,
226 .pll2 = &ov7251_pll2_cfg_24_mhz,
840 configs->pll2->pre_div); in ov7251_pll_configure()
845 configs->pll2->mult); in ov7251_pll_configure()
850 configs->pll2->div); in ov7251_pll_configure()
855 configs->pll2->sys_div); in ov7251_pll_configure()
860 configs->pll2->adc_div); in ov7251_pll_configure()
/kernel/linux/linux-5.10/drivers/clk/sirf/
H A Dclk-prima2.c60 rtc, osc, pll1, pll2, pll3, mem, sys, security, dsp, gps, enumerator
H A Dclk-atlas6.c61 rtc, osc, pll1, pll2, pll3, mem, sys, security, dsp, gps, enumerator
/kernel/linux/linux-5.10/drivers/clk/sunxi/
H A Dclk-a10-pll2.c16 #include <dt-bindings/clock/sun4i-a10-pll2.h>
62 prediv_clk = clk_register_divider(NULL, "pll2-prediv", in sun4i_pll2_setup()
95 base_clk = clk_register_composite(NULL, "pll2-base", in sun4i_pll2_setup()
186 CLK_OF_DECLARE(sun4i_a10_pll2, "allwinner,sun4i-a10-pll2-clk",
194 CLK_OF_DECLARE(sun5i_a13_pll2, "allwinner,sun5i-a13-pll2-clk",
/kernel/linux/linux-5.10/drivers/gpu/drm/i915/display/
H A Dintel_dpll_mgr.h195 u32 ebb0, ebb4, pll0, pll1, pll2, pll3, pll6, pll8, pll9, pll10, pcsdw12; member
H A Dintel_dpll_mgr.c1871 temp |= pll->state.hw_state.pll2; in bxt_ddi_pll_enable()
1999 hw_state->pll2 = intel_de_read(dev_priv, BXT_PORT_PLL(phy, ch, 2)); in bxt_ddi_pll_get_hw_state()
2000 hw_state->pll2 &= PORT_PLL_M2_FRAC_MASK; in bxt_ddi_pll_get_hw_state()
2164 dpll_hw_state->pll2 = clk_div->m2_frac; in bxt_ddi_set_dpll_hw_state()
2216 clock.m2 |= pll_state->pll2 & PORT_PLL_M2_FRAC_MASK; in bxt_ddi_pll_get_freq()
2268 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, " in bxt_dump_hw_state()
2274 hw_state->pll2, in bxt_dump_hw_state()
/kernel/linux/linux-6.6/drivers/clk/sunxi/
H A Dclk-a10-pll2.c16 #include <dt-bindings/clock/sun4i-a10-pll2.h>
62 prediv_clk = clk_register_divider(NULL, "pll2-prediv", in sun4i_pll2_setup()
95 base_clk = clk_register_composite(NULL, "pll2-base", in sun4i_pll2_setup()
186 CLK_OF_DECLARE(sun4i_a10_pll2, "allwinner,sun4i-a10-pll2-clk",
194 CLK_OF_DECLARE(sun5i_a13_pll2, "allwinner,sun5i-a13-pll2-clk",
/kernel/linux/linux-5.10/sound/soc/codecs/
H A Dtscs454.c132 struct pll pll2; member
293 pll_init(&tscs454->pll2, 2); in tscs454_data_init()
440 mutex_lock(&tscs454->pll2.lock); in coeff_ram_put()
457 mutex_unlock(&tscs454->pll2.lock); in coeff_ram_put()
689 mutex_lock(&tscs454->pll2.lock); in pll_connected()
690 users = tscs454->pll2.users; in pll_connected()
691 mutex_unlock(&tscs454->pll2.lock); in pll_connected()
3184 aif->pll = &tscs454->pll2; in tscs454_hw_params()
3197 tscs454->internal_rate.pll = &tscs454->pll2; in tscs454_hw_params()
/kernel/linux/linux-6.6/sound/soc/codecs/
H A Dtscs454.c132 struct pll pll2; member
293 pll_init(&tscs454->pll2, 2); in tscs454_data_init()
440 mutex_lock(&tscs454->pll2.lock); in coeff_ram_put()
457 mutex_unlock(&tscs454->pll2.lock); in coeff_ram_put()
689 mutex_lock(&tscs454->pll2.lock); in pll_connected()
690 users = tscs454->pll2.users; in pll_connected()
691 mutex_unlock(&tscs454->pll2.lock); in pll_connected()
3189 aif->pll = &tscs454->pll2; in tscs454_hw_params()
3202 tscs454->internal_rate.pll = &tscs454->pll2; in tscs454_hw_params()
/kernel/linux/linux-5.10/arch/arm/mach-davinci/
H A Ddm365.c778 void __iomem *pll1, *pll2, *psc; in dm365_init_time() local
787 pll2 = ioremap(DAVINCI_PLL2_BASE, SZ_1K); in dm365_init_time()
788 dm365_pll2_init(NULL, pll2, NULL); in dm365_init_time()
/kernel/linux/linux-6.6/drivers/clk/qcom/
H A Dmmcc-msm8960.c44 static struct clk_pll pll2 = { variable
53 .name = "pll2",
103 { .hw = &pll2.clkr.hw },
116 { .hw = &pll2.clkr.hw },
130 { .hw = &pll2.clkr.hw },
2801 [PLL2] = &pll2.clkr,
2977 [PLL2] = &pll2.clkr,

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