Lines Matching refs:pll2
133 uint32_t pll2, struct nvkm_pll_vals *pllvals)
137 /* to force parsing as single stage (i.e. nv40 vplls) pass pll2 as 0 */
144 pllvals->NM1 = pll2 & 0xffff;
147 pllvals->NM2 = pll2 >> 16;
150 if (nv_two_reg_pll(dev) && pll2 & NV31_RAMDAC_ENABLE_VCO2)
151 pllvals->NM2 = pll2 & 0xffff;
170 uint32_t reg1, pll1, pll2 = 0;
180 pll2 = nvif_rd32(device, reg1 + 4);
184 pll2 = nvif_rd32(device, reg2);
193 pll2 = 0;
196 pll2 = 0;
199 nouveau_hw_decode_pll(dev, reg1, pll1, pll2, pllvals);