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Searched refs:pll1 (Results 1 - 25 of 28) sorted by relevance

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/kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/
H A Dnv04.c207 uint32_t pll1 = (oldpll1 & 0xfff80000) | pv->log2P << 16 | pv->NM1; in setPLL_double_highregs() local
214 /* model specific additions to generic pll1 and pll2 set up above */ in setPLL_double_highregs()
216 pll1 = (pll1 & 0xfcc7ffff) | (pv->N2 & 0x18) << 21 | in setPLL_double_highregs()
231 pll1 = (pll1 & 0x7fffffff) | (single_stage ? 0x4 : 0xc) << 28; in setPLL_double_highregs()
233 if (oldpll1 == pll1 && oldpll2 == pll2) in setPLL_double_highregs()
267 nvkm_wr32(device, reg1, pll1); in setPLL_double_highregs()
/kernel/linux/linux-6.6/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/
H A Dnv04.c207 uint32_t pll1 = (oldpll1 & 0xfff80000) | pv->log2P << 16 | pv->NM1; in setPLL_double_highregs() local
214 /* model specific additions to generic pll1 and pll2 set up above */ in setPLL_double_highregs()
216 pll1 = (pll1 & 0xfcc7ffff) | (pv->N2 & 0x18) << 21 | in setPLL_double_highregs()
231 pll1 = (pll1 & 0x7fffffff) | (single_stage ? 0x4 : 0xc) << 28; in setPLL_double_highregs()
233 if (oldpll1 == pll1 && oldpll2 == pll2) in setPLL_double_highregs()
267 nvkm_wr32(device, reg1, pll1); in setPLL_double_highregs()
/kernel/linux/linux-5.10/drivers/gpu/drm/hisilicon/hibmc/
H A Dhibmc_drm_de.c285 u32 *pll1, u32 *pll2) in get_pll_config()
293 *pll1 = hibmc_pll_table[i].pll1_config_value; in get_pll_config()
300 *pll1 = CRT_PLL1_HS_25MHZ; in get_pll_config()
316 u32 pll1; /* bit[31:0] of PLL */ in display_ctrl_adjust() local
323 get_pll_config(x, y, &pll1, &pll2); in display_ctrl_adjust()
325 set_vclock_hisilicon(dev, pll1); in display_ctrl_adjust()
284 get_pll_config(unsigned long x, unsigned long y, u32 *pll1, u32 *pll2) get_pll_config() argument
/kernel/linux/linux-6.6/drivers/gpu/drm/hisilicon/hibmc/
H A Dhibmc_drm_de.c284 static void get_pll_config(u64 x, u64 y, u32 *pll1, u32 *pll2) in get_pll_config() argument
292 *pll1 = hibmc_pll_table[i].pll1_config_value; in get_pll_config()
299 *pll1 = CRT_PLL1_HS_25MHZ; in get_pll_config()
315 u32 pll1; /* bit[31:0] of PLL */ in display_ctrl_adjust() local
322 get_pll_config(x, y, &pll1, &pll2); in display_ctrl_adjust()
324 set_vclock_hisilicon(dev, pll1); in display_ctrl_adjust()
/kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/dispnv04/
H A Dhw.c132 nouveau_hw_decode_pll(struct drm_device *dev, uint32_t reg1, uint32_t pll1, in nouveau_hw_decode_pll() argument
140 pllvals->log2P = (pll1 >> 16) & 0x7; in nouveau_hw_decode_pll()
146 if (!(pll1 & 0x1100)) in nouveau_hw_decode_pll()
149 pllvals->NM1 = pll1 & 0xffff; in nouveau_hw_decode_pll()
154 if (pll1 & NV30_RAMDAC_ENABLE_VCO2) { in nouveau_hw_decode_pll()
155 pllvals->M2 = (pll1 >> 4) & 0x7; in nouveau_hw_decode_pll()
156 pllvals->N2 = ((pll1 >> 21) & 0x18) | in nouveau_hw_decode_pll()
157 ((pll1 >> 19) & 0x7); in nouveau_hw_decode_pll()
170 uint32_t reg1, pll1, pll2 = 0; in nouveau_hw_get_pllvals() local
178 pll1 in nouveau_hw_get_pllvals()
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/nouveau/dispnv04/
H A Dhw.c132 nouveau_hw_decode_pll(struct drm_device *dev, uint32_t reg1, uint32_t pll1, in nouveau_hw_decode_pll() argument
140 pllvals->log2P = (pll1 >> 16) & 0x7; in nouveau_hw_decode_pll()
146 if (!(pll1 & 0x1100)) in nouveau_hw_decode_pll()
149 pllvals->NM1 = pll1 & 0xffff; in nouveau_hw_decode_pll()
154 if (pll1 & NV30_RAMDAC_ENABLE_VCO2) { in nouveau_hw_decode_pll()
155 pllvals->M2 = (pll1 >> 4) & 0x7; in nouveau_hw_decode_pll()
156 pllvals->N2 = ((pll1 >> 21) & 0x18) | in nouveau_hw_decode_pll()
157 ((pll1 >> 19) & 0x7); in nouveau_hw_decode_pll()
170 uint32_t reg1, pll1, pll2 = 0; in nouveau_hw_get_pllvals() local
178 pll1 in nouveau_hw_get_pllvals()
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/kernel/linux/linux-5.10/drivers/gpu/drm/tegra/
H A Dhdmi.c37 u32 pll1; member
132 .pll1 = SOR_PLL_TMDS_TERM_ENABLE,
147 .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
165 .pll1 = SOR_PLL_TMDS_TERM_ENABLE,
179 .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
193 .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
210 .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(0),
228 .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) |
247 .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) |
266 .pll1
[all...]
H A Dsor.c366 unsigned int pll1; member
769 value = tegra_sor_readl(sor, sor->soc->regs->pll1); in tegra_sor_dp_term_calibrate()
771 tegra_sor_writel(sor, value, sor->soc->regs->pll1); in tegra_sor_dp_term_calibrate()
776 value = tegra_sor_readl(sor, sor->soc->regs->pll1); in tegra_sor_dp_term_calibrate()
779 tegra_sor_writel(sor, value, sor->soc->regs->pll1); in tegra_sor_dp_term_calibrate()
783 value = tegra_sor_readl(sor, sor->soc->regs->pll1); in tegra_sor_dp_term_calibrate()
790 value = tegra_sor_readl(sor, sor->soc->regs->pll1); in tegra_sor_dp_term_calibrate()
793 tegra_sor_writel(sor, value, sor->soc->regs->pll1); in tegra_sor_dp_term_calibrate()
900 value = tegra_sor_readl(sor, sor->soc->regs->pll1); in tegra_sor_dp_link_configure()
917 tegra_sor_writel(sor, value, sor->soc->regs->pll1); in tegra_sor_dp_link_configure()
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/tegra/
H A Dhdmi.c43 u32 pll1; member
141 .pll1 = SOR_PLL_TMDS_TERM_ENABLE,
156 .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
174 .pll1 = SOR_PLL_TMDS_TERM_ENABLE,
188 .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
202 .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
219 .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(0),
237 .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) |
256 .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) |
275 .pll1
[all...]
H A Dsor.c366 unsigned int pll1; member
770 value = tegra_sor_readl(sor, sor->soc->regs->pll1); in tegra_sor_dp_term_calibrate()
772 tegra_sor_writel(sor, value, sor->soc->regs->pll1); in tegra_sor_dp_term_calibrate()
777 value = tegra_sor_readl(sor, sor->soc->regs->pll1); in tegra_sor_dp_term_calibrate()
780 tegra_sor_writel(sor, value, sor->soc->regs->pll1); in tegra_sor_dp_term_calibrate()
784 value = tegra_sor_readl(sor, sor->soc->regs->pll1); in tegra_sor_dp_term_calibrate()
791 value = tegra_sor_readl(sor, sor->soc->regs->pll1); in tegra_sor_dp_term_calibrate()
794 tegra_sor_writel(sor, value, sor->soc->regs->pll1); in tegra_sor_dp_term_calibrate()
901 value = tegra_sor_readl(sor, sor->soc->regs->pll1); in tegra_sor_dp_link_configure()
918 tegra_sor_writel(sor, value, sor->soc->regs->pll1); in tegra_sor_dp_link_configure()
[all...]
/kernel/linux/linux-5.10/drivers/clk/sirf/
H A Dclk-prima2.c60 rtc, osc, pll1, pll2, pll3, mem, sys, security, dsp, gps, enumerator
135 for (i = pll1; i < maxclk; i++) { in prima2_clk_init()
H A Dclk-atlas6.c61 rtc, osc, pll1, pll2, pll3, mem, sys, security, dsp, gps, enumerator
136 for (i = pll1; i < maxclk; i++) { in atlas6_clk_init()
/kernel/linux/linux-5.10/sound/soc/codecs/
H A Dtscs454.c131 struct pll pll1; member
292 pll_init(&tscs454->pll1, 1); in tscs454_data_init()
439 mutex_lock(&tscs454->pll1.lock); in coeff_ram_put()
458 mutex_unlock(&tscs454->pll1.lock); in coeff_ram_put()
683 mutex_lock(&tscs454->pll1.lock); in pll_connected()
684 users = tscs454->pll1.users; in pll_connected()
685 mutex_unlock(&tscs454->pll1.lock); in pll_connected()
710 bool pll1; in pll_power_event() local
716 pll1 = true; in pll_power_event()
718 pll1 in pll_power_event()
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/kernel/linux/linux-6.6/sound/soc/codecs/
H A Dtscs454.c131 struct pll pll1; member
292 pll_init(&tscs454->pll1, 1); in tscs454_data_init()
439 mutex_lock(&tscs454->pll1.lock); in coeff_ram_put()
458 mutex_unlock(&tscs454->pll1.lock); in coeff_ram_put()
683 mutex_lock(&tscs454->pll1.lock); in pll_connected()
684 users = tscs454->pll1.users; in pll_connected()
685 mutex_unlock(&tscs454->pll1.lock); in pll_connected()
710 bool pll1; in pll_power_event() local
716 pll1 = true; in pll_power_event()
718 pll1 in pll_power_event()
[all...]
/kernel/linux/linux-5.10/arch/arm/mach-davinci/
H A Ddm644x.c670 void __iomem *pll1, *psc; in dm644x_init_time() local
676 pll1 = ioremap(DAVINCI_PLL1_BASE, SZ_1K); in dm644x_init_time()
677 dm644x_pll1_init(NULL, pll1, NULL); in dm644x_init_time()
H A Ddm646x.c653 void __iomem *pll1, *psc; in dm646x_init_time() local
660 pll1 = ioremap(DAVINCI_PLL1_BASE, SZ_1K); in dm646x_init_time()
661 dm646x_pll1_init(NULL, pll1, NULL); in dm646x_init_time()
H A Ddm355.c734 void __iomem *pll1, *psc; in dm355_init_time() local
740 pll1 = ioremap(DAVINCI_PLL1_BASE, SZ_1K); in dm355_init_time()
741 dm355_pll1_init(NULL, pll1, NULL); in dm355_init_time()
H A Ddm365.c778 void __iomem *pll1, *pll2, *psc; in dm365_init_time() local
784 pll1 = ioremap(DAVINCI_PLL1_BASE, SZ_1K); in dm365_init_time()
785 dm365_pll1_init(NULL, pll1, NULL); in dm365_init_time()
993 /* set sysclk4 to output 74.25 MHz from pll1 */ in dm365_venc_setup_clock()
/kernel/linux/linux-5.10/drivers/clk/mxs/
H A Dclk-imx28.c133 ref_xtal, pll0, pll1, pll2, ref_cpu, ref_emi, ref_io0, ref_io1, enumerator
169 clks[pll1] = mxs_clk_pll("pll1", "ref_xtal", PLL1CTRL0, 17, 480000000); in mx28_clocks_init()
230 clks[usb1_phy] = clk_register_gate(NULL, "usb1_phy", "pll1", 0, PLL1CTRL0, 18, 0, &mxs_lock); in mx28_clocks_init()
/kernel/linux/linux-6.6/drivers/clk/mxs/
H A Dclk-imx28.c133 ref_xtal, pll0, pll1, pll2, ref_cpu, ref_emi, ref_io0, ref_io1, enumerator
169 clks[pll1] = mxs_clk_pll("pll1", "ref_xtal", PLL1CTRL0, 17, 480000000); in mx28_clocks_init()
230 clks[usb1_phy] = clk_register_gate(NULL, "usb1_phy", "pll1", 0, PLL1CTRL0, 18, 0, &mxs_lock); in mx28_clocks_init()
/kernel/linux/linux-6.6/drivers/gpu/drm/i915/display/
H A Dintel_dpll_mgr.h207 u32 ebb0, ebb4, pll0, pll1, pll2, pll3, pll6, pll8, pll9, pll10, pcsdw12; member
/kernel/linux/linux-6.6/drivers/media/i2c/
H A Dov7251.c110 const struct ov7251_pll1_cfg *pll1[]; member
219 .pll1 = {
227 .pll1 = {
816 configs->pll1[ov7251->link_freq_idx]->pre_div); in ov7251_pll_configure()
821 configs->pll1[ov7251->link_freq_idx]->mult); in ov7251_pll_configure()
825 configs->pll1[ov7251->link_freq_idx]->div); in ov7251_pll_configure()
830 configs->pll1[ov7251->link_freq_idx]->pix_div); in ov7251_pll_configure()
835 configs->pll1[ov7251->link_freq_idx]->mipi_div); in ov7251_pll_configure()
/kernel/linux/linux-5.10/drivers/gpu/drm/i915/display/
H A Dintel_dpll_mgr.h195 u32 ebb0, ebb4, pll0, pll1, pll2, pll3, pll6, pll8, pll9, pll10, pcsdw12; member
H A Dintel_dpll_mgr.c1865 temp |= pll->state.hw_state.pll1; in bxt_ddi_pll_enable()
1996 hw_state->pll1 = intel_de_read(dev_priv, BXT_PORT_PLL(phy, ch, 1)); in bxt_ddi_pll_get_hw_state()
1997 hw_state->pll1 &= PORT_PLL_N_MASK; in bxt_ddi_pll_get_hw_state()
2163 dpll_hw_state->pll1 = PORT_PLL_N(clk_div->n); in bxt_ddi_set_dpll_hw_state()
2217 clock.n = (pll_state->pll1 & PORT_PLL_N_MASK) >> PORT_PLL_N_SHIFT; in bxt_ddi_pll_get_freq()
2268 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, " in bxt_dump_hw_state()
2273 hw_state->pll1, in bxt_dump_hw_state()
/kernel/linux/linux-6.6/drivers/clk/
H A Dclk-k210.c582 ret = k210_register_pll(np, ksc, K210_PLL1, "pll1", 1, &k210_pll_ops); in k210_register_plls()
1002 struct k210_pll pll1; in k210_clk_early_init() local
1008 k210_init_pll(regs, K210_PLL1, &pll1); in k210_clk_early_init()
1009 k210_pll_enable_hw(regs, &pll1); in k210_clk_early_init()

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