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Searched refs:phy_write (Results 1 - 25 of 168) sorted by relevance

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/kernel/linux/linux-5.10/drivers/net/phy/
H A Dvitesse.c94 err = phy_write(phydev, MII_VSC8244_EXT_CON1, extcon); in vsc824x_add_skew()
103 err = phy_write(phydev, MII_VSC8244_AUX_CONSTAT, in vsc824x_config_init()
129 phy_write(phydev, 0x1f, 0x2a30); in vsc73xx_config_init()
131 phy_write(phydev, 0x1f, 0x0000); in vsc73xx_config_init()
145 phy_write(phydev, 0x1f, 0x2a30); in vsc738x_config_init()
147 phy_write(phydev, 0x1f, 0x52b5); in vsc738x_config_init()
148 phy_write(phydev, 0x10, 0xb68a); in vsc738x_config_init()
151 phy_write(phydev, 0x10, 0x968a); in vsc738x_config_init()
152 phy_write(phydev, 0x1f, 0x2a30); in vsc738x_config_init()
154 phy_write(phyde in vsc738x_config_init()
[all...]
H A Dnational.c56 phy_write(phydev, NS_EXP_MEM_ADD, reg); in ns_exp_read()
62 phy_write(phydev, NS_EXP_MEM_ADD, reg); in ns_exp_write()
63 phy_write(phydev, NS_EXP_MEM_DATA, data); in ns_exp_write()
71 err = phy_write(phydev, DP83865_INT_MASK, in ns_config_intr()
74 err = phy_write(phydev, DP83865_INT_MASK, 0); in ns_config_intr()
87 ret = phy_write(phydev, DP83865_INT_CLEAR, ret & ~0x7); in ns_ack_interrupt()
96 phy_write(phydev, MII_BMCR, (bmcr | BMCR_PDOWN)); in ns_giga_speed_fallback()
99 phy_write(phydev, NS_EXP_MEM_CTL, 0); in ns_giga_speed_fallback()
100 phy_write(phydev, NS_EXP_MEM_ADD, 0x1C0); in ns_giga_speed_fallback()
101 phy_write(phyde in ns_giga_speed_fallback()
[all...]
H A Drockchip.c47 ret = phy_write(phydev, SMI_ADDR_TSTCNTL, TSTMODE_ENABLE); in rockchip_init_tstmode()
51 ret = phy_write(phydev, SMI_ADDR_TSTCNTL, TSTMODE_DISABLE); in rockchip_init_tstmode()
55 return phy_write(phydev, SMI_ADDR_TSTCNTL, TSTMODE_ENABLE); in rockchip_init_tstmode()
61 return phy_write(phydev, SMI_ADDR_TSTCNTL, TSTMODE_DISABLE); in rockchip_close_tstmode()
76 ret = phy_write(phydev, SMI_ADDR_TSTWRITE, 0xB); in rockchip_integrated_phy_analog_init()
79 ret = phy_write(phydev, SMI_ADDR_TSTCNTL, TSTCNTL_WR | WR_ADDR_A7CFG); in rockchip_integrated_phy_analog_init()
98 ret = phy_write(phydev, MII_INTERNAL_CTRL_STATUS, val); in rockchip_integrated_phy_config_init()
147 err = phy_write(phydev, MII_INTERNAL_CTRL_STATUS, val); in rockchip_set_polarity()
H A Dbcm7xxx.c80 phy_write(phydev, MII_BRCM_CORE_BASE1E, 0x0010); in bcm7xxx_28nm_d0_afe_config_init()
108 phy_write(phydev, MII_BRCM_CORE_BASE1E, 0x0010); in bcm7xxx_28nm_e0_plus_afe_config_init()
266 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_BIAS_TRIM, 0x3BE0); in bcm7xxx_28nm_ephy_01_afe_config_init()
271 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL, in bcm7xxx_28nm_ephy_01_afe_config_init()
281 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL, in bcm7xxx_28nm_ephy_01_afe_config_init()
337 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL, in bcm7xxx_28nm_ephy_eee_enable()
341 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_CTRL_STAT, in bcm7xxx_28nm_ephy_eee_enable()
347 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL, in bcm7xxx_28nm_ephy_eee_enable()
351 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_CTRL_STAT, in bcm7xxx_28nm_ephy_eee_enable()
356 ret = phy_write(phyde in bcm7xxx_28nm_ephy_eee_enable()
[all...]
H A Dmeson-gxl.c55 ret = phy_write(phydev, TSTCNTL, 0); in meson_gxl_open_banks()
58 ret = phy_write(phydev, TSTCNTL, TSTCNTL_TEST_MODE); in meson_gxl_open_banks()
61 ret = phy_write(phydev, TSTCNTL, 0); in meson_gxl_open_banks()
64 return phy_write(phydev, TSTCNTL, TSTCNTL_TEST_MODE); in meson_gxl_open_banks()
69 phy_write(phydev, TSTCNTL, 0); in meson_gxl_close_banks()
81 ret = phy_write(phydev, TSTCNTL, TSTCNTL_READ | in meson_gxl_read_reg()
105 ret = phy_write(phydev, TSTWRITE, value); in meson_gxl_write_reg()
109 ret = phy_write(phydev, TSTCNTL, TSTCNTL_WRITE | in meson_gxl_write_reg()
222 return phy_write(phydev, INTSRC_MASK, val); in meson_gxl_config_intr()
H A Dmicrochip.c40 rc = phy_write(phydev, LAN88XX_INT_MASK, 0x7FFF); in lan88xx_phy_config_intr()
42 rc = phy_write(phydev, LAN88XX_INT_MASK, in lan88xx_phy_config_intr()
46 rc = phy_write(phydev, LAN88XX_INT_MASK, 0); in lan88xx_phy_config_intr()
244 (void)phy_write(phydev, LAN78XX_PHY_LED_MODE_SELECT, reg); in lan88xx_probe()
296 phy_write(phydev, LAN88XX_EXT_PAGE_ACCESS, LAN88XX_EXT_PAGE_SPACE_1); in lan88xx_set_mdix()
300 phy_write(phydev, LAN88XX_EXT_MODE_CTRL, buf); in lan88xx_set_mdix()
301 phy_write(phydev, LAN88XX_EXT_PAGE_ACCESS, LAN88XX_EXT_PAGE_SPACE_0); in lan88xx_set_mdix()
342 phy_write(phydev, LAN88XX_INT_MASK, temp); in lan88xx_link_change_notify()
346 phy_write(phydev, MII_BMCR, temp); /* set to 10 first */ in lan88xx_link_change_notify()
348 phy_write(phyde in lan88xx_link_change_notify()
[all...]
H A Ddp83tc811.c213 err = phy_write(phydev, MII_DP83811_INT_STAT1, misr_status); in dp83811_config_intr()
228 err = phy_write(phydev, MII_DP83811_INT_STAT2, misr_status); in dp83811_config_intr()
240 err = phy_write(phydev, MII_DP83811_INT_STAT3, misr_status); in dp83811_config_intr()
243 err = phy_write(phydev, MII_DP83811_INT_STAT1, 0); in dp83811_config_intr()
247 err = phy_write(phydev, MII_DP83811_INT_STAT2, 0); in dp83811_config_intr()
251 err = phy_write(phydev, MII_DP83811_INT_STAT3, 0); in dp83811_config_intr()
264 err = phy_write(phydev, MII_DP83811_SGMII_CTRL, in dp83811_config_aneg()
269 err = phy_write(phydev, MII_DP83811_SGMII_CTRL, in dp83811_config_aneg()
285 err = phy_write(phydev, MII_DP83811_SGMII_CTRL, in dp83811_config_init()
288 err = phy_write(phyde in dp83811_config_init()
[all...]
H A Ddavicom.c75 temp = phy_write(phydev, MII_DM9161_INTR, temp); in dm9161_config_intr()
85 err = phy_write(phydev, MII_BMCR, BMCR_ISOLATE); in dm9161_config_aneg()
104 err = phy_write(phydev, MII_BMCR, BMCR_ISOLATE); in dm9161_config_init()
121 err = phy_write(phydev, MII_DM9161_SCR, temp); in dm9161_config_init()
126 err = phy_write(phydev, MII_DM9161_10BTCSR, MII_DM9161_10BTCSR_INIT); in dm9161_config_init()
132 return phy_write(phydev, MII_BMCR, BMCR_ANENABLE); in dm9161_config_init()
/kernel/linux/linux-6.6/drivers/net/phy/
H A Dvitesse.c99 err = phy_write(phydev, MII_VSC8244_EXT_CON1, extcon); in vsc824x_add_skew()
108 err = phy_write(phydev, MII_VSC8244_AUX_CONSTAT, in vsc824x_config_init()
134 phy_write(phydev, 0x1f, 0x2a30); in vsc73xx_config_init()
136 phy_write(phydev, 0x1f, 0x0000); in vsc73xx_config_init()
150 phy_write(phydev, 0x1f, 0x2a30); in vsc738x_config_init()
152 phy_write(phydev, 0x1f, 0x52b5); in vsc738x_config_init()
153 phy_write(phydev, 0x10, 0xb68a); in vsc738x_config_init()
156 phy_write(phydev, 0x10, 0x968a); in vsc738x_config_init()
157 phy_write(phydev, 0x1f, 0x2a30); in vsc738x_config_init()
159 phy_write(phyde in vsc738x_config_init()
[all...]
H A Dnational.c54 phy_write(phydev, NS_EXP_MEM_ADD, reg); in ns_exp_read()
60 phy_write(phydev, NS_EXP_MEM_ADD, reg); in ns_exp_write()
61 phy_write(phydev, NS_EXP_MEM_DATA, data); in ns_exp_write()
73 ret = phy_write(phydev, DP83865_INT_CLEAR, ret & ~0x7); in ns_ack_interrupt()
92 phy_write(phydev, DP83865_INT_CLEAR, irq_status & ~0x7); in ns_handle_interrupt()
108 err = phy_write(phydev, DP83865_INT_MASK, in ns_config_intr()
111 err = phy_write(phydev, DP83865_INT_MASK, 0); in ns_config_intr()
125 phy_write(phydev, MII_BMCR, (bmcr | BMCR_PDOWN)); in ns_giga_speed_fallback()
128 phy_write(phydev, NS_EXP_MEM_CTL, 0); in ns_giga_speed_fallback()
129 phy_write(phyde in ns_giga_speed_fallback()
[all...]
H A Drockchip.c47 ret = phy_write(phydev, SMI_ADDR_TSTCNTL, TSTMODE_ENABLE); in rockchip_init_tstmode()
51 ret = phy_write(phydev, SMI_ADDR_TSTCNTL, TSTMODE_DISABLE); in rockchip_init_tstmode()
55 return phy_write(phydev, SMI_ADDR_TSTCNTL, TSTMODE_ENABLE); in rockchip_init_tstmode()
61 return phy_write(phydev, SMI_ADDR_TSTCNTL, TSTMODE_DISABLE); in rockchip_close_tstmode()
76 ret = phy_write(phydev, SMI_ADDR_TSTWRITE, 0xB); in rockchip_integrated_phy_analog_init()
79 ret = phy_write(phydev, SMI_ADDR_TSTCNTL, TSTCNTL_WR | WR_ADDR_A7CFG); in rockchip_integrated_phy_analog_init()
98 ret = phy_write(phydev, MII_INTERNAL_CTRL_STATUS, val); in rockchip_integrated_phy_config_init()
147 err = phy_write(phydev, MII_INTERNAL_CTRL_STATUS, val); in rockchip_set_polarity()
H A Dmeson-gxl.c48 ret = phy_write(phydev, TSTCNTL, 0); in meson_gxl_open_banks()
51 ret = phy_write(phydev, TSTCNTL, TSTCNTL_TEST_MODE); in meson_gxl_open_banks()
54 ret = phy_write(phydev, TSTCNTL, 0); in meson_gxl_open_banks()
57 return phy_write(phydev, TSTCNTL, TSTCNTL_TEST_MODE); in meson_gxl_open_banks()
62 phy_write(phydev, TSTCNTL, 0); in meson_gxl_close_banks()
74 ret = phy_write(phydev, TSTCNTL, TSTCNTL_READ | in meson_gxl_read_reg()
98 ret = phy_write(phydev, TSTWRITE, value); in meson_gxl_write_reg()
102 ret = phy_write(phydev, TSTCNTL, TSTCNTL_WRITE | in meson_gxl_write_reg()
H A Ddp83tc811.c217 err = phy_write(phydev, MII_DP83811_INT_STAT1, misr_status); in dp83811_config_intr()
232 err = phy_write(phydev, MII_DP83811_INT_STAT2, misr_status); in dp83811_config_intr()
244 err = phy_write(phydev, MII_DP83811_INT_STAT3, misr_status); in dp83811_config_intr()
247 err = phy_write(phydev, MII_DP83811_INT_STAT1, 0); in dp83811_config_intr()
251 err = phy_write(phydev, MII_DP83811_INT_STAT2, 0); in dp83811_config_intr()
255 err = phy_write(phydev, MII_DP83811_INT_STAT3, 0); in dp83811_config_intr()
316 err = phy_write(phydev, MII_DP83811_SGMII_CTRL, in dp83811_config_aneg()
321 err = phy_write(phydev, MII_DP83811_SGMII_CTRL, in dp83811_config_aneg()
337 err = phy_write(phydev, MII_DP83811_SGMII_CTRL, in dp83811_config_init()
340 err = phy_write(phyde in dp83811_config_init()
[all...]
H A Dmicrochip.c40 rc = phy_write(phydev, LAN88XX_INT_MASK, 0x7FFF); in lan88xx_phy_config_intr()
42 rc = phy_write(phydev, LAN88XX_INT_MASK, in lan88xx_phy_config_intr()
46 rc = phy_write(phydev, LAN88XX_INT_MASK, 0); in lan88xx_phy_config_intr()
260 (void)phy_write(phydev, LAN78XX_PHY_LED_MODE_SELECT, reg); in lan88xx_probe()
312 phy_write(phydev, LAN88XX_EXT_PAGE_ACCESS, LAN88XX_EXT_PAGE_SPACE_1); in lan88xx_set_mdix()
316 phy_write(phydev, LAN88XX_EXT_MODE_CTRL, buf); in lan88xx_set_mdix()
317 phy_write(phydev, LAN88XX_EXT_PAGE_ACCESS, LAN88XX_EXT_PAGE_SPACE_0); in lan88xx_set_mdix()
358 phy_write(phydev, LAN88XX_INT_MASK, temp); in lan88xx_link_change_notify()
362 phy_write(phydev, MII_BMCR, temp); /* set to 10 first */ in lan88xx_link_change_notify()
364 phy_write(phyde in lan88xx_link_change_notify()
[all...]
H A Dbcm7xxx.c79 phy_write(phydev, MII_BRCM_CORE_BASE1E, 0x0010); in bcm7xxx_28nm_d0_afe_config_init()
107 phy_write(phydev, MII_BRCM_CORE_BASE1E, 0x0010); in bcm7xxx_28nm_e0_plus_afe_config_init()
265 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_BIAS_TRIM, 0x3BE0); in bcm7xxx_28nm_ephy_01_afe_config_init()
270 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL, in bcm7xxx_28nm_ephy_01_afe_config_init()
280 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL, in bcm7xxx_28nm_ephy_01_afe_config_init()
336 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL, in bcm7xxx_28nm_ephy_eee_enable()
340 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_CTRL_STAT, in bcm7xxx_28nm_ephy_eee_enable()
346 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL, in bcm7xxx_28nm_ephy_eee_enable()
350 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_CTRL_STAT, in bcm7xxx_28nm_ephy_eee_enable()
355 ret = phy_write(phyde in bcm7xxx_28nm_ephy_eee_enable()
[all...]
H A Ddavicom.c87 err = phy_write(phydev, MII_DM9161_INTR, temp); in dm9161_config_intr()
90 err = phy_write(phydev, MII_DM9161_INTR, temp); in dm9161_config_intr()
123 err = phy_write(phydev, MII_BMCR, BMCR_ISOLATE); in dm9161_config_aneg()
142 err = phy_write(phydev, MII_BMCR, BMCR_ISOLATE); in dm9161_config_init()
159 err = phy_write(phydev, MII_DM9161_SCR, temp); in dm9161_config_init()
164 err = phy_write(phydev, MII_DM9161_10BTCSR, MII_DM9161_10BTCSR_INIT); in dm9161_config_init()
170 return phy_write(phydev, MII_BMCR, BMCR_ANENABLE); in dm9161_config_init()
/kernel/linux/linux-6.6/drivers/net/ethernet/realtek/
H A Dr8169_phy_config.c285 phy_write(phydev, 0x1f, 0x0001); in rtl8168bb_hw_phy_config()
287 phy_write(phydev, 0x10, 0xf41b); in rtl8168bb_hw_phy_config()
288 phy_write(phydev, 0x1f, 0x0000); in rtl8168bb_hw_phy_config()
300 phy_write(phydev, 0x1d, 0x0f00); in rtl8168cp_1_hw_phy_config()
438 phy_write(phydev, 0x1f, 0x0005); in rtl8168d_apply_firmware_cond()
439 phy_write(phydev, 0x05, 0x001b); in rtl8168d_apply_firmware_cond()
441 phy_write(phydev, 0x1f, 0x0000); in rtl8168d_apply_firmware_cond()
455 phy_write(phydev, 0x1f, 0x0002); in rtl8168d_1_common()
468 phy_write(phydev, 0x0d, val | set[i]); in rtl8168d_1_common()
481 phy_write(phyde in rtl8168d_1_hw_phy_config()
[all...]
/kernel/linux/linux-5.10/arch/arm/mach-imx/
H A Dmach-imx6q.c28 phy_write(phydev, MICREL_KSZ9021_EXTREG_CTRL, in ksz9021rn_phy_fixup()
30 phy_write(phydev, MICREL_KSZ9021_EXTREG_DATA_WRITE, 0x0000); in ksz9021rn_phy_fixup()
33 phy_write(phydev, MICREL_KSZ9021_EXTREG_CTRL, in ksz9021rn_phy_fixup()
35 phy_write(phydev, MICREL_KSZ9021_EXTREG_DATA_WRITE, 0xf0f0); in ksz9021rn_phy_fixup()
36 phy_write(phydev, MICREL_KSZ9021_EXTREG_CTRL, in ksz9021rn_phy_fixup()
45 phy_write(dev, 0x0d, device); in mmd_write_reg()
46 phy_write(dev, 0x0e, reg); in mmd_write_reg()
47 phy_write(dev, 0x0d, (1 << 14) | device); in mmd_write_reg()
48 phy_write(dev, 0x0e, val); in mmd_write_reg()
97 phy_write(de in ar8031_phy_fixup()
[all...]
H A Dmach-imx7d.c22 phy_write(dev, 0x1d, 0x1f); in ar8031_phy_fixup()
23 phy_write(dev, 0x1e, 0x8); in ar8031_phy_fixup()
26 phy_write(dev, 0xd, 0x3); in ar8031_phy_fixup()
27 phy_write(dev, 0xe, 0x805d); in ar8031_phy_fixup()
28 phy_write(dev, 0xd, 0x4003); in ar8031_phy_fixup()
31 phy_write(dev, 0xe, val); in ar8031_phy_fixup()
39 phy_write(dev, 0x1e, 0x21); in bcm54220_phy_fixup()
40 phy_write(dev, 0x1f, 0x7ea8); in bcm54220_phy_fixup()
41 phy_write(dev, 0x1e, 0x2f); in bcm54220_phy_fixup()
42 phy_write(de in bcm54220_phy_fixup()
[all...]
/kernel/linux/linux-5.10/drivers/net/ethernet/ibm/emac/
H A Dphy.c33 #define phy_write _phy_write macro
63 phy_write(phy, MII_BMCR, val); in emac_mii_reset_phy()
74 phy_write(phy, MII_BMCR, val & ~BMCR_ISOLATE); in emac_mii_reset_phy()
126 phy_write(phy, MII_BMCR, ctl); in genmii_setup_aneg()
146 phy_write(phy, MII_ADVERTISE, adv); in genmii_setup_aneg()
158 phy_write(phy, MII_CTRL1000, adv); in genmii_setup_aneg()
164 phy_write(phy, MII_BMCR, ctl); in genmii_setup_aneg()
184 phy_write(phy, MII_BMCR, ctl | BMCR_RESET); in genmii_setup_forced()
201 phy_write(phy, MII_BMCR, ctl); in genmii_setup_forced()
331 phy_write(ph in cis8201_init()
[all...]
/kernel/linux/linux-6.6/drivers/net/ethernet/ibm/emac/
H A Dphy.c33 #define phy_write _phy_write macro
63 phy_write(phy, MII_BMCR, val); in emac_mii_reset_phy()
74 phy_write(phy, MII_BMCR, val & ~BMCR_ISOLATE); in emac_mii_reset_phy()
126 phy_write(phy, MII_BMCR, ctl); in genmii_setup_aneg()
146 phy_write(phy, MII_ADVERTISE, adv); in genmii_setup_aneg()
158 phy_write(phy, MII_CTRL1000, adv); in genmii_setup_aneg()
164 phy_write(phy, MII_BMCR, ctl); in genmii_setup_aneg()
184 phy_write(phy, MII_BMCR, ctl | BMCR_RESET); in genmii_setup_forced()
201 phy_write(phy, MII_BMCR, ctl); in genmii_setup_forced()
331 phy_write(ph in cis8201_init()
[all...]
/kernel/linux/linux-5.10/drivers/phy/freescale/
H A Dphy-fsl-imx8-mipi-dphy.c110 static int phy_write(struct phy *phy, u32 value, unsigned int reg) in phy_write() function
292 phy_write(phy, priv->cfg.m_prg_hs_prepare, DPHY_M_PRG_HS_PREPARE); in mixel_phy_set_hs_timings()
293 phy_write(phy, priv->cfg.mc_prg_hs_prepare, DPHY_MC_PRG_HS_PREPARE); in mixel_phy_set_hs_timings()
294 phy_write(phy, priv->cfg.m_prg_hs_zero, DPHY_M_PRG_HS_ZERO); in mixel_phy_set_hs_timings()
295 phy_write(phy, priv->cfg.mc_prg_hs_zero, DPHY_MC_PRG_HS_ZERO); in mixel_phy_set_hs_timings()
296 phy_write(phy, priv->cfg.m_prg_hs_trail, DPHY_M_PRG_HS_TRAIL); in mixel_phy_set_hs_timings()
297 phy_write(phy, priv->cfg.mc_prg_hs_trail, DPHY_MC_PRG_HS_TRAIL); in mixel_phy_set_hs_timings()
298 phy_write(phy, priv->cfg.rxhs_settle, priv->devdata->reg_rxhs_settle); in mixel_phy_set_hs_timings()
314 phy_write(phy, CM(priv->cfg.cm), DPHY_CM); in mixel_dphy_set_pll_params()
315 phy_write(ph in mixel_dphy_set_pll_params()
[all...]
/kernel/linux/linux-5.10/drivers/net/ethernet/realtek/
H A Dr8169_phy_config.c285 phy_write(phydev, 0x1f, 0x0001); in rtl8168bb_hw_phy_config()
287 phy_write(phydev, 0x10, 0xf41b); in rtl8168bb_hw_phy_config()
288 phy_write(phydev, 0x1f, 0x0000); in rtl8168bb_hw_phy_config()
300 phy_write(phydev, 0x1d, 0x0f00); in rtl8168cp_1_hw_phy_config()
447 phy_write(phydev, 0x1f, 0x0005); in rtl8168d_apply_firmware_cond()
448 phy_write(phydev, 0x05, 0x001b); in rtl8168d_apply_firmware_cond()
450 phy_write(phydev, 0x1f, 0x0000); in rtl8168d_apply_firmware_cond()
467 phy_write(phydev, 0x1f, 0x0002); in rtl8168d_1_hw_phy_config()
485 phy_write(phydev, 0x1f, 0x0002); in rtl8168d_1_hw_phy_config()
489 phy_write(phyde in rtl8168d_1_hw_phy_config()
[all...]
/kernel/linux/linux-6.6/drivers/phy/freescale/
H A Dphy-fsl-imx8-mipi-dphy.c142 static int phy_write(struct phy *phy, u32 value, unsigned int reg) in phy_write() function
324 phy_write(phy, priv->cfg.m_prg_hs_prepare, DPHY_M_PRG_HS_PREPARE); in mixel_phy_set_hs_timings()
325 phy_write(phy, priv->cfg.mc_prg_hs_prepare, DPHY_MC_PRG_HS_PREPARE); in mixel_phy_set_hs_timings()
326 phy_write(phy, priv->cfg.m_prg_hs_zero, DPHY_M_PRG_HS_ZERO); in mixel_phy_set_hs_timings()
327 phy_write(phy, priv->cfg.mc_prg_hs_zero, DPHY_MC_PRG_HS_ZERO); in mixel_phy_set_hs_timings()
328 phy_write(phy, priv->cfg.m_prg_hs_trail, DPHY_M_PRG_HS_TRAIL); in mixel_phy_set_hs_timings()
329 phy_write(phy, priv->cfg.mc_prg_hs_trail, DPHY_MC_PRG_HS_TRAIL); in mixel_phy_set_hs_timings()
330 phy_write(phy, priv->cfg.rxhs_settle, priv->devdata->reg_rxhs_settle); in mixel_phy_set_hs_timings()
346 phy_write(phy, CM(priv->cfg.cm), DPHY_CM); in mixel_dphy_set_pll_params()
347 phy_write(ph in mixel_dphy_set_pll_params()
[all...]
/kernel/linux/linux-6.6/arch/arm/mach-imx/
H A Dmach-imx7d.c20 phy_write(dev, 0x1e, 0x21); in bcm54220_phy_fixup()
21 phy_write(dev, 0x1f, 0x7ea8); in bcm54220_phy_fixup()
22 phy_write(dev, 0x1e, 0x2f); in bcm54220_phy_fixup()
23 phy_write(dev, 0x1f, 0x71b7); in bcm54220_phy_fixup()

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