Lines Matching refs:phy_write
80 phy_write(phydev, MII_BRCM_CORE_BASE1E, 0x0010);
108 phy_write(phydev, MII_BRCM_CORE_BASE1E, 0x0010);
266 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_BIAS_TRIM, 0x3BE0);
271 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL,
281 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL,
337 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL,
341 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_CTRL_STAT,
347 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL,
351 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_CTRL_STAT,
356 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL,
360 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_CTRL_STAT,
366 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL,
370 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_CTRL_STAT,
383 phy_write(phydev, MII_BMCR,
522 phy_write(phydev, MII_BCM7XXX_AUX_MODE, MII_BCM7XXX_64CLK_MDIO);
532 phy_write(phydev, MII_BCM7XXX_100TX_DISC, 0x0F00);
536 phy_write(phydev, MII_BCM7XXX_100TX_DISC, 0x0C00);
538 phy_write(phydev, MII_BCM7XXX_100TX_FALSE_CAR, 0x7555);
568 ret = phy_write(phydev,