Lines Matching refs:phy_write
79 phy_write(phydev, MII_BRCM_CORE_BASE1E, 0x0010);
107 phy_write(phydev, MII_BRCM_CORE_BASE1E, 0x0010);
265 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_BIAS_TRIM, 0x3BE0);
270 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL,
280 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL,
336 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL,
340 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_CTRL_STAT,
346 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL,
350 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_CTRL_STAT,
355 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL,
359 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_CTRL_STAT,
365 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL,
369 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_CTRL_STAT,
382 phy_write(phydev, MII_BMCR,
705 phy_write(phydev, MII_BCM7XXX_AUX_MODE, MII_BCM7XXX_64CLK_MDIO);
715 phy_write(phydev, MII_BCM7XXX_100TX_DISC, 0x0F00);
719 phy_write(phydev, MII_BCM7XXX_100TX_DISC, 0x0C00);
721 phy_write(phydev, MII_BCM7XXX_100TX_FALSE_CAR, 0x7555);
751 ret = phy_write(phydev,