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Searched
refs:crtc_reg
(Results
1 - 18
of
18
) sorted by relevance
/kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/dispnv04/
H
A
D
dfp.c
95
struct nv04_crtc_reg *crtcstate = nv04_display(dev)->mode_reg.
crtc_reg
;
in nv04_dfp_disable()
122
fpc = &nv04_display(dev)->mode_reg.
crtc_reg
[nv_crtc->index].fp_control;
in nv04_dfp_update_fp_control()
137
fpc = &nv04_display(dev)->mode_reg.
crtc_reg
[nv_crtc->index].fp_control;
in nv04_dfp_update_fp_control()
251
struct nv04_crtc_reg *crtcstate = nv04_display(dev)->mode_reg.
crtc_reg
;
in nv04_dfp_prepare()
288
struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.
crtc_reg
[nv_crtc->index];
in nv04_dfp_mode_set()
289
struct nv04_crtc_reg *savep = &nv04_display(dev)->saved_reg.
crtc_reg
[nv_crtc->index];
in nv04_dfp_mode_set()
464
nv04_display(dev)->mode_reg.
crtc_reg
[head].fp_control =
in nv04_dfp_commit()
604
(&nv04_display(dev)->saved_reg.
crtc_reg
[head].pllvals);
in nv04_dfp_restore()
H
A
D
tvnv04.c
107
struct nv04_crtc_reg *state = &nv04_display(dev)->mode_reg.
crtc_reg
[head];
in nv04_tv_bind()
146
struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.
crtc_reg
[nv_crtc->index];
in nv04_tv_mode_set()
H
A
D
hw.c
396
struct nv04_crtc_reg *regp = &state->
crtc_reg
[head];
in nv_save_state_ramdac()
472
struct nv04_crtc_reg *regp = &state->
crtc_reg
[head];
in nv_load_state_ramdac()
542
struct nv04_crtc_reg *regp = &state->
crtc_reg
[head];
in nv_save_state_vga()
566
struct nv04_crtc_reg *regp = &state->
crtc_reg
[head];
in nv_load_state_vga()
593
struct nv04_crtc_reg *regp = &state->
crtc_reg
[head];
in nv_save_state_ext()
669
struct nv04_crtc_reg *regp = &state->
crtc_reg
[head];
in nv_load_state_ext()
786
state->
crtc_reg
[head].DAC[i] = nvif_rd08(device,
in nv_save_state_palette()
806
state->
crtc_reg
[head].DAC[i]);
in nouveau_hw_load_state_palette()
H
A
D
crtc.c
67
struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.
crtc_reg
[nv_crtc->index];
in nv_crtc_set_digital_vibrance()
82
struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.
crtc_reg
[nv_crtc->index];
in nv_crtc_set_image_sharpening()
125
struct nv04_crtc_reg *regp = &state->
crtc_reg
[nv_crtc->index];
in nv_crtc_calc_state_ext()
241
struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.
crtc_reg
[nv_crtc->index];
in nv_crtc_mode_set_vga()
466
struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.
crtc_reg
[nv_crtc->index];
in nv_crtc_mode_set_regs()
467
struct nv04_crtc_reg *savep = &nv04_display(dev)->saved_reg.
crtc_reg
[nv_crtc->index];
in nv_crtc_mode_set_regs()
546
regp->CRTC[NV_CIO_CRE_TVOUT_LATENCY] = nv04_display(dev)->saved_reg.
crtc_reg
[0].CRTC[NV_CIO_CRE_TVOUT_LATENCY];
in nv_crtc_mode_set_regs()
670
struct nv04_crtc_reg *crtc_state = &state->
crtc_reg
[nv_crtc->index];
in nv_crtc_save()
672
struct nv04_crtc_reg *crtc_saved = &saved->
crtc_reg
[nv_crtc->index];
in nv_crtc_save()
691
uint8_t saved_cr21 = nv04_display(dev)->saved_reg.
crtc_reg
[hea
in nv_crtc_restore()
[all...]
H
A
D
cursor.c
42
struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.
crtc_reg
[nv_crtc->index];
in nv04_cursor_set_offset()
H
A
D
disp.h
76
struct nv04_crtc_reg
crtc_reg
[2];
member
H
A
D
tvnv17.c
403
uint8_t *cr_lcd = &nv04_display(dev)->mode_reg.
crtc_reg
[head].CRTC[
in nv17_tv_prepare()
464
struct nv04_crtc_reg *regs = &nv04_display(dev)->mode_reg.
crtc_reg
[head];
in nv17_tv_mode_set()
H
A
D
hw.h
376
&nv04_display(dev)->mode_reg.
crtc_reg
[head].CRTC[NV_CIO_CRE_HCUR_ADDR1_INDEX];
in nv_show_cursor()
H
A
D
tvmodesnv17.c
547
struct nv04_crtc_reg *regs = &nv04_display(dev)->mode_reg.
crtc_reg
[head];
in nv17_ctv_update_rescaler()
/kernel/linux/linux-6.6/drivers/gpu/drm/nouveau/dispnv04/
H
A
D
dfp.c
95
struct nv04_crtc_reg *crtcstate = nv04_display(dev)->mode_reg.
crtc_reg
;
in nv04_dfp_disable()
122
fpc = &nv04_display(dev)->mode_reg.
crtc_reg
[nv_crtc->index].fp_control;
in nv04_dfp_update_fp_control()
137
fpc = &nv04_display(dev)->mode_reg.
crtc_reg
[nv_crtc->index].fp_control;
in nv04_dfp_update_fp_control()
251
struct nv04_crtc_reg *crtcstate = nv04_display(dev)->mode_reg.
crtc_reg
;
in nv04_dfp_prepare()
288
struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.
crtc_reg
[nv_crtc->index];
in nv04_dfp_mode_set()
289
struct nv04_crtc_reg *savep = &nv04_display(dev)->saved_reg.
crtc_reg
[nv_crtc->index];
in nv04_dfp_mode_set()
464
nv04_display(dev)->mode_reg.
crtc_reg
[head].fp_control =
in nv04_dfp_commit()
605
(&nv04_display(dev)->saved_reg.
crtc_reg
[head].pllvals);
in nv04_dfp_restore()
H
A
D
tvnv04.c
107
struct nv04_crtc_reg *state = &nv04_display(dev)->mode_reg.
crtc_reg
[head];
in nv04_tv_bind()
146
struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.
crtc_reg
[nv_crtc->index];
in nv04_tv_mode_set()
H
A
D
hw.c
398
struct nv04_crtc_reg *regp = &state->
crtc_reg
[head];
in nv_save_state_ramdac()
474
struct nv04_crtc_reg *regp = &state->
crtc_reg
[head];
in nv_load_state_ramdac()
544
struct nv04_crtc_reg *regp = &state->
crtc_reg
[head];
in nv_save_state_vga()
568
struct nv04_crtc_reg *regp = &state->
crtc_reg
[head];
in nv_load_state_vga()
595
struct nv04_crtc_reg *regp = &state->
crtc_reg
[head];
in nv_save_state_ext()
671
struct nv04_crtc_reg *regp = &state->
crtc_reg
[head];
in nv_load_state_ext()
788
state->
crtc_reg
[head].DAC[i] = nvif_rd08(device,
in nv_save_state_palette()
808
state->
crtc_reg
[head].DAC[i]);
in nouveau_hw_load_state_palette()
H
A
D
crtc.c
67
struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.
crtc_reg
[nv_crtc->index];
in nv_crtc_set_digital_vibrance()
82
struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.
crtc_reg
[nv_crtc->index];
in nv_crtc_set_image_sharpening()
125
struct nv04_crtc_reg *regp = &state->
crtc_reg
[nv_crtc->index];
in nv_crtc_calc_state_ext()
241
struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.
crtc_reg
[nv_crtc->index];
in nv_crtc_mode_set_vga()
466
struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.
crtc_reg
[nv_crtc->index];
in nv_crtc_mode_set_regs()
467
struct nv04_crtc_reg *savep = &nv04_display(dev)->saved_reg.
crtc_reg
[nv_crtc->index];
in nv_crtc_mode_set_regs()
546
regp->CRTC[NV_CIO_CRE_TVOUT_LATENCY] = nv04_display(dev)->saved_reg.
crtc_reg
[0].CRTC[NV_CIO_CRE_TVOUT_LATENCY];
in nv_crtc_mode_set_regs()
670
struct nv04_crtc_reg *crtc_state = &state->
crtc_reg
[nv_crtc->index];
in nv_crtc_save()
672
struct nv04_crtc_reg *crtc_saved = &saved->
crtc_reg
[nv_crtc->index];
in nv_crtc_save()
691
uint8_t saved_cr21 = nv04_display(dev)->saved_reg.
crtc_reg
[hea
in nv_crtc_restore()
[all...]
H
A
D
cursor.c
42
struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.
crtc_reg
[nv_crtc->index];
in nv04_cursor_set_offset()
H
A
D
disp.h
78
struct nv04_crtc_reg
crtc_reg
[2];
member
H
A
D
tvnv17.c
404
uint8_t *cr_lcd = &nv04_display(dev)->mode_reg.
crtc_reg
[head].CRTC[
in nv17_tv_prepare()
465
struct nv04_crtc_reg *regs = &nv04_display(dev)->mode_reg.
crtc_reg
[head];
in nv17_tv_mode_set()
H
A
D
hw.h
376
&nv04_display(dev)->mode_reg.
crtc_reg
[head].CRTC[NV_CIO_CRE_HCUR_ADDR1_INDEX];
in nv_show_cursor()
H
A
D
tvmodesnv17.c
546
struct nv04_crtc_reg *regs = &nv04_display(dev)->mode_reg.
crtc_reg
[head];
in nv17_ctv_update_rescaler()
Completed in 16 milliseconds