162306a36Sopenharmony_ci// SPDX-License-Identifier: MIT
262306a36Sopenharmony_ci#include <drm/drm_mode.h>
362306a36Sopenharmony_ci#include "nouveau_drv.h"
462306a36Sopenharmony_ci#include "nouveau_reg.h"
562306a36Sopenharmony_ci#include "nouveau_crtc.h"
662306a36Sopenharmony_ci#include "hw.h"
762306a36Sopenharmony_ci
862306a36Sopenharmony_cistatic void
962306a36Sopenharmony_cinv04_cursor_show(struct nouveau_crtc *nv_crtc, bool update)
1062306a36Sopenharmony_ci{
1162306a36Sopenharmony_ci	nv_show_cursor(nv_crtc->base.dev, nv_crtc->index, true);
1262306a36Sopenharmony_ci}
1362306a36Sopenharmony_ci
1462306a36Sopenharmony_cistatic void
1562306a36Sopenharmony_cinv04_cursor_hide(struct nouveau_crtc *nv_crtc, bool update)
1662306a36Sopenharmony_ci{
1762306a36Sopenharmony_ci	nv_show_cursor(nv_crtc->base.dev, nv_crtc->index, false);
1862306a36Sopenharmony_ci}
1962306a36Sopenharmony_ci
2062306a36Sopenharmony_cistatic void
2162306a36Sopenharmony_cinv04_cursor_set_pos(struct nouveau_crtc *nv_crtc, int x, int y)
2262306a36Sopenharmony_ci{
2362306a36Sopenharmony_ci	nv_crtc->cursor_saved_x = x; nv_crtc->cursor_saved_y = y;
2462306a36Sopenharmony_ci	NVWriteRAMDAC(nv_crtc->base.dev, nv_crtc->index,
2562306a36Sopenharmony_ci		      NV_PRAMDAC_CU_START_POS,
2662306a36Sopenharmony_ci		      XLATE(y, 0, NV_PRAMDAC_CU_START_POS_Y) |
2762306a36Sopenharmony_ci		      XLATE(x, 0, NV_PRAMDAC_CU_START_POS_X));
2862306a36Sopenharmony_ci}
2962306a36Sopenharmony_ci
3062306a36Sopenharmony_cistatic void
3162306a36Sopenharmony_cicrtc_wr_cio_state(struct drm_crtc *crtc, struct nv04_crtc_reg *crtcstate, int index)
3262306a36Sopenharmony_ci{
3362306a36Sopenharmony_ci	NVWriteVgaCrtc(crtc->dev, nouveau_crtc(crtc)->index, index,
3462306a36Sopenharmony_ci		       crtcstate->CRTC[index]);
3562306a36Sopenharmony_ci}
3662306a36Sopenharmony_ci
3762306a36Sopenharmony_cistatic void
3862306a36Sopenharmony_cinv04_cursor_set_offset(struct nouveau_crtc *nv_crtc, uint32_t offset)
3962306a36Sopenharmony_ci{
4062306a36Sopenharmony_ci	struct drm_device *dev = nv_crtc->base.dev;
4162306a36Sopenharmony_ci	struct nouveau_drm *drm = nouveau_drm(dev);
4262306a36Sopenharmony_ci	struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];
4362306a36Sopenharmony_ci	struct drm_crtc *crtc = &nv_crtc->base;
4462306a36Sopenharmony_ci
4562306a36Sopenharmony_ci	regp->CRTC[NV_CIO_CRE_HCUR_ADDR0_INDEX] =
4662306a36Sopenharmony_ci		MASK(NV_CIO_CRE_HCUR_ASI) |
4762306a36Sopenharmony_ci		XLATE(offset, 17, NV_CIO_CRE_HCUR_ADDR0_ADR);
4862306a36Sopenharmony_ci	regp->CRTC[NV_CIO_CRE_HCUR_ADDR1_INDEX] =
4962306a36Sopenharmony_ci		XLATE(offset, 11, NV_CIO_CRE_HCUR_ADDR1_ADR);
5062306a36Sopenharmony_ci	if (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)
5162306a36Sopenharmony_ci		regp->CRTC[NV_CIO_CRE_HCUR_ADDR1_INDEX] |=
5262306a36Sopenharmony_ci			MASK(NV_CIO_CRE_HCUR_ADDR1_CUR_DBL);
5362306a36Sopenharmony_ci	regp->CRTC[NV_CIO_CRE_HCUR_ADDR2_INDEX] = offset >> 24;
5462306a36Sopenharmony_ci
5562306a36Sopenharmony_ci	crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_HCUR_ADDR0_INDEX);
5662306a36Sopenharmony_ci	crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_HCUR_ADDR1_INDEX);
5762306a36Sopenharmony_ci	crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_HCUR_ADDR2_INDEX);
5862306a36Sopenharmony_ci	if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CURIE)
5962306a36Sopenharmony_ci		nv_fix_nv40_hw_cursor(dev, nv_crtc->index);
6062306a36Sopenharmony_ci}
6162306a36Sopenharmony_ci
6262306a36Sopenharmony_ciint
6362306a36Sopenharmony_cinv04_cursor_init(struct nouveau_crtc *crtc)
6462306a36Sopenharmony_ci{
6562306a36Sopenharmony_ci	crtc->cursor.set_offset = nv04_cursor_set_offset;
6662306a36Sopenharmony_ci	crtc->cursor.set_pos = nv04_cursor_set_pos;
6762306a36Sopenharmony_ci	crtc->cursor.hide = nv04_cursor_hide;
6862306a36Sopenharmony_ci	crtc->cursor.show = nv04_cursor_show;
6962306a36Sopenharmony_ci	return 0;
7062306a36Sopenharmony_ci}
71