18c2ecf20Sopenharmony_ci// SPDX-License-Identifier: MIT 28c2ecf20Sopenharmony_ci#include <drm/drm_mode.h> 38c2ecf20Sopenharmony_ci#include "nouveau_drv.h" 48c2ecf20Sopenharmony_ci#include "nouveau_reg.h" 58c2ecf20Sopenharmony_ci#include "nouveau_crtc.h" 68c2ecf20Sopenharmony_ci#include "hw.h" 78c2ecf20Sopenharmony_ci 88c2ecf20Sopenharmony_cistatic void 98c2ecf20Sopenharmony_cinv04_cursor_show(struct nouveau_crtc *nv_crtc, bool update) 108c2ecf20Sopenharmony_ci{ 118c2ecf20Sopenharmony_ci nv_show_cursor(nv_crtc->base.dev, nv_crtc->index, true); 128c2ecf20Sopenharmony_ci} 138c2ecf20Sopenharmony_ci 148c2ecf20Sopenharmony_cistatic void 158c2ecf20Sopenharmony_cinv04_cursor_hide(struct nouveau_crtc *nv_crtc, bool update) 168c2ecf20Sopenharmony_ci{ 178c2ecf20Sopenharmony_ci nv_show_cursor(nv_crtc->base.dev, nv_crtc->index, false); 188c2ecf20Sopenharmony_ci} 198c2ecf20Sopenharmony_ci 208c2ecf20Sopenharmony_cistatic void 218c2ecf20Sopenharmony_cinv04_cursor_set_pos(struct nouveau_crtc *nv_crtc, int x, int y) 228c2ecf20Sopenharmony_ci{ 238c2ecf20Sopenharmony_ci nv_crtc->cursor_saved_x = x; nv_crtc->cursor_saved_y = y; 248c2ecf20Sopenharmony_ci NVWriteRAMDAC(nv_crtc->base.dev, nv_crtc->index, 258c2ecf20Sopenharmony_ci NV_PRAMDAC_CU_START_POS, 268c2ecf20Sopenharmony_ci XLATE(y, 0, NV_PRAMDAC_CU_START_POS_Y) | 278c2ecf20Sopenharmony_ci XLATE(x, 0, NV_PRAMDAC_CU_START_POS_X)); 288c2ecf20Sopenharmony_ci} 298c2ecf20Sopenharmony_ci 308c2ecf20Sopenharmony_cistatic void 318c2ecf20Sopenharmony_cicrtc_wr_cio_state(struct drm_crtc *crtc, struct nv04_crtc_reg *crtcstate, int index) 328c2ecf20Sopenharmony_ci{ 338c2ecf20Sopenharmony_ci NVWriteVgaCrtc(crtc->dev, nouveau_crtc(crtc)->index, index, 348c2ecf20Sopenharmony_ci crtcstate->CRTC[index]); 358c2ecf20Sopenharmony_ci} 368c2ecf20Sopenharmony_ci 378c2ecf20Sopenharmony_cistatic void 388c2ecf20Sopenharmony_cinv04_cursor_set_offset(struct nouveau_crtc *nv_crtc, uint32_t offset) 398c2ecf20Sopenharmony_ci{ 408c2ecf20Sopenharmony_ci struct drm_device *dev = nv_crtc->base.dev; 418c2ecf20Sopenharmony_ci struct nouveau_drm *drm = nouveau_drm(dev); 428c2ecf20Sopenharmony_ci struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index]; 438c2ecf20Sopenharmony_ci struct drm_crtc *crtc = &nv_crtc->base; 448c2ecf20Sopenharmony_ci 458c2ecf20Sopenharmony_ci regp->CRTC[NV_CIO_CRE_HCUR_ADDR0_INDEX] = 468c2ecf20Sopenharmony_ci MASK(NV_CIO_CRE_HCUR_ASI) | 478c2ecf20Sopenharmony_ci XLATE(offset, 17, NV_CIO_CRE_HCUR_ADDR0_ADR); 488c2ecf20Sopenharmony_ci regp->CRTC[NV_CIO_CRE_HCUR_ADDR1_INDEX] = 498c2ecf20Sopenharmony_ci XLATE(offset, 11, NV_CIO_CRE_HCUR_ADDR1_ADR); 508c2ecf20Sopenharmony_ci if (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN) 518c2ecf20Sopenharmony_ci regp->CRTC[NV_CIO_CRE_HCUR_ADDR1_INDEX] |= 528c2ecf20Sopenharmony_ci MASK(NV_CIO_CRE_HCUR_ADDR1_CUR_DBL); 538c2ecf20Sopenharmony_ci regp->CRTC[NV_CIO_CRE_HCUR_ADDR2_INDEX] = offset >> 24; 548c2ecf20Sopenharmony_ci 558c2ecf20Sopenharmony_ci crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_HCUR_ADDR0_INDEX); 568c2ecf20Sopenharmony_ci crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_HCUR_ADDR1_INDEX); 578c2ecf20Sopenharmony_ci crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_HCUR_ADDR2_INDEX); 588c2ecf20Sopenharmony_ci if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CURIE) 598c2ecf20Sopenharmony_ci nv_fix_nv40_hw_cursor(dev, nv_crtc->index); 608c2ecf20Sopenharmony_ci} 618c2ecf20Sopenharmony_ci 628c2ecf20Sopenharmony_ciint 638c2ecf20Sopenharmony_cinv04_cursor_init(struct nouveau_crtc *crtc) 648c2ecf20Sopenharmony_ci{ 658c2ecf20Sopenharmony_ci crtc->cursor.set_offset = nv04_cursor_set_offset; 668c2ecf20Sopenharmony_ci crtc->cursor.set_pos = nv04_cursor_set_pos; 678c2ecf20Sopenharmony_ci crtc->cursor.hide = nv04_cursor_hide; 688c2ecf20Sopenharmony_ci crtc->cursor.show = nv04_cursor_show; 698c2ecf20Sopenharmony_ci return 0; 708c2ecf20Sopenharmony_ci} 71