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/kernel/linux/linux-5.10/drivers/clk/sprd/
H A Dgate.h31 #define SPRD_SC_GATE_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, \
41 .reg = _reg, \
47 #define SPRD_SC_GATE_CLK_OPS_UDELAY(_struct, _name, _parent, _reg, \
50 SPRD_SC_GATE_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, \
54 #define SPRD_SC_GATE_CLK_OPS(_struct, _name, _parent, _reg, _sc_offset, \
56 SPRD_SC_GATE_CLK_OPS_UDELAY(_struct, _name, _parent, _reg, \
60 #define SPRD_SC_GATE_CLK(_struct, _name, _parent, _reg, _sc_offset, \
62 SPRD_SC_GATE_CLK_OPS(_struct, _name, _parent, _reg, _sc_offset, \
66 #define SPRD_GATE_CLK(_struct, _name, _parent, _reg, \
68 SPRD_SC_GATE_CLK_OPS(_struct, _name, _parent, _reg,
[all...]
H A Dcomposite.h21 #define SPRD_COMP_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, _table, \
29 .reg = _reg, \
35 #define SPRD_COMP_CLK_TABLE(_struct, _name, _parent, _reg, _table, \
37 SPRD_COMP_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, _table, \
41 #define SPRD_COMP_CLK(_struct, _name, _parent, _reg, _mshift, \
43 SPRD_COMP_CLK_TABLE(_struct, _name, _parent, _reg, NULL, \
46 #define SPRD_COMP_CLK_DATA_TABLE(_struct, _name, _parent, _reg, _table, \
49 SPRD_COMP_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, _table, \
53 #define SPRD_COMP_CLK_DATA(_struct, _name, _parent, _reg, _mshift, \
55 SPRD_COMP_CLK_DATA_TABLE(_struct, _name, _parent, _reg, NUL
[all...]
H A Dmux.h40 _reg, _shift, _width, _flags, _fn) \
45 .reg = _reg, \
52 _reg, _shift, _width, _flags) \
54 _reg, _shift, _width, _flags, \
57 #define SPRD_MUX_CLK(_struct, _name, _parents, _reg, \
60 _reg, _shift, _width, _flags)
63 _reg, _shift, _width, _flags) \
65 _reg, _shift, _width, _flags, \
68 #define SPRD_MUX_CLK_DATA(_struct, _name, _parents, _reg, \
71 _reg, _shif
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H A Dpll.h64 #define SPRD_PLL_HW_INIT_FN(_struct, _name, _parent, _reg, \
79 .reg = _reg, \
85 #define SPRD_PLL_WITH_ITABLE_K_FVCO(_struct, _name, _parent, _reg, \
88 SPRD_PLL_HW_INIT_FN(_struct, _name, _parent, _reg, _regs_num, \
92 #define SPRD_PLL_WITH_ITABLE_K(_struct, _name, _parent, _reg, \
95 SPRD_PLL_WITH_ITABLE_K_FVCO(_struct, _name, _parent, _reg, \
99 #define SPRD_PLL_WITH_ITABLE_1K(_struct, _name, _parent, _reg, \
101 SPRD_PLL_WITH_ITABLE_K_FVCO(_struct, _name, _parent, _reg, \
105 #define SPRD_PLL_FW_NAME(_struct, _name, _parent, _reg, _regs_num, \
108 SPRD_PLL_HW_INIT_FN(_struct, _name, _parent, _reg, _regs_nu
[all...]
/kernel/linux/linux-6.6/drivers/clk/sprd/
H A Dgate.h31 #define SPRD_SC_GATE_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, \
41 .reg = _reg, \
47 #define SPRD_SC_GATE_CLK_OPS_UDELAY(_struct, _name, _parent, _reg, \
50 SPRD_SC_GATE_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, \
54 #define SPRD_SC_GATE_CLK_OPS(_struct, _name, _parent, _reg, _sc_offset, \
56 SPRD_SC_GATE_CLK_OPS_UDELAY(_struct, _name, _parent, _reg, \
60 #define SPRD_SC_GATE_CLK(_struct, _name, _parent, _reg, _sc_offset, \
62 SPRD_SC_GATE_CLK_OPS(_struct, _name, _parent, _reg, _sc_offset, \
66 #define SPRD_GATE_CLK(_struct, _name, _parent, _reg, \
68 SPRD_SC_GATE_CLK_OPS(_struct, _name, _parent, _reg,
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H A Dcomposite.h21 #define SPRD_COMP_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, _table, \
29 .reg = _reg, \
35 #define SPRD_COMP_CLK_TABLE(_struct, _name, _parent, _reg, _table, \
37 SPRD_COMP_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, _table, \
41 #define SPRD_COMP_CLK(_struct, _name, _parent, _reg, _mshift, \
43 SPRD_COMP_CLK_TABLE(_struct, _name, _parent, _reg, NULL, \
46 #define SPRD_COMP_CLK_DATA_TABLE(_struct, _name, _parent, _reg, _table, \
49 SPRD_COMP_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, _table, \
53 #define SPRD_COMP_CLK_DATA(_struct, _name, _parent, _reg, _mshift, \
55 SPRD_COMP_CLK_DATA_TABLE(_struct, _name, _parent, _reg, NUL
[all...]
H A Dmux.h40 _reg, _shift, _width, _flags, _fn) \
45 .reg = _reg, \
52 _reg, _shift, _width, _flags) \
54 _reg, _shift, _width, _flags, \
57 #define SPRD_MUX_CLK(_struct, _name, _parents, _reg, \
60 _reg, _shift, _width, _flags)
63 _reg, _shift, _width, _flags) \
65 _reg, _shift, _width, _flags, \
68 #define SPRD_MUX_CLK_DATA(_struct, _name, _parents, _reg, \
71 _reg, _shif
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H A Dpll.h64 #define SPRD_PLL_HW_INIT_FN(_struct, _name, _parent, _reg, \
79 .reg = _reg, \
85 #define SPRD_PLL_WITH_ITABLE_K_FVCO(_struct, _name, _parent, _reg, \
88 SPRD_PLL_HW_INIT_FN(_struct, _name, _parent, _reg, _regs_num, \
92 #define SPRD_PLL_WITH_ITABLE_K(_struct, _name, _parent, _reg, \
95 SPRD_PLL_WITH_ITABLE_K_FVCO(_struct, _name, _parent, _reg, \
99 #define SPRD_PLL_WITH_ITABLE_1K(_struct, _name, _parent, _reg, \
101 SPRD_PLL_WITH_ITABLE_K_FVCO(_struct, _name, _parent, _reg, \
105 #define SPRD_PLL_FW_NAME(_struct, _name, _parent, _reg, _regs_num, \
108 SPRD_PLL_HW_INIT_FN(_struct, _name, _parent, _reg, _regs_nu
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/kernel/linux/linux-5.10/drivers/net/ethernet/amd/xgbe/
H A Dxgbe-common.h1462 #define XGMAC_IOREAD(_pdata, _reg) \
1463 ioread32((_pdata)->xgmac_regs + _reg)
1465 #define XGMAC_IOREAD_BITS(_pdata, _reg, _field) \
1466 GET_BITS(XGMAC_IOREAD((_pdata), _reg), \
1467 _reg##_##_field##_INDEX, \
1468 _reg##_##_field##_WIDTH)
1470 #define XGMAC_IOWRITE(_pdata, _reg, _val) \
1471 iowrite32((_val), (_pdata)->xgmac_regs + _reg)
1473 #define XGMAC_IOWRITE_BITS(_pdata, _reg, _field, _val) \
1475 u32 reg_val = XGMAC_IOREAD((_pdata), _reg); \
[all...]
/kernel/linux/linux-6.6/drivers/net/ethernet/amd/xgbe/
H A Dxgbe-common.h1502 #define XGMAC_IOREAD(_pdata, _reg) \
1503 ioread32((_pdata)->xgmac_regs + _reg)
1505 #define XGMAC_IOREAD_BITS(_pdata, _reg, _field) \
1506 GET_BITS(XGMAC_IOREAD((_pdata), _reg), \
1507 _reg##_##_field##_INDEX, \
1508 _reg##_##_field##_WIDTH)
1510 #define XGMAC_IOWRITE(_pdata, _reg, _val) \
1511 iowrite32((_val), (_pdata)->xgmac_regs + _reg)
1513 #define XGMAC_IOWRITE_BITS(_pdata, _reg, _field, _val) \
1515 u32 reg_val = XGMAC_IOREAD((_pdata), _reg); \
[all...]
/kernel/linux/linux-6.6/drivers/clk/sunxi-ng/
H A Dccu_div.h87 #define SUNXI_CCU_DIV_TABLE_WITH_GATE(_struct, _name, _parent, _reg, \
95 .reg = _reg, \
104 #define SUNXI_CCU_DIV_TABLE(_struct, _name, _parent, _reg, \
107 SUNXI_CCU_DIV_TABLE_WITH_GATE(_struct, _name, _parent, _reg, \
111 #define SUNXI_CCU_DIV_TABLE_HW(_struct, _name, _parent, _reg, \
118 .reg = _reg, \
129 _reg, \
138 .reg = _reg, \
148 _reg, \
157 .reg = _reg, \
[all...]
H A Dccu_gate.h19 #define SUNXI_CCU_GATE(_struct, _name, _parent, _reg, _gate, _flags) \
23 .reg = _reg, \
31 #define SUNXI_CCU_GATE_HW(_struct, _name, _parent, _reg, _gate, _flags) \
35 .reg = _reg, \
43 #define SUNXI_CCU_GATE_FW(_struct, _name, _parent, _reg, _gate, _flags) \
47 .reg = _reg, \
59 #define SUNXI_CCU_GATE_HWS(_struct, _name, _parent, _reg, _gate, _flags) \
63 .reg = _reg, \
71 #define SUNXI_CCU_GATE_HWS_WITH_PREDIV(_struct, _name, _parent, _reg, \
76 .reg = _reg, \
[all...]
H A Dccu_mux.h50 _reg, _shift, _width, _gate, \
56 .reg = _reg, \
66 _table, _reg, _shift, \
69 _table, _reg, _shift, \
74 _reg, _shift, _width, _gate, \
77 _table, _reg, _shift, \
80 #define SUNXI_CCU_MUX_WITH_GATE(_struct, _name, _parents, _reg, \
83 _reg, _shift, _width, _gate, \
86 #define SUNXI_CCU_MUX(_struct, _name, _parents, _reg, _shift, _width, \
89 _reg, _shif
[all...]
H A Dccu_mp.h34 #define SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(_struct, _name, _parents, _reg, \
46 .reg = _reg, \
55 #define SUNXI_CCU_MP_WITH_MUX_GATE(_struct, _name, _parents, _reg, \
66 .reg = _reg, \
74 #define SUNXI_CCU_MP_WITH_MUX(_struct, _name, _parents, _reg, \
79 SUNXI_CCU_MP_WITH_MUX_GATE(_struct, _name, _parents, _reg, \
85 #define SUNXI_CCU_MP_DATA_WITH_MUX_GATE(_struct, _name, _parents, _reg, \
96 .reg = _reg, \
104 #define SUNXI_CCU_MP_DATA_WITH_MUX(_struct, _name, _parents, _reg, \
109 SUNXI_CCU_MP_DATA_WITH_MUX_GATE(_struct, _name, _parents, _reg, \
[all...]
H A Dccu_nm.h38 #define SUNXI_CCU_NM_WITH_SDM_GATE_LOCK(_struct, _name, _parent, _reg, \
52 .reg = _reg, \
61 #define SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(_struct, _name, _parent, _reg, \
76 .reg = _reg, \
86 _reg, _min_rate, \
102 .reg = _reg, \
112 _parent, _reg, \
132 .reg = _reg, \
142 _parent, _reg, \
151 _parent, _reg, \
[all...]
/kernel/linux/linux-5.10/drivers/regulator/
H A Dmc13xxx.h55 #define MC13xxx_DEFINE(prefix, _name, _node, _reg, _vsel_reg, _voltages, _ops) \
66 .reg = prefix ## _reg, \
67 .enable_bit = prefix ## _reg ## _ ## _name ## EN, \
73 #define MC13xxx_FIXED_DEFINE(prefix, _name, _node, _reg, _voltages, _ops) \
84 .reg = prefix ## _reg, \
85 .enable_bit = prefix ## _reg ## _ ## _name ## EN, \
88 #define MC13xxx_GPO_DEFINE(prefix, _name, _node, _reg, _voltages, _ops) \
99 .reg = prefix ## _reg, \
100 .enable_bit = prefix ## _reg ## _ ## _name ## EN, \
103 #define MC13xxx_DEFINE_SW(_name, _node, _reg, _vsel_re
[all...]
/kernel/linux/linux-6.6/drivers/regulator/
H A Dmc13xxx.h55 #define MC13xxx_DEFINE(prefix, _name, _node, _reg, _vsel_reg, _voltages, _ops) \
66 .reg = prefix ## _reg, \
67 .enable_bit = prefix ## _reg ## _ ## _name ## EN, \
73 #define MC13xxx_FIXED_DEFINE(prefix, _name, _node, _reg, _voltages, _ops) \
84 .reg = prefix ## _reg, \
85 .enable_bit = prefix ## _reg ## _ ## _name ## EN, \
88 #define MC13xxx_GPO_DEFINE(prefix, _name, _node, _reg, _voltages, _ops) \
99 .reg = prefix ## _reg, \
100 .enable_bit = prefix ## _reg ## _ ## _name ## EN, \
103 #define MC13xxx_DEFINE_SW(_name, _node, _reg, _vsel_re
[all...]
/kernel/linux/linux-5.10/drivers/clk/sunxi-ng/
H A Dccu_gate.h19 #define SUNXI_CCU_GATE(_struct, _name, _parent, _reg, _gate, _flags) \
23 .reg = _reg, \
31 #define SUNXI_CCU_GATE_HW(_struct, _name, _parent, _reg, _gate, _flags) \
35 .reg = _reg, \
43 #define SUNXI_CCU_GATE_FW(_struct, _name, _parent, _reg, _gate, _flags) \
47 .reg = _reg, \
59 #define SUNXI_CCU_GATE_HWS(_struct, _name, _parent, _reg, _gate, _flags) \
63 .reg = _reg, \
71 #define SUNXI_CCU_GATE_DATA(_struct, _name, _data, _reg, _gate, _flags) \
75 .reg = _reg, \
[all...]
H A Dccu_div.h87 #define SUNXI_CCU_DIV_TABLE_WITH_GATE(_struct, _name, _parent, _reg, \
95 .reg = _reg, \
104 #define SUNXI_CCU_DIV_TABLE(_struct, _name, _parent, _reg, \
107 SUNXI_CCU_DIV_TABLE_WITH_GATE(_struct, _name, _parent, _reg, \
113 _reg, \
122 .reg = _reg, \
130 #define SUNXI_CCU_M_WITH_MUX_GATE(_struct, _name, _parents, _reg, \
135 _reg, _mshift, _mwidth, \
139 #define SUNXI_CCU_M_WITH_MUX(_struct, _name, _parents, _reg, \
144 _reg, _mshif
[all...]
/kernel/linux/linux-5.10/drivers/clk/zte/
H A Dclk.h37 #define ZX_PLL(_name, _parent, _reg, _table, _pd, _lock) \
39 .reg_base = (void __iomem *) _reg, \
52 #define ZX296718_PLL(_name, _parent, _reg, _table) \
53 ZX_PLL(_name, _parent, _reg, _table, 0xff, 30)
60 #define GATE(_id, _name, _parent, _reg, _bit, _flag, _gflags) \
63 .reg = (void __iomem *) _reg, \
98 #define MUX_F(_id, _name, _parent, _reg, _shift, _width, _flag, _mflag) \
101 .reg = (void __iomem *) _reg, \
114 #define MUX(_id, _name, _parent, _reg, _shift, _width) \
115 MUX_F(_id, _name, _parent, _reg, _shif
[all...]
/kernel/linux/linux-5.10/drivers/clk/pistachio/
H A Dclk.h19 #define GATE(_id, _name, _pname, _reg, _shift) \
22 .reg = _reg, \
39 #define MUX(_id, _name, _pnames, _reg, _shift) \
42 .reg = _reg, \
59 #define DIV(_id, _name, _pname, _reg, _width) \
62 .reg = _reg, \
69 #define DIV_F(_id, _name, _pname, _reg, _width, _div_flags) \
72 .reg = _reg, \
119 #define PLL(_id, _name, _pname, _type, _reg, _rates) \
122 .reg_base = _reg, \
[all...]
/kernel/linux/linux-6.6/drivers/clk/pistachio/
H A Dclk.h19 #define GATE(_id, _name, _pname, _reg, _shift) \
22 .reg = _reg, \
39 #define MUX(_id, _name, _pnames, _reg, _shift) \
42 .reg = _reg, \
59 #define DIV(_id, _name, _pname, _reg, _width) \
62 .reg = _reg, \
69 #define DIV_F(_id, _name, _pname, _reg, _width, _div_flags) \
72 .reg = _reg, \
119 #define PLL(_id, _name, _pname, _type, _reg, _rates) \
122 .reg_base = _reg, \
[all...]
/kernel/linux/linux-5.10/arch/mips/include/asm/mach-pic32/
H A Dpic32.h14 #define PIC32_CLR(_reg) ((_reg) + 0x04)
15 #define PIC32_SET(_reg) ((_reg) + 0x08)
16 #define PIC32_INV(_reg) ((_reg) + 0x0C)
/kernel/linux/linux-6.6/arch/mips/include/asm/mach-pic32/
H A Dpic32.h14 #define PIC32_CLR(_reg) ((_reg) + 0x04)
15 #define PIC32_SET(_reg) ((_reg) + 0x08)
16 #define PIC32_INV(_reg) ((_reg) + 0x0C)
/kernel/linux/linux-5.10/drivers/clk/mediatek/
H A Dclk-mtk.h81 #define MUX_GATE_FLAGS_2(_id, _name, _parents, _reg, _shift, \
85 .mux_reg = _reg, \
88 .gate_reg = _reg, \
101 #define MUX_GATE_FLAGS(_id, _name, _parents, _reg, _shift, _width, \
103 MUX_GATE_FLAGS_2(_id, _name, _parents, _reg, \
110 #define MUX_GATE(_id, _name, _parents, _reg, _shift, _width, _gate) \
111 MUX_GATE_FLAGS(_id, _name, _parents, _reg, _shift, _width, \
114 #define MUX(_id, _name, _parents, _reg, _shift, _width) \
115 MUX_FLAGS(_id, _name, _parents, _reg, \
118 #define MUX_FLAGS(_id, _name, _parents, _reg, _shif
[all...]

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12345678910>>...12