162306a36Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0-only */ 262306a36Sopenharmony_ci/* 362306a36Sopenharmony_ci * Joshua Henderson <joshua.henderson@microchip.com> 462306a36Sopenharmony_ci * Copyright (C) 2015 Microchip Technology Inc. All rights reserved. 562306a36Sopenharmony_ci */ 662306a36Sopenharmony_ci#ifndef _ASM_MACH_PIC32_H 762306a36Sopenharmony_ci#define _ASM_MACH_PIC32_H 862306a36Sopenharmony_ci 962306a36Sopenharmony_ci#include <linux/io.h> 1062306a36Sopenharmony_ci 1162306a36Sopenharmony_ci/* 1262306a36Sopenharmony_ci * PIC32 register offsets for SET/CLR/INV where supported. 1362306a36Sopenharmony_ci */ 1462306a36Sopenharmony_ci#define PIC32_CLR(_reg) ((_reg) + 0x04) 1562306a36Sopenharmony_ci#define PIC32_SET(_reg) ((_reg) + 0x08) 1662306a36Sopenharmony_ci#define PIC32_INV(_reg) ((_reg) + 0x0C) 1762306a36Sopenharmony_ci 1862306a36Sopenharmony_ci/* 1962306a36Sopenharmony_ci * PIC32 Base Register Offsets 2062306a36Sopenharmony_ci */ 2162306a36Sopenharmony_ci#define PIC32_BASE_CONFIG 0x1f800000 2262306a36Sopenharmony_ci#define PIC32_BASE_OSC 0x1f801200 2362306a36Sopenharmony_ci#define PIC32_BASE_RESET 0x1f801240 2462306a36Sopenharmony_ci#define PIC32_BASE_PPS 0x1f801400 2562306a36Sopenharmony_ci#define PIC32_BASE_UART 0x1f822000 2662306a36Sopenharmony_ci#define PIC32_BASE_PORT 0x1f860000 2762306a36Sopenharmony_ci#define PIC32_BASE_DEVCFG2 0x1fc4ff44 2862306a36Sopenharmony_ci 2962306a36Sopenharmony_ci/* 3062306a36Sopenharmony_ci * Register unlock sequence required for some register access. 3162306a36Sopenharmony_ci */ 3262306a36Sopenharmony_civoid pic32_syskey_unlock_debug(const char *fn, const ulong ln); 3362306a36Sopenharmony_ci#define pic32_syskey_unlock() \ 3462306a36Sopenharmony_ci pic32_syskey_unlock_debug(__func__, __LINE__) 3562306a36Sopenharmony_ci 3662306a36Sopenharmony_ci#endif /* _ASM_MACH_PIC32_H */ 37