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Searched refs:__raw_writel (Results 1 - 25 of 944) sorted by relevance

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/kernel/linux/linux-5.10/arch/mips/alchemy/common/
H A Dirq.c293 __raw_writel(1 << bit, base + IC_MASKSET); in au1x_ic0_unmask()
294 __raw_writel(1 << bit, base + IC_WAKESET); in au1x_ic0_unmask()
303 __raw_writel(1 << bit, base + IC_MASKSET); in au1x_ic1_unmask()
304 __raw_writel(1 << bit, base + IC_WAKESET); in au1x_ic1_unmask()
313 __raw_writel(1 << bit, base + IC_MASKCLR); in au1x_ic0_mask()
314 __raw_writel(1 << bit, base + IC_WAKECLR); in au1x_ic0_mask()
323 __raw_writel(1 << bit, base + IC_MASKCLR); in au1x_ic1_mask()
324 __raw_writel(1 << bit, base + IC_WAKECLR); in au1x_ic1_mask()
337 __raw_writel(1 << bit, base + IC_FALLINGCLR); in au1x_ic0_ack()
338 __raw_writel( in au1x_ic0_ack()
[all...]
H A Dusb.c112 __raw_writel(r, base + USB_DWC_CTRL2); in __au1300_usb_phyctl()
118 __raw_writel(r, base + USB_DWC_CTRL2); in __au1300_usb_phyctl()
128 __raw_writel(1, base + USB_DWC_CTRL7); /* start OHCI clock */ in __au1300_ohci_control()
134 __raw_writel(r, base + USB_DWC_CTRL3); in __au1300_ohci_control()
141 __raw_writel(r, base + USB_INT_ENABLE); in __au1300_ohci_control()
145 __raw_writel(0, base + USB_DWC_CTRL7); in __au1300_ohci_control()
150 __raw_writel(r, base + USB_INT_ENABLE); in __au1300_ohci_control()
156 __raw_writel(r, base + USB_DWC_CTRL3); in __au1300_ohci_control()
170 __raw_writel(r, base + USB_DWC_CTRL3); in __au1300_ehci_control()
175 __raw_writel( in __au1300_ehci_control()
[all...]
H A Dvss.c27 __raw_writel(3, base + VSS_CLKRST); /* enable clock, assert reset */ in __enable_block()
30 __raw_writel(0x01fffffe, base + VSS_GATE); /* maximum setup time */ in __enable_block()
34 __raw_writel(0x01, base + VSS_FTR); in __enable_block()
36 __raw_writel(0x03, base + VSS_FTR); in __enable_block()
38 __raw_writel(0x07, base + VSS_FTR); in __enable_block()
40 __raw_writel(0x0f, base + VSS_FTR); in __enable_block()
43 __raw_writel(0x01ffffff, base + VSS_GATE); /* start FSM too */ in __enable_block()
46 __raw_writel(2, base + VSS_CLKRST); /* deassert reset */ in __enable_block()
49 __raw_writel(0x1f, base + VSS_FTR); /* enable isolation cells */ in __enable_block()
58 __raw_writel( in __disable_block()
[all...]
/kernel/linux/linux-6.6/arch/mips/alchemy/common/
H A Dirq.c293 __raw_writel(1 << bit, base + IC_MASKSET); in au1x_ic0_unmask()
294 __raw_writel(1 << bit, base + IC_WAKESET); in au1x_ic0_unmask()
303 __raw_writel(1 << bit, base + IC_MASKSET); in au1x_ic1_unmask()
304 __raw_writel(1 << bit, base + IC_WAKESET); in au1x_ic1_unmask()
313 __raw_writel(1 << bit, base + IC_MASKCLR); in au1x_ic0_mask()
314 __raw_writel(1 << bit, base + IC_WAKECLR); in au1x_ic0_mask()
323 __raw_writel(1 << bit, base + IC_MASKCLR); in au1x_ic1_mask()
324 __raw_writel(1 << bit, base + IC_WAKECLR); in au1x_ic1_mask()
337 __raw_writel(1 << bit, base + IC_FALLINGCLR); in au1x_ic0_ack()
338 __raw_writel( in au1x_ic0_ack()
[all...]
H A Dusb.c112 __raw_writel(r, base + USB_DWC_CTRL2); in __au1300_usb_phyctl()
118 __raw_writel(r, base + USB_DWC_CTRL2); in __au1300_usb_phyctl()
128 __raw_writel(1, base + USB_DWC_CTRL7); /* start OHCI clock */ in __au1300_ohci_control()
134 __raw_writel(r, base + USB_DWC_CTRL3); in __au1300_ohci_control()
141 __raw_writel(r, base + USB_INT_ENABLE); in __au1300_ohci_control()
145 __raw_writel(0, base + USB_DWC_CTRL7); in __au1300_ohci_control()
150 __raw_writel(r, base + USB_INT_ENABLE); in __au1300_ohci_control()
156 __raw_writel(r, base + USB_DWC_CTRL3); in __au1300_ohci_control()
170 __raw_writel(r, base + USB_DWC_CTRL3); in __au1300_ehci_control()
175 __raw_writel( in __au1300_ehci_control()
[all...]
H A Dvss.c27 __raw_writel(3, base + VSS_CLKRST); /* enable clock, assert reset */ in __enable_block()
30 __raw_writel(0x01fffffe, base + VSS_GATE); /* maximum setup time */ in __enable_block()
34 __raw_writel(0x01, base + VSS_FTR); in __enable_block()
36 __raw_writel(0x03, base + VSS_FTR); in __enable_block()
38 __raw_writel(0x07, base + VSS_FTR); in __enable_block()
40 __raw_writel(0x0f, base + VSS_FTR); in __enable_block()
43 __raw_writel(0x01ffffff, base + VSS_GATE); /* start FSM too */ in __enable_block()
46 __raw_writel(2, base + VSS_CLKRST); /* deassert reset */ in __enable_block()
49 __raw_writel(0x1f, base + VSS_FTR); /* enable isolation cells */ in __enable_block()
58 __raw_writel( in __disable_block()
[all...]
/kernel/linux/linux-5.10/arch/mips/kernel/
H A Dcevt-txx9.c63 __raw_writel(TCR_BASE, &tmrptr->tcr); in txx9_clocksource_init()
64 __raw_writel(0, &tmrptr->tisr); in txx9_clocksource_init()
65 __raw_writel(TIMER_CCD, &tmrptr->ccdr); in txx9_clocksource_init()
66 __raw_writel(TXx9_TMITMR_TZCE, &tmrptr->itmr); in txx9_clocksource_init()
67 __raw_writel(1 << TXX9_CLOCKSOURCE_BITS, &tmrptr->cpra); in txx9_clocksource_init()
68 __raw_writel(TCR_BASE | TXx9_TMTCR_TCE, &tmrptr->tcr); in txx9_clocksource_init()
83 __raw_writel(TCR_BASE, &tmrptr->tcr); in txx9tmr_stop_and_clear()
85 __raw_writel(0, &tmrptr->tisr); in txx9tmr_stop_and_clear()
96 __raw_writel(TXx9_TMITMR_TIIE | TXx9_TMITMR_TZCE, &tmrptr->itmr); in txx9tmr_set_state_periodic()
98 __raw_writel(((u6 in txx9tmr_set_state_periodic()
[all...]
/kernel/linux/linux-6.6/arch/mips/kernel/
H A Dcevt-txx9.c63 __raw_writel(TCR_BASE, &tmrptr->tcr); in txx9_clocksource_init()
64 __raw_writel(0, &tmrptr->tisr); in txx9_clocksource_init()
65 __raw_writel(TIMER_CCD, &tmrptr->ccdr); in txx9_clocksource_init()
66 __raw_writel(TXx9_TMITMR_TZCE, &tmrptr->itmr); in txx9_clocksource_init()
67 __raw_writel(1 << TXX9_CLOCKSOURCE_BITS, &tmrptr->cpra); in txx9_clocksource_init()
68 __raw_writel(TCR_BASE | TXx9_TMTCR_TCE, &tmrptr->tcr); in txx9_clocksource_init()
83 __raw_writel(TCR_BASE, &tmrptr->tcr); in txx9tmr_stop_and_clear()
85 __raw_writel(0, &tmrptr->tisr); in txx9tmr_stop_and_clear()
96 __raw_writel(TXx9_TMITMR_TIIE | TXx9_TMITMR_TZCE, &tmrptr->itmr); in txx9tmr_set_state_periodic()
98 __raw_writel(((u6 in txx9tmr_set_state_periodic()
[all...]
/kernel/linux/linux-5.10/arch/mips/sgi-ip22/
H A Dip22-nvram.c36 __raw_writel(__raw_readl(ptr) & ~EEPROM_DATO, ptr); \
37 __raw_writel(__raw_readl(ptr) & ~EEPROM_ECLK, ptr); \
38 __raw_writel(__raw_readl(ptr) & ~EEPROM_EPROT, ptr); \
40 __raw_writel(__raw_readl(ptr) | EEPROM_CSEL, ptr); \
41 __raw_writel(__raw_readl(ptr) | EEPROM_ECLK, ptr); })
45 __raw_writel(__raw_readl(ptr) & ~EEPROM_ECLK, ptr); \
46 __raw_writel(__raw_readl(ptr) & ~EEPROM_CSEL, ptr); \
47 __raw_writel(__raw_readl(ptr) | EEPROM_EPROT, ptr); \
48 __raw_writel(__raw_readl(ptr) | EEPROM_ECLK, ptr); })
64 __raw_writel(__raw_read in eeprom_cmd()
[all...]
/kernel/linux/linux-6.6/arch/mips/sgi-ip22/
H A Dip22-nvram.c36 __raw_writel(__raw_readl(ptr) & ~EEPROM_DATO, ptr); \
37 __raw_writel(__raw_readl(ptr) & ~EEPROM_ECLK, ptr); \
38 __raw_writel(__raw_readl(ptr) & ~EEPROM_EPROT, ptr); \
40 __raw_writel(__raw_readl(ptr) | EEPROM_CSEL, ptr); \
41 __raw_writel(__raw_readl(ptr) | EEPROM_ECLK, ptr); })
45 __raw_writel(__raw_readl(ptr) & ~EEPROM_ECLK, ptr); \
46 __raw_writel(__raw_readl(ptr) & ~EEPROM_CSEL, ptr); \
47 __raw_writel(__raw_readl(ptr) | EEPROM_EPROT, ptr); \
48 __raw_writel(__raw_readl(ptr) | EEPROM_ECLK, ptr); })
64 __raw_writel(__raw_read in eeprom_cmd()
[all...]
/kernel/linux/linux-5.10/arch/arm/mach-mmp/
H A Dtime.c55 __raw_writel(1, mmp_timer_base + TMR_CVWR(1)); in timer_read()
75 __raw_writel(0x01, mmp_timer_base + TMR_ICR(0)); in timer_interrupt()
80 __raw_writel(0x02, mmp_timer_base + TMR_CER); in timer_interrupt()
97 __raw_writel(0x02, mmp_timer_base + TMR_CER); in timer_set_next_event()
102 __raw_writel(0x01, mmp_timer_base + TMR_ICR(0)); in timer_set_next_event()
103 __raw_writel(0x01, mmp_timer_base + TMR_IER(0)); in timer_set_next_event()
108 __raw_writel(delta - 1, mmp_timer_base + TMR_TN_MM(0, 0)); in timer_set_next_event()
113 __raw_writel(0x03, mmp_timer_base + TMR_CER); in timer_set_next_event()
126 __raw_writel(0x00, mmp_timer_base + TMR_IER(0)); in timer_set_shutdown()
158 __raw_writel( in timer_config()
[all...]
H A Dpm-mmp2.c48 __raw_writel(data, MPMU_WUCRM_PJ); in mmp2_set_wake()
53 __raw_writel(data, MPMU_WUCRM_PJ); in mmp2_set_wake()
64 __raw_writel(0x0, CIU_REG(0x64)); in pm_scu_clk_disable()
65 __raw_writel(0x0, CIU_REG(0x68)); in pm_scu_clk_disable()
70 __raw_writel(val, CIU_REG(0x1c)); in pm_scu_clk_disable()
80 __raw_writel(0x03003003, CIU_REG(0x64)); in pm_scu_clk_enable()
81 __raw_writel(0x00303030, CIU_REG(0x68)); in pm_scu_clk_enable()
86 __raw_writel(val, CIU_REG(0x1c)); in pm_scu_clk_enable()
97 __raw_writel(0x0000a010, MPMU_CGR_PJ); in pm_mpmu_clk_disable()
104 __raw_writel( in pm_mpmu_clk_enable()
[all...]
/kernel/linux/linux-6.6/arch/arm/mach-mmp/
H A Dtime.c50 __raw_writel(1, mmp_timer_base + TMR_CVWR(1)); in timer_read()
70 __raw_writel(0x01, mmp_timer_base + TMR_ICR(0)); in timer_interrupt()
75 __raw_writel(0x02, mmp_timer_base + TMR_CER); in timer_interrupt()
92 __raw_writel(0x02, mmp_timer_base + TMR_CER); in timer_set_next_event()
97 __raw_writel(0x01, mmp_timer_base + TMR_ICR(0)); in timer_set_next_event()
98 __raw_writel(0x01, mmp_timer_base + TMR_IER(0)); in timer_set_next_event()
103 __raw_writel(delta - 1, mmp_timer_base + TMR_TN_MM(0, 0)); in timer_set_next_event()
108 __raw_writel(0x03, mmp_timer_base + TMR_CER); in timer_set_next_event()
121 __raw_writel(0x00, mmp_timer_base + TMR_IER(0)); in timer_set_shutdown()
153 __raw_writel( in timer_config()
[all...]
/kernel/linux/linux-5.10/arch/mips/pci/
H A Dops-tx4927.c64 __raw_writel(((bus->number & 0xff) << 0x10) in mkaddr()
69 __raw_writel((__raw_readl(&pcicptr->pcistatus) & 0x0000ffff) in mkaddr()
84 __raw_writel((__raw_readl(&pcicptr->pcistatus) & 0x0000ffff) in check_abort()
130 __raw_writel(val, &pcicptr->g2pcfgdata); in icd_writel()
239 __raw_writel(__raw_readl(&pcicptr->pciccfg) in tx4927_pcic_setup()
247 __raw_writel((channel->io_resource->end - channel->io_resource->start) in tx4927_pcic_setup()
261 __raw_writel(0, &pcicptr->g2pmmask[i]); in tx4927_pcic_setup()
266 __raw_writel((channel->mem_resource->end in tx4927_pcic_setup()
281 __raw_writel(0, &pcicptr->p2giopbase); /* 256B */ in tx4927_pcic_setup()
284 __raw_writel( in tx4927_pcic_setup()
[all...]
/kernel/linux/linux-6.6/arch/mips/pci/
H A Dops-tx4927.c64 __raw_writel(((bus->number & 0xff) << 0x10) in mkaddr()
69 __raw_writel((__raw_readl(&pcicptr->pcistatus) & 0x0000ffff) in mkaddr()
84 __raw_writel((__raw_readl(&pcicptr->pcistatus) & 0x0000ffff) in check_abort()
130 __raw_writel(val, &pcicptr->g2pcfgdata); in icd_writel()
239 __raw_writel(__raw_readl(&pcicptr->pciccfg) in tx4927_pcic_setup()
247 __raw_writel((channel->io_resource->end - channel->io_resource->start) in tx4927_pcic_setup()
261 __raw_writel(0, &pcicptr->g2pmmask[i]); in tx4927_pcic_setup()
266 __raw_writel((channel->mem_resource->end in tx4927_pcic_setup()
281 __raw_writel(0, &pcicptr->p2giopbase); /* 256B */ in tx4927_pcic_setup()
284 __raw_writel( in tx4927_pcic_setup()
[all...]
/kernel/linux/linux-5.10/arch/sh/drivers/pci/
H A Dpci-sh7780.c127 __raw_writel(cmd, hose->reg_base + SH4_PCIAINT); in sh7780_pci_err_irq()
140 __raw_writel(cmd, hose->reg_base + SH4_PCIINT); in sh7780_pci_err_irq()
154 __raw_writel(SH4_PCIINTM_SDIM, hose->reg_base + SH4_PCIINTM); in sh7780_pci_serr_irq()
169 __raw_writel(0, hose->reg_base + SH4_PCIAINT); in sh7780_pci_setup_irqs()
200 __raw_writel(SH4_PCIAINT_MBKN | SH4_PCIAINT_TBTO | SH4_PCIAINT_MBTO | \ in sh7780_pci_setup_irqs()
205 __raw_writel(SH4_PCIINTM_TTADIM | SH4_PCIINTM_TMTOIM | \ in sh7780_pci_setup_irqs()
231 __raw_writel(tmp, hose->reg_base + SH4_PCICR); in sh7780_pci66_init()
241 __raw_writel(tmp, hose->reg_base + SH4_PCICR); in sh7780_pci66_init()
258 __raw_writel(PCIECR_ENBL, PCIECR); in sh7780_pci_init()
261 __raw_writel(SH4_PCICR_PREFI in sh7780_pci_init()
[all...]
/kernel/linux/linux-6.6/arch/sh/drivers/pci/
H A Dpci-sh7780.c127 __raw_writel(cmd, hose->reg_base + SH4_PCIAINT); in sh7780_pci_err_irq()
140 __raw_writel(cmd, hose->reg_base + SH4_PCIINT); in sh7780_pci_err_irq()
154 __raw_writel(SH4_PCIINTM_SDIM, hose->reg_base + SH4_PCIINTM); in sh7780_pci_serr_irq()
169 __raw_writel(0, hose->reg_base + SH4_PCIAINT); in sh7780_pci_setup_irqs()
200 __raw_writel(SH4_PCIAINT_MBKN | SH4_PCIAINT_TBTO | SH4_PCIAINT_MBTO | \ in sh7780_pci_setup_irqs()
205 __raw_writel(SH4_PCIINTM_TTADIM | SH4_PCIINTM_TMTOIM | \ in sh7780_pci_setup_irqs()
231 __raw_writel(tmp, hose->reg_base + SH4_PCICR); in sh7780_pci66_init()
241 __raw_writel(tmp, hose->reg_base + SH4_PCICR); in sh7780_pci66_init()
258 __raw_writel(PCIECR_ENBL, PCIECR); in sh7780_pci_init()
261 __raw_writel(SH4_PCICR_PREFI in sh7780_pci_init()
[all...]
/kernel/linux/linux-5.10/arch/m68k/coldfire/
H A Dpci.c71 __raw_writel(PCICAR_E | addr, PCICAR); in mcf_pci_readconfig()
87 __raw_writel(0, PCICAR); in mcf_pci_readconfig()
103 __raw_writel(PCICAR_E | addr, PCICAR); in mcf_pci_writeconfig()
115 __raw_writel(cpu_to_le32(value), addr); in mcf_pci_writeconfig()
119 __raw_writel(0, PCICAR); in mcf_pci_writeconfig()
178 __raw_writel(PCIGSCR_RESET, PCIGSCR); in mcf_pci_init()
179 __raw_writel(0, PCITCR); in mcf_pci_init()
185 __raw_writel(PACR_INTMPRI | PACR_INTMINTE | PACR_EXTMPRI(0x1f) | in mcf_pci_init()
193 __raw_writel(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | in mcf_pci_init()
195 __raw_writel(PCICR1_L in mcf_pci_init()
[all...]
/kernel/linux/linux-6.6/arch/m68k/coldfire/
H A Dpci.c71 __raw_writel(PCICAR_E | addr, PCICAR); in mcf_pci_readconfig()
87 __raw_writel(0, PCICAR); in mcf_pci_readconfig()
103 __raw_writel(PCICAR_E | addr, PCICAR); in mcf_pci_writeconfig()
115 __raw_writel(cpu_to_le32(value), addr); in mcf_pci_writeconfig()
119 __raw_writel(0, PCICAR); in mcf_pci_writeconfig()
178 __raw_writel(PCIGSCR_RESET, PCIGSCR); in mcf_pci_init()
179 __raw_writel(0, PCITCR); in mcf_pci_init()
185 __raw_writel(PACR_INTMPRI | PACR_INTMINTE | PACR_EXTMPRI(0x1f) | in mcf_pci_init()
193 __raw_writel(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | in mcf_pci_init()
195 __raw_writel(PCICR1_L in mcf_pci_init()
[all...]
/kernel/linux/linux-5.10/arch/arm/mach-s3c/
H A Dmach-n30.c452 __raw_writel(0x007fffff, S3C2410_GPACON); in n30_hwinit()
454 __raw_writel(0x007fefff, S3C2410_GPACON); in n30_hwinit()
455 __raw_writel(0x00000000, S3C2410_GPADAT); in n30_hwinit()
470 __raw_writel(0x00154556, S3C2410_GPBCON); in n30_hwinit()
471 __raw_writel(0x00000750, S3C2410_GPBDAT); in n30_hwinit()
472 __raw_writel(0x00000073, S3C2410_GPBUP); in n30_hwinit()
489 __raw_writel(0xaaa80618, S3C2410_GPCCON); in n30_hwinit()
490 __raw_writel(0x0000014c, S3C2410_GPCDAT); in n30_hwinit()
491 __raw_writel(0x0000fef2, S3C2410_GPCUP); in n30_hwinit()
501 __raw_writel( in n30_hwinit()
[all...]
/kernel/linux/linux-5.10/arch/arm/mach-pxa/
H A Dsmemc.c36 __raw_writel(msc[0], MSC0); in pxa3xx_smemc_resume()
37 __raw_writel(msc[1], MSC1); in pxa3xx_smemc_resume()
38 __raw_writel(sxcnfg, SXCNFG); in pxa3xx_smemc_resume()
39 __raw_writel(memclkcfg, MEMCLKCFG); in pxa3xx_smemc_resume()
40 __raw_writel(csadrcfg[0], CSADRCFG0); in pxa3xx_smemc_resume()
41 __raw_writel(csadrcfg[1], CSADRCFG1); in pxa3xx_smemc_resume()
42 __raw_writel(csadrcfg[2], CSADRCFG2); in pxa3xx_smemc_resume()
43 __raw_writel(csadrcfg[3], CSADRCFG3); in pxa3xx_smemc_resume()
45 __raw_writel(0x2, CSMSADRCFG); in pxa3xx_smemc_resume()
64 __raw_writel( in smemc_init()
[all...]
/kernel/linux/linux-5.10/arch/sh/mm/
H A Dtlb-pteaex.c32 __raw_writel(vpn, MMU_PTEH); in __update_tlb()
35 __raw_writel(get_asid(), MMU_PTEAEX); in __update_tlb()
47 __raw_writel(pte.pte_high, MMU_PTEA); in __update_tlb()
56 __raw_writel(pteval, MMU_PTEL); in __update_tlb()
73 __raw_writel(page, MMU_UTLB_ADDRESS_ARRAY | MMU_PAGE_ASSOC_BIT); in local_flush_tlb_one()
74 __raw_writel(asid, MMU_UTLB_ADDRESS_ARRAY2 | MMU_PAGE_ASSOC_BIT); in local_flush_tlb_one()
75 __raw_writel(page, MMU_ITLB_ADDRESS_ARRAY | MMU_PAGE_ASSOC_BIT); in local_flush_tlb_one()
76 __raw_writel(asid, MMU_ITLB_ADDRESS_ARRAY2 | MMU_PAGE_ASSOC_BIT); in local_flush_tlb_one()
98 __raw_writel(0x0, MMU_UTLB_ADDRESS_ARRAY | (i << 8)); in local_flush_tlb_all()
101 __raw_writel( in local_flush_tlb_all()
[all...]
/kernel/linux/linux-6.6/arch/arm/mach-pxa/
H A Dsmemc.c37 __raw_writel(msc[0], MSC0); in pxa3xx_smemc_resume()
38 __raw_writel(msc[1], MSC1); in pxa3xx_smemc_resume()
39 __raw_writel(sxcnfg, SXCNFG); in pxa3xx_smemc_resume()
40 __raw_writel(memclkcfg, MEMCLKCFG); in pxa3xx_smemc_resume()
41 __raw_writel(csadrcfg[0], CSADRCFG0); in pxa3xx_smemc_resume()
42 __raw_writel(csadrcfg[1], CSADRCFG1); in pxa3xx_smemc_resume()
43 __raw_writel(csadrcfg[2], CSADRCFG2); in pxa3xx_smemc_resume()
44 __raw_writel(csadrcfg[3], CSADRCFG3); in pxa3xx_smemc_resume()
46 __raw_writel(0x2, CSMSADRCFG); in pxa3xx_smemc_resume()
65 __raw_writel( in smemc_init()
[all...]
/kernel/linux/linux-6.6/arch/sh/mm/
H A Dtlb-pteaex.c32 __raw_writel(vpn, MMU_PTEH); in __update_tlb()
35 __raw_writel(get_asid(), MMU_PTEAEX); in __update_tlb()
47 __raw_writel(pte.pte_high, MMU_PTEA); in __update_tlb()
56 __raw_writel(pteval, MMU_PTEL); in __update_tlb()
73 __raw_writel(page, MMU_UTLB_ADDRESS_ARRAY | MMU_PAGE_ASSOC_BIT); in local_flush_tlb_one()
74 __raw_writel(asid, MMU_UTLB_ADDRESS_ARRAY2 | MMU_PAGE_ASSOC_BIT); in local_flush_tlb_one()
75 __raw_writel(page, MMU_ITLB_ADDRESS_ARRAY | MMU_PAGE_ASSOC_BIT); in local_flush_tlb_one()
76 __raw_writel(asid, MMU_ITLB_ADDRESS_ARRAY2 | MMU_PAGE_ASSOC_BIT); in local_flush_tlb_one()
98 __raw_writel(0x0, MMU_UTLB_ADDRESS_ARRAY | (i << 8)); in local_flush_tlb_all()
101 __raw_writel( in local_flush_tlb_all()
[all...]
/kernel/linux/linux-5.10/arch/mips/loongson32/common/
H A Dirq.c28 __raw_writel(__raw_readl(LS1X_INTC_INTCLR(n)) in ls1x_irq_ack()
37 __raw_writel(__raw_readl(LS1X_INTC_INTIEN(n)) in ls1x_irq_mask()
46 __raw_writel(__raw_readl(LS1X_INTC_INTIEN(n)) in ls1x_irq_mask_ack()
48 __raw_writel(__raw_readl(LS1X_INTC_INTCLR(n)) in ls1x_irq_mask_ack()
57 __raw_writel(__raw_readl(LS1X_INTC_INTIEN(n)) in ls1x_irq_unmask()
68 __raw_writel(__raw_readl(LS1X_INTC_INTPOL(n)) in ls1x_irq_settype()
70 __raw_writel(__raw_readl(LS1X_INTC_INTEDGE(n)) in ls1x_irq_settype()
74 __raw_writel(__raw_readl(LS1X_INTC_INTPOL(n)) in ls1x_irq_settype()
76 __raw_writel(__raw_readl(LS1X_INTC_INTEDGE(n)) in ls1x_irq_settype()
80 __raw_writel(__raw_read in ls1x_irq_settype()
[all...]

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