Home
last modified time | relevance | path

Searched refs:REG_WRITE (Results 1 - 25 of 204) sorted by relevance

123456789

/kernel/linux/linux-5.10/drivers/gpu/drm/gma500/
H A Dmdfld_dsi_dpi.c138 REG_WRITE(pipeconf_reg, BIT(31)); in dsi_set_pipe_plane_enable_state()
145 REG_WRITE(dspcntr_reg, dspcntr); in dsi_set_pipe_plane_enable_state()
161 REG_WRITE(dspbase_reg, REG_READ(dspbase_reg)); in dsi_set_pipe_plane_enable_state()
247 REG_WRITE(gen_data_reg, 0x00008036); in mdfld_dsi_tpo_ic_init()
249 REG_WRITE(gen_ctrl_reg, gen_ctrl_val | (0x02 << WORD_COUNTS_POS)); in mdfld_dsi_tpo_ic_init()
253 REG_WRITE(gen_data_reg, 0x005a5af0); in mdfld_dsi_tpo_ic_init()
255 REG_WRITE(gen_ctrl_reg, gen_ctrl_val | (0x03 << WORD_COUNTS_POS)); in mdfld_dsi_tpo_ic_init()
259 REG_WRITE(gen_data_reg, 0x005a5af1); in mdfld_dsi_tpo_ic_init()
261 REG_WRITE(gen_ctrl_reg, gen_ctrl_val | (0x03 << WORD_COUNTS_POS)); in mdfld_dsi_tpo_ic_init()
265 REG_WRITE(gen_data_re in mdfld_dsi_tpo_ic_init()
[all...]
H A Dmdfld_intel_display.c169 REG_WRITE(map->stride, fb->pitches[0]); in mdfld__intel_pipe_set_base()
188 REG_WRITE(map->cntr, dspcntr); in mdfld__intel_pipe_set_base()
192 REG_WRITE(map->linoff, offset); in mdfld__intel_pipe_set_base()
194 REG_WRITE(map->surf, start); in mdfld__intel_pipe_set_base()
222 REG_WRITE(map->cntr, in mdfld_disable_crtc()
225 REG_WRITE(map->base, REG_READ(map->base)); in mdfld_disable_crtc()
236 REG_WRITE(map->conf, temp); in mdfld_disable_crtc()
249 REG_WRITE(map->dpll, temp); in mdfld_disable_crtc()
257 REG_WRITE(map->dpll, temp | MDFLD_PWR_GATE_EN); in mdfld_disable_crtc()
306 REG_WRITE(ma in mdfld_crtc_dpms()
[all...]
H A Doaktrail_hdmi.c289 REG_WRITE(VGACNTRL, VGA_DISP_DISABLE); in oaktrail_crtc_hdmi_mode_set()
294 REG_WRITE(DPLL_CTRL, dpll | (DPLL_PWRDN | DPLL_RESET)); in oaktrail_crtc_hdmi_mode_set()
295 REG_WRITE(DPLL_DIV_CTRL, 0x00000000); in oaktrail_crtc_hdmi_mode_set()
296 REG_WRITE(DPLL_STATUS, 0x1); in oaktrail_crtc_hdmi_mode_set()
311 REG_WRITE(DPLL_CTRL, 0x00000008); in oaktrail_crtc_hdmi_mode_set()
312 REG_WRITE(DPLL_DIV_CTRL, ((clock.nf << 6) | clock.nr)); in oaktrail_crtc_hdmi_mode_set()
313 REG_WRITE(DPLL_ADJUST, ((clock.nf >> 14) - 1)); in oaktrail_crtc_hdmi_mode_set()
314 REG_WRITE(DPLL_CTRL, (dpll | (clock.np << DPLL_PDIV_SHIFT) | DPLL_ENSTAT | DPLL_DITHEN)); in oaktrail_crtc_hdmi_mode_set()
315 REG_WRITE(DPLL_UPDATE, 0x80000000); in oaktrail_crtc_hdmi_mode_set()
316 REG_WRITE(DPLL_CLK_ENABL in oaktrail_crtc_hdmi_mode_set()
[all...]
H A Dgma_display.c83 REG_WRITE(map->stride, fb->pitches[0]); in gma_pipe_set_base()
107 REG_WRITE(map->cntr, dspcntr); in gma_pipe_set_base()
116 REG_WRITE(map->base, offset + start); in gma_pipe_set_base()
119 REG_WRITE(map->base, offset); in gma_pipe_set_base()
121 REG_WRITE(map->surf, start); in gma_pipe_set_base()
156 REG_WRITE(palreg + 4 * i, in gma_crtc_load_lut()
217 REG_WRITE(map->dpll, temp); in gma_crtc_dpms()
221 REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE); in gma_crtc_dpms()
225 REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE); in gma_crtc_dpms()
234 REG_WRITE(ma in gma_crtc_dpms()
[all...]
H A Dcdv_intel_display.c139 REG_WRITE(SB_ADDR, reg); in cdv_sb_read()
140 REG_WRITE(SB_PCKT, in cdv_sb_read()
174 REG_WRITE(SB_ADDR, reg); in cdv_sb_write()
175 REG_WRITE(SB_DATA, val); in cdv_sb_write()
176 REG_WRITE(SB_PCKT, in cdv_sb_write()
201 REG_WRITE(DPIO_CFG, 0); in cdv_sb_reset()
203 REG_WRITE(DPIO_CFG, DPIO_MODE_SELECT_0 | DPIO_CMN_RESET_N); in cdv_sb_reset()
226 REG_WRITE(dpll_reg, DPLL_SYNCLOCK_ENABLE | DPLL_VGA_MODE_DIS); in cdv_dpll_set_clock_cdv()
474 REG_WRITE(FW_BLC_SELF, (REG_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN)); in cdv_disable_sr()
482 REG_WRITE(OV_OVAD in cdv_disable_sr()
[all...]
H A Dcdv_device.c35 REG_WRITE(vga_reg, VGA_DISP_DISABLE); in cdv_disable_vga()
135 REG_WRITE(BLC_PWM_CTL, (blc_pwm_ctl | in cdv_set_brightness()
318 REG_WRITE(DSPCLK_GATE_D, regs->cdv.saveDSPCLK_GATE_D); in cdv_restore_display_registers()
319 REG_WRITE(RAMCLK_GATE_D, regs->cdv.saveRAMCLK_GATE_D); in cdv_restore_display_registers()
322 REG_WRITE(DPIO_CFG, 0); in cdv_restore_display_registers()
323 REG_WRITE(DPIO_CFG, DPIO_MODE_SELECT_0 | DPIO_CMN_RESET_N); in cdv_restore_display_registers()
327 REG_WRITE(DPLL_A, temp | DPLL_SYNCLOCK_ENABLE); in cdv_restore_display_registers()
333 REG_WRITE(DPLL_B, temp | DPLL_SYNCLOCK_ENABLE); in cdv_restore_display_registers()
339 REG_WRITE(DSPFW1, regs->cdv.saveDSPFW[0]); in cdv_restore_display_registers()
340 REG_WRITE(DSPFW in cdv_restore_display_registers()
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dmub/src/
H A Ddmub_dcn30.c102 REG_WRITE(DMCUB_REGION3_CW0_OFFSET, offset.u.low_part); in dmub_dcn30_backdoor_load()
103 REG_WRITE(DMCUB_REGION3_CW0_OFFSET_HIGH, offset.u.high_part); in dmub_dcn30_backdoor_load()
104 REG_WRITE(DMCUB_REGION3_CW0_BASE_ADDRESS, cw0->region.base); in dmub_dcn30_backdoor_load()
111 REG_WRITE(DMCUB_REGION3_CW1_OFFSET, offset.u.low_part); in dmub_dcn30_backdoor_load()
112 REG_WRITE(DMCUB_REGION3_CW1_OFFSET_HIGH, offset.u.high_part); in dmub_dcn30_backdoor_load()
113 REG_WRITE(DMCUB_REGION3_CW1_BASE_ADDRESS, cw1->region.base); in dmub_dcn30_backdoor_load()
136 REG_WRITE(DMCUB_REGION3_CW2_OFFSET, offset.u.low_part); in dmub_dcn30_setup_windows()
137 REG_WRITE(DMCUB_REGION3_CW2_OFFSET_HIGH, offset.u.high_part); in dmub_dcn30_setup_windows()
138 REG_WRITE(DMCUB_REGION3_CW2_BASE_ADDRESS, cw2->region.base); in dmub_dcn30_setup_windows()
143 REG_WRITE(DMCUB_REGION3_CW2_OFFSE in dmub_dcn30_setup_windows()
[all...]
H A Ddmub_dcn32.c125 REG_WRITE(DMCUB_INBOX1_RPTR, 0); in dmub_dcn32_reset()
126 REG_WRITE(DMCUB_INBOX1_WPTR, 0); in dmub_dcn32_reset()
127 REG_WRITE(DMCUB_OUTBOX1_RPTR, 0); in dmub_dcn32_reset()
128 REG_WRITE(DMCUB_OUTBOX1_WPTR, 0); in dmub_dcn32_reset()
129 REG_WRITE(DMCUB_OUTBOX0_RPTR, 0); in dmub_dcn32_reset()
130 REG_WRITE(DMCUB_OUTBOX0_WPTR, 0); in dmub_dcn32_reset()
131 REG_WRITE(DMCUB_SCRATCH0, 0); in dmub_dcn32_reset()
141 REG_WRITE(DMCUB_SCRATCH15, dmub->psp_version & 0x001100FF); in dmub_dcn32_reset_release()
159 REG_WRITE(DMCUB_REGION3_CW0_OFFSET, offset.u.low_part); in dmub_dcn32_backdoor_load()
160 REG_WRITE(DMCUB_REGION3_CW0_OFFSET_HIG in dmub_dcn32_backdoor_load()
[all...]
H A Ddmub_dcn20.c139 REG_WRITE(DMCUB_INBOX1_RPTR, 0); in dmub_dcn20_reset()
140 REG_WRITE(DMCUB_INBOX1_WPTR, 0); in dmub_dcn20_reset()
141 REG_WRITE(DMCUB_OUTBOX1_RPTR, 0); in dmub_dcn20_reset()
142 REG_WRITE(DMCUB_OUTBOX1_WPTR, 0); in dmub_dcn20_reset()
143 REG_WRITE(DMCUB_SCRATCH0, 0); in dmub_dcn20_reset()
149 REG_WRITE(DMCUB_SCRATCH15, dmub->psp_version & 0x001100FF); in dmub_dcn20_reset_release()
169 REG_WRITE(DMCUB_REGION3_CW0_OFFSET, offset.u.low_part); in dmub_dcn20_backdoor_load()
170 REG_WRITE(DMCUB_REGION3_CW0_OFFSET_HIGH, offset.u.high_part); in dmub_dcn20_backdoor_load()
171 REG_WRITE(DMCUB_REGION3_CW0_BASE_ADDRESS, cw0->region.base); in dmub_dcn20_backdoor_load()
178 REG_WRITE(DMCUB_REGION3_CW1_OFFSE in dmub_dcn20_backdoor_load()
[all...]
H A Ddmub_dcn31.c131 REG_WRITE(DMCUB_INBOX1_RPTR, 0); in dmub_dcn31_reset()
132 REG_WRITE(DMCUB_INBOX1_WPTR, 0); in dmub_dcn31_reset()
133 REG_WRITE(DMCUB_OUTBOX1_RPTR, 0); in dmub_dcn31_reset()
134 REG_WRITE(DMCUB_OUTBOX1_WPTR, 0); in dmub_dcn31_reset()
135 REG_WRITE(DMCUB_OUTBOX0_RPTR, 0); in dmub_dcn31_reset()
136 REG_WRITE(DMCUB_OUTBOX0_WPTR, 0); in dmub_dcn31_reset()
137 REG_WRITE(DMCUB_SCRATCH0, 0); in dmub_dcn31_reset()
147 REG_WRITE(DMCUB_SCRATCH15, dmub->psp_version & 0x001100FF); in dmub_dcn31_reset_release()
165 REG_WRITE(DMCUB_REGION3_CW0_OFFSET, offset.u.low_part); in dmub_dcn31_backdoor_load()
166 REG_WRITE(DMCUB_REGION3_CW0_OFFSET_HIG in dmub_dcn31_backdoor_load()
[all...]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dmub/src/
H A Ddmub_dcn20.c129 REG_WRITE(DMCUB_INBOX1_RPTR, 0); in dmub_dcn20_reset()
130 REG_WRITE(DMCUB_INBOX1_WPTR, 0); in dmub_dcn20_reset()
131 REG_WRITE(DMCUB_SCRATCH0, 0); in dmub_dcn20_reset()
137 REG_WRITE(DMCUB_SCRATCH15, dmub->psp_version & 0x001100FF); in dmub_dcn20_reset_release()
157 REG_WRITE(DMCUB_REGION3_CW0_OFFSET, offset.u.low_part); in dmub_dcn20_backdoor_load()
158 REG_WRITE(DMCUB_REGION3_CW0_OFFSET_HIGH, offset.u.high_part); in dmub_dcn20_backdoor_load()
159 REG_WRITE(DMCUB_REGION3_CW0_BASE_ADDRESS, cw0->region.base); in dmub_dcn20_backdoor_load()
166 REG_WRITE(DMCUB_REGION3_CW1_OFFSET, offset.u.low_part); in dmub_dcn20_backdoor_load()
167 REG_WRITE(DMCUB_REGION3_CW1_OFFSET_HIGH, offset.u.high_part); in dmub_dcn20_backdoor_load()
168 REG_WRITE(DMCUB_REGION3_CW1_BASE_ADDRES in dmub_dcn20_backdoor_load()
[all...]
H A Ddmub_dcn30.c98 REG_WRITE(DMCUB_REGION3_CW0_OFFSET, offset.u.low_part); in dmub_dcn30_backdoor_load()
99 REG_WRITE(DMCUB_REGION3_CW0_OFFSET_HIGH, offset.u.high_part); in dmub_dcn30_backdoor_load()
100 REG_WRITE(DMCUB_REGION3_CW0_BASE_ADDRESS, cw0->region.base); in dmub_dcn30_backdoor_load()
107 REG_WRITE(DMCUB_REGION3_CW1_OFFSET, offset.u.low_part); in dmub_dcn30_backdoor_load()
108 REG_WRITE(DMCUB_REGION3_CW1_OFFSET_HIGH, offset.u.high_part); in dmub_dcn30_backdoor_load()
109 REG_WRITE(DMCUB_REGION3_CW1_BASE_ADDRESS, cw1->region.base); in dmub_dcn30_backdoor_load()
132 REG_WRITE(DMCUB_REGION3_CW2_OFFSET, offset.u.low_part); in dmub_dcn30_setup_windows()
133 REG_WRITE(DMCUB_REGION3_CW2_OFFSET_HIGH, offset.u.high_part); in dmub_dcn30_setup_windows()
134 REG_WRITE(DMCUB_REGION3_CW2_BASE_ADDRESS, cw2->region.base); in dmub_dcn30_setup_windows()
139 REG_WRITE(DMCUB_REGION3_CW2_OFFSE in dmub_dcn30_setup_windows()
[all...]
/kernel/linux/linux-5.10/drivers/net/wireless/ath/
H A Dkey.c26 #define REG_WRITE(_ah, _reg, _val) (common->ops->write)(_ah, _val, _reg) macro
57 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0); in ath_hw_keyreset()
58 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0); in ath_hw_keyreset()
59 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0); in ath_hw_keyreset()
60 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0); in ath_hw_keyreset()
61 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0); in ath_hw_keyreset()
62 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR); in ath_hw_keyreset()
63 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0); in ath_hw_keyreset()
64 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0); in ath_hw_keyreset()
69 REG_WRITE(a in ath_hw_keyreset()
[all...]
H A Dhw.c24 #define REG_WRITE(_ah, _reg, _val) (common->ops->write)(_ah, _val, _reg) macro
123 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr)); in ath_hw_setbssidmask()
126 REG_WRITE(ah, AR_STA_ID1, id1); in ath_hw_setbssidmask()
128 REG_WRITE(ah, AR_BSSMSKL, get_unaligned_le32(common->bssidmask)); in ath_hw_setbssidmask()
129 REG_WRITE(ah, AR_BSSMSKU, get_unaligned_le16(common->bssidmask + 4)); in ath_hw_setbssidmask()
148 REG_WRITE(ah, AR_MIBC, AR_MIBC_FMC); in ath_hw_cycle_counters_update()
157 REG_WRITE(ah, AR_CCCNT, 0); in ath_hw_cycle_counters_update()
158 REG_WRITE(ah, AR_RFCNT, 0); in ath_hw_cycle_counters_update()
159 REG_WRITE(ah, AR_RCCNT, 0); in ath_hw_cycle_counters_update()
160 REG_WRITE(a in ath_hw_cycle_counters_update()
[all...]
/kernel/linux/linux-6.6/drivers/net/wireless/ath/
H A Dkey.c26 #define REG_WRITE(_ah, _reg, _val) (common->ops->write)(_ah, _val, _reg) macro
57 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0); in ath_hw_keyreset()
58 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0); in ath_hw_keyreset()
59 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0); in ath_hw_keyreset()
60 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0); in ath_hw_keyreset()
61 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0); in ath_hw_keyreset()
62 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR); in ath_hw_keyreset()
63 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0); in ath_hw_keyreset()
64 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0); in ath_hw_keyreset()
69 REG_WRITE(a in ath_hw_keyreset()
[all...]
H A Dhw.c24 #define REG_WRITE(_ah, _reg, _val) (common->ops->write)(_ah, _val, _reg) macro
123 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr)); in ath_hw_setbssidmask()
126 REG_WRITE(ah, AR_STA_ID1, id1); in ath_hw_setbssidmask()
128 REG_WRITE(ah, AR_BSSMSKL, get_unaligned_le32(common->bssidmask)); in ath_hw_setbssidmask()
129 REG_WRITE(ah, AR_BSSMSKU, get_unaligned_le16(common->bssidmask + 4)); in ath_hw_setbssidmask()
148 REG_WRITE(ah, AR_MIBC, AR_MIBC_FMC); in ath_hw_cycle_counters_update()
157 REG_WRITE(ah, AR_CCCNT, 0); in ath_hw_cycle_counters_update()
158 REG_WRITE(ah, AR_RFCNT, 0); in ath_hw_cycle_counters_update()
159 REG_WRITE(ah, AR_RCCNT, 0); in ath_hw_cycle_counters_update()
160 REG_WRITE(a in ath_hw_cycle_counters_update()
[all...]
/kernel/linux/linux-5.10/drivers/net/wireless/ath/ath9k/
H A Dar9003_wow.c44 REG_WRITE(ah, AR_CR, AR_CR_RXD); in ath9k_hw_set_powermode_wow_sleep()
62 REG_WRITE(ah, AR_RTC_KEEP_AWAKE, 0x2); in ath9k_hw_set_powermode_wow_sleep()
64 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_ON_INT); in ath9k_hw_set_powermode_wow_sleep()
92 REG_WRITE(ah, (AR_WOW_KA_DESC_WORD2 + i * 4), ctl[i]); in ath9k_wow_create_keep_alive_pattern()
111 REG_WRITE(ah, (AR_WOW_KA_DESC_WORD2 + (12 * 4)), 0); in ath9k_wow_create_keep_alive_pattern()
118 REG_WRITE(ah, (wow_ka_data_word0 + i*4), data_word[i]); in ath9k_wow_create_keep_alive_pattern()
139 REG_WRITE(ah, (AR_WOW_TB_PATTERN(pattern_count) + i), in ath9k_hw_wow_apply_pattern()
146 REG_WRITE(ah, (AR_WOW_TB_MASK(pattern_count) + i), mask_val); in ath9k_hw_wow_apply_pattern()
235 REG_WRITE(ah, AR_WOW_PATTERN, in ath9k_hw_wow_wakeup()
237 REG_WRITE(a in ath9k_hw_wow_wakeup()
[all...]
H A Dar9003_mci.c48 REG_WRITE(ah, address, bit_position); in ar9003_mci_wait_for_interrupt()
58 REG_WRITE(ah, AR_MCI_INTERRUPT_RAW, in ar9003_mci_wait_for_interrupt()
61 REG_WRITE(ah, AR_MCI_INTERRUPT_RAW, AR_MCI_INTERRUPT_RX_MSG); in ar9003_mci_wait_for_interrupt()
234 REG_WRITE(ah, AR_MCI_INTERRUPT_EN, 0); in ar9003_mci_prep_interface()
235 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_RAW, in ar9003_mci_prep_interface()
237 REG_WRITE(ah, AR_MCI_INTERRUPT_RAW, in ar9003_mci_prep_interface()
272 REG_WRITE(ah, AR_MCI_BT_PRI0, 0xFFFFFFFF); in ar9003_mci_prep_interface()
273 REG_WRITE(ah, AR_MCI_BT_PRI1, 0xFFFFFFFF); in ar9003_mci_prep_interface()
274 REG_WRITE(ah, AR_MCI_BT_PRI2, 0xFFFFFFFF); in ar9003_mci_prep_interface()
275 REG_WRITE(a in ar9003_mci_prep_interface()
[all...]
H A Dar5008_phy.c98 REG_WRITE(ah, INI_RA(array, r, 0), data[r]); in ar5008_write_bank6()
243 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL, in ar5008_hw_set_channel()
246 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL, in ar5008_hw_set_channel()
275 REG_WRITE(ah, AR_PHY(0x37), reg32); in ar5008_hw_set_channel()
319 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask); in ar5008_hw_cmn_spur_mitigate()
320 REG_WRITE(ah, chan_mask_reg[i], chan_mask); in ar5008_hw_cmn_spur_mitigate()
352 REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask); in ar5008_hw_cmn_spur_mitigate()
353 REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask); in ar5008_hw_cmn_spur_mitigate()
363 REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask); in ar5008_hw_cmn_spur_mitigate()
364 REG_WRITE(a in ar5008_hw_cmn_spur_mitigate()
[all...]
/kernel/linux/linux-6.6/drivers/net/wireless/ath/ath9k/
H A Dar9003_wow.c44 REG_WRITE(ah, AR_CR, AR_CR_RXD); in ath9k_hw_set_powermode_wow_sleep()
62 REG_WRITE(ah, AR_RTC_KEEP_AWAKE, 0x2); in ath9k_hw_set_powermode_wow_sleep()
64 REG_WRITE(ah, AR_RTC_FORCE_WAKE(ah), AR_RTC_FORCE_WAKE_ON_INT); in ath9k_hw_set_powermode_wow_sleep()
92 REG_WRITE(ah, (AR_WOW_KA_DESC_WORD2 + i * 4), ctl[i]); in ath9k_wow_create_keep_alive_pattern()
111 REG_WRITE(ah, (AR_WOW_KA_DESC_WORD2 + (12 * 4)), 0); in ath9k_wow_create_keep_alive_pattern()
118 REG_WRITE(ah, (wow_ka_data_word0 + i*4), data_word[i]); in ath9k_wow_create_keep_alive_pattern()
139 REG_WRITE(ah, (AR_WOW_TB_PATTERN(pattern_count) + i), in ath9k_hw_wow_apply_pattern()
146 REG_WRITE(ah, (AR_WOW_TB_MASK(pattern_count) + i), mask_val); in ath9k_hw_wow_apply_pattern()
235 REG_WRITE(ah, AR_WOW_PATTERN, in ath9k_hw_wow_wakeup()
237 REG_WRITE(a in ath9k_hw_wow_wakeup()
[all...]
H A Dar9003_mci.c48 REG_WRITE(ah, address, bit_position); in ar9003_mci_wait_for_interrupt()
58 REG_WRITE(ah, AR_MCI_INTERRUPT_RAW, in ar9003_mci_wait_for_interrupt()
61 REG_WRITE(ah, AR_MCI_INTERRUPT_RAW, AR_MCI_INTERRUPT_RX_MSG); in ar9003_mci_wait_for_interrupt()
234 REG_WRITE(ah, AR_MCI_INTERRUPT_EN, 0); in ar9003_mci_prep_interface()
235 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_RAW, in ar9003_mci_prep_interface()
237 REG_WRITE(ah, AR_MCI_INTERRUPT_RAW, in ar9003_mci_prep_interface()
272 REG_WRITE(ah, AR_MCI_BT_PRI0, 0xFFFFFFFF); in ar9003_mci_prep_interface()
273 REG_WRITE(ah, AR_MCI_BT_PRI1, 0xFFFFFFFF); in ar9003_mci_prep_interface()
274 REG_WRITE(ah, AR_MCI_BT_PRI2, 0xFFFFFFFF); in ar9003_mci_prep_interface()
275 REG_WRITE(a in ar9003_mci_prep_interface()
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/gma500/
H A Doaktrail_hdmi.c292 REG_WRITE(VGACNTRL, VGA_DISP_DISABLE); in oaktrail_crtc_hdmi_mode_set()
297 REG_WRITE(DPLL_CTRL, dpll | (DPLL_PWRDN | DPLL_RESET)); in oaktrail_crtc_hdmi_mode_set()
298 REG_WRITE(DPLL_DIV_CTRL, 0x00000000); in oaktrail_crtc_hdmi_mode_set()
299 REG_WRITE(DPLL_STATUS, 0x1); in oaktrail_crtc_hdmi_mode_set()
314 REG_WRITE(DPLL_CTRL, 0x00000008); in oaktrail_crtc_hdmi_mode_set()
315 REG_WRITE(DPLL_DIV_CTRL, ((clock.nf << 6) | clock.nr)); in oaktrail_crtc_hdmi_mode_set()
316 REG_WRITE(DPLL_ADJUST, ((clock.nf >> 14) - 1)); in oaktrail_crtc_hdmi_mode_set()
317 REG_WRITE(DPLL_CTRL, (dpll | (clock.np << DPLL_PDIV_SHIFT) | DPLL_ENSTAT | DPLL_DITHEN)); in oaktrail_crtc_hdmi_mode_set()
318 REG_WRITE(DPLL_UPDATE, 0x80000000); in oaktrail_crtc_hdmi_mode_set()
319 REG_WRITE(DPLL_CLK_ENABL in oaktrail_crtc_hdmi_mode_set()
[all...]
H A Dgma_display.c91 REG_WRITE(map->stride, fb->pitches[0]); in gma_pipe_set_base()
115 REG_WRITE(map->cntr, dspcntr); in gma_pipe_set_base()
124 REG_WRITE(map->base, offset + start); in gma_pipe_set_base()
127 REG_WRITE(map->base, offset); in gma_pipe_set_base()
129 REG_WRITE(map->surf, start); in gma_pipe_set_base()
164 REG_WRITE(palreg + 4 * i, in gma_crtc_load_lut()
225 REG_WRITE(map->dpll, temp); in gma_crtc_dpms()
229 REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE); in gma_crtc_dpms()
233 REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE); in gma_crtc_dpms()
242 REG_WRITE(ma in gma_crtc_dpms()
[all...]
H A Dcdv_intel_display.c140 REG_WRITE(SB_ADDR, reg); in cdv_sb_read()
141 REG_WRITE(SB_PCKT, in cdv_sb_read()
175 REG_WRITE(SB_ADDR, reg); in cdv_sb_write()
176 REG_WRITE(SB_DATA, val); in cdv_sb_write()
177 REG_WRITE(SB_PCKT, in cdv_sb_write()
202 REG_WRITE(DPIO_CFG, 0); in cdv_sb_reset()
204 REG_WRITE(DPIO_CFG, DPIO_MODE_SELECT_0 | DPIO_CMN_RESET_N); in cdv_sb_reset()
227 REG_WRITE(dpll_reg, DPLL_SYNCLOCK_ENABLE | DPLL_VGA_MODE_DIS); in cdv_dpll_set_clock_cdv()
475 REG_WRITE(FW_BLC_SELF, (REG_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN)); in cdv_disable_sr()
483 REG_WRITE(OV_OVAD in cdv_disable_sr()
[all...]
H A Dcdv_device.c35 REG_WRITE(vga_reg, VGA_DISP_DISABLE); in cdv_disable_vga()
125 REG_WRITE(BLC_PWM_CTL, (blc_pwm_ctl | in cdv_set_brightness()
297 REG_WRITE(DSPCLK_GATE_D, regs->cdv.saveDSPCLK_GATE_D); in cdv_restore_display_registers()
298 REG_WRITE(RAMCLK_GATE_D, regs->cdv.saveRAMCLK_GATE_D); in cdv_restore_display_registers()
301 REG_WRITE(DPIO_CFG, 0); in cdv_restore_display_registers()
302 REG_WRITE(DPIO_CFG, DPIO_MODE_SELECT_0 | DPIO_CMN_RESET_N); in cdv_restore_display_registers()
306 REG_WRITE(DPLL_A, temp | DPLL_SYNCLOCK_ENABLE); in cdv_restore_display_registers()
312 REG_WRITE(DPLL_B, temp | DPLL_SYNCLOCK_ENABLE); in cdv_restore_display_registers()
318 REG_WRITE(DSPFW1, regs->cdv.saveDSPFW[0]); in cdv_restore_display_registers()
319 REG_WRITE(DSPFW in cdv_restore_display_registers()
[all...]

Completed in 16 milliseconds

123456789