PACKET0 (reference) in projects: kernel

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Searched refs:PACKET0 (Results 1 - 25 of 81) sorted by relevance

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/kernel/linux/linux-5.10/drivers/gpu/drm/radeon/
H A D	uvd_v2_2.c	45 radeon_ring_write(ring, PACKET0(UVD_CONTEXT_ID, 0)); in uvd_v2_2_fence_emit() 47 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA0, 0)); in uvd_v2_2_fence_emit() 49 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA1, 0)); in uvd_v2_2_fence_emit() 51 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_CMD, 0)); in uvd_v2_2_fence_emit() 54 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA0, 0)); in uvd_v2_2_fence_emit() 56 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA1, 0)); in uvd_v2_2_fence_emit() 58 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_CMD, 0)); in uvd_v2_2_fence_emit() 79 radeon_ring_write(ring, PACKET0(UVD_SEMA_ADDR_LOW, 0)); in uvd_v2_2_semaphore_emit() 82 radeon_ring_write(ring, PACKET0(UVD_SEMA_ADDR_HIGH, 0)); in uvd_v2_2_semaphore_emit() 85 radeon_ring_write(ring, PACKET0(UVD_SEMA_CM in uvd_v2_2_semaphore_emit() [all...]
H A D	uvd_v1_0.c	87 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA0, 0)); in uvd_v1_0_fence_emit() 89 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA1, 0)); in uvd_v1_0_fence_emit() 91 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_CMD, 0)); in uvd_v1_0_fence_emit() 94 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA0, 0)); in uvd_v1_0_fence_emit() 96 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA1, 0)); in uvd_v1_0_fence_emit() 98 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_CMD, 0)); in uvd_v1_0_fence_emit() 186 tmp = PACKET0(UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL, 0); in uvd_v1_0_init() 190 tmp = PACKET0(UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL, 0); in uvd_v1_0_init() 194 tmp = PACKET0(UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL, 0); in uvd_v1_0_init() 199 radeon_ring_write(ring, PACKET0(UVD_SEMA_TIMEOUT_STATU in uvd_v1_0_init() [all...]
H A D	uvd_v3_1.c	`46 radeon_ring_write(ring, PACKET0(UVD_SEMA_ADDR_LOW, 0)); in uvd_v3_1_semaphore_emit() 49 radeon_ring_write(ring, PACKET0(UVD_SEMA_ADDR_HIGH, 0)); in uvd_v3_1_semaphore_emit() 52 radeon_ring_write(ring, PACKET0(UVD_SEMA_CMD, 0)); in uvd_v3_1_semaphore_emit()`
H A D	r300.c	222 radeon_ring_write(ring, PACKET0(R300_RE_SCISSORS_TL, 0)); in r300_fence_ring_emit() 224 radeon_ring_write(ring, PACKET0(R300_RE_SCISSORS_BR, 0)); in r300_fence_ring_emit() 227 radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); in r300_fence_ring_emit() 229 radeon_ring_write(ring, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0)); in r300_fence_ring_emit() 232 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0)); in r300_fence_ring_emit() 236 radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0)); in r300_fence_ring_emit() 239 radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0)); in r300_fence_ring_emit() 242 radeon_ring_write(ring, PACKET0(rdev->fence_drv[fence->ring].scratch_reg, 0)); in r300_fence_ring_emit() 244 radeon_ring_write(ring, PACKET0(RADEON_GEN_INT_STATUS, 0)); in r300_fence_ring_emit() 275 radeon_ring_write(ring, PACKET0(RADEON_ISYNC_CNT in r300_ring_start() [all...]
H A D	rv515.c	75 radeon_ring_write(ring, PACKET0(ISYNC_CNTL, 0)); in rv515_ring_start() 81 radeon_ring_write(ring, PACKET0(WAIT_UNTIL, 0)); in rv515_ring_start() 83 radeon_ring_write(ring, PACKET0(R300_DST_PIPE_CONFIG, 0)); in rv515_ring_start() 85 radeon_ring_write(ring, PACKET0(GB_SELECT, 0)); in rv515_ring_start() 87 radeon_ring_write(ring, PACKET0(GB_ENABLE, 0)); in rv515_ring_start() 89 radeon_ring_write(ring, PACKET0(R500_SU_REG_DEST, 0)); in rv515_ring_start() 91 radeon_ring_write(ring, PACKET0(VAP_INDEX_OFFSET, 0)); in rv515_ring_start() 93 radeon_ring_write(ring, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0)); in rv515_ring_start() 95 radeon_ring_write(ring, PACKET0(ZB_ZCACHE_CTLSTAT, 0)); in rv515_ring_start() 97 radeon_ring_write(ring, PACKET0(WAIT_UNTI in rv515_ring_start() [all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/radeon/
H A D	uvd_v2_2.c	45 radeon_ring_write(ring, PACKET0(UVD_CONTEXT_ID, 0)); in uvd_v2_2_fence_emit() 47 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA0, 0)); in uvd_v2_2_fence_emit() 49 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA1, 0)); in uvd_v2_2_fence_emit() 51 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_CMD, 0)); in uvd_v2_2_fence_emit() 54 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA0, 0)); in uvd_v2_2_fence_emit() 56 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA1, 0)); in uvd_v2_2_fence_emit() 58 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_CMD, 0)); in uvd_v2_2_fence_emit() 79 radeon_ring_write(ring, PACKET0(UVD_SEMA_ADDR_LOW, 0)); in uvd_v2_2_semaphore_emit() 82 radeon_ring_write(ring, PACKET0(UVD_SEMA_ADDR_HIGH, 0)); in uvd_v2_2_semaphore_emit() 85 radeon_ring_write(ring, PACKET0(UVD_SEMA_CM in uvd_v2_2_semaphore_emit() [all...]
H A D	uvd_v1_0.c	87 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA0, 0)); in uvd_v1_0_fence_emit() 89 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA1, 0)); in uvd_v1_0_fence_emit() 91 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_CMD, 0)); in uvd_v1_0_fence_emit() 94 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA0, 0)); in uvd_v1_0_fence_emit() 96 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA1, 0)); in uvd_v1_0_fence_emit() 98 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_CMD, 0)); in uvd_v1_0_fence_emit() 186 tmp = PACKET0(UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL, 0); in uvd_v1_0_init() 190 tmp = PACKET0(UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL, 0); in uvd_v1_0_init() 194 tmp = PACKET0(UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL, 0); in uvd_v1_0_init() 199 radeon_ring_write(ring, PACKET0(UVD_SEMA_TIMEOUT_STATU in uvd_v1_0_init() [all...]
H A D	uvd_v3_1.c	`46 radeon_ring_write(ring, PACKET0(UVD_SEMA_ADDR_LOW, 0)); in uvd_v3_1_semaphore_emit() 49 radeon_ring_write(ring, PACKET0(UVD_SEMA_ADDR_HIGH, 0)); in uvd_v3_1_semaphore_emit() 52 radeon_ring_write(ring, PACKET0(UVD_SEMA_CMD, 0)); in uvd_v3_1_semaphore_emit()`
H A D	r300.c	219 radeon_ring_write(ring, PACKET0(R300_RE_SCISSORS_TL, 0)); in r300_fence_ring_emit() 221 radeon_ring_write(ring, PACKET0(R300_RE_SCISSORS_BR, 0)); in r300_fence_ring_emit() 224 radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); in r300_fence_ring_emit() 226 radeon_ring_write(ring, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0)); in r300_fence_ring_emit() 229 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0)); in r300_fence_ring_emit() 233 radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0)); in r300_fence_ring_emit() 236 radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0)); in r300_fence_ring_emit() 239 radeon_ring_write(ring, PACKET0(rdev->fence_drv[fence->ring].scratch_reg, 0)); in r300_fence_ring_emit() 241 radeon_ring_write(ring, PACKET0(RADEON_GEN_INT_STATUS, 0)); in r300_fence_ring_emit() 272 radeon_ring_write(ring, PACKET0(RADEON_ISYNC_CNT in r300_ring_start() [all...]
H A D	rv515.c	59 radeon_ring_write(ring, PACKET0(ISYNC_CNTL, 0)); in rv515_ring_start() 65 radeon_ring_write(ring, PACKET0(WAIT_UNTIL, 0)); in rv515_ring_start() 67 radeon_ring_write(ring, PACKET0(R300_DST_PIPE_CONFIG, 0)); in rv515_ring_start() 69 radeon_ring_write(ring, PACKET0(GB_SELECT, 0)); in rv515_ring_start() 71 radeon_ring_write(ring, PACKET0(GB_ENABLE, 0)); in rv515_ring_start() 73 radeon_ring_write(ring, PACKET0(R500_SU_REG_DEST, 0)); in rv515_ring_start() 75 radeon_ring_write(ring, PACKET0(VAP_INDEX_OFFSET, 0)); in rv515_ring_start() 77 radeon_ring_write(ring, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0)); in rv515_ring_start() 79 radeon_ring_write(ring, PACKET0(ZB_ZCACHE_CTLSTAT, 0)); in rv515_ring_start() 81 radeon_ring_write(ring, PACKET0(WAIT_UNTI in rv515_ring_start() [all...]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/amdgpu/
H A D	uvd_v4_2.c	176 tmp = PACKET0(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL, 0); in uvd_v4_2_hw_init() 180 tmp = PACKET0(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL, 0); in uvd_v4_2_hw_init() 184 tmp = PACKET0(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL, 0); in uvd_v4_2_hw_init() 189 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_TIMEOUT_STATUS, 0)); in uvd_v4_2_hw_init() 192 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CNTL, 0)); in uvd_v4_2_hw_init() 449 amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0)); in uvd_v4_2_ring_emit_fence() 451 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); in uvd_v4_2_ring_emit_fence() 453 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0)); in uvd_v4_2_ring_emit_fence() 455 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0)); in uvd_v4_2_ring_emit_fence() 458 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA in uvd_v4_2_ring_emit_fence() [all...]
H A D	uvd_v3_1.c	92 amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_BASE, 0)); in uvd_v3_1_ring_emit_ib() 94 amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_SIZE, 0)); in uvd_v3_1_ring_emit_ib() 111 amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0)); in uvd_v3_1_ring_emit_fence() 113 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); in uvd_v3_1_ring_emit_fence() 115 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0)); in uvd_v3_1_ring_emit_fence() 117 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0)); in uvd_v3_1_ring_emit_fence() 120 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); in uvd_v3_1_ring_emit_fence() 122 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0)); in uvd_v3_1_ring_emit_fence() 124 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0)); in uvd_v3_1_ring_emit_fence() 147 amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_I in uvd_v3_1_ring_test_ring() [all...]
H A D	uvd_v5_0.c	173 tmp = PACKET0(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL, 0); in uvd_v5_0_hw_init() 177 tmp = PACKET0(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL, 0); in uvd_v5_0_hw_init() 181 tmp = PACKET0(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL, 0); in uvd_v5_0_hw_init() 186 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_TIMEOUT_STATUS, 0)); in uvd_v5_0_hw_init() 189 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CNTL, 0)); in uvd_v5_0_hw_init() 466 amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0)); in uvd_v5_0_ring_emit_fence() 468 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); in uvd_v5_0_ring_emit_fence() 470 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0)); in uvd_v5_0_ring_emit_fence() 472 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0)); in uvd_v5_0_ring_emit_fence() 475 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA in uvd_v5_0_ring_emit_fence() [all...]
H A D	uvd_v6_0.c	493 tmp = PACKET0(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL, 0); in uvd_v6_0_hw_init() 497 tmp = PACKET0(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL, 0); in uvd_v6_0_hw_init() 501 tmp = PACKET0(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL, 0); in uvd_v6_0_hw_init() 506 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_TIMEOUT_STATUS, 0)); in uvd_v6_0_hw_init() 509 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CNTL, 0)); in uvd_v6_0_hw_init() 904 amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0)); in uvd_v6_0_ring_emit_fence() 906 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); in uvd_v6_0_ring_emit_fence() 908 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0)); in uvd_v6_0_ring_emit_fence() 910 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0)); in uvd_v6_0_ring_emit_fence() 913 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA in uvd_v6_0_ring_emit_fence() [all...]
H A D	uvd_v7_0.c	556 tmp = PACKET0(SOC15_REG_OFFSET(UVD, j, in uvd_v7_0_hw_init() 561 tmp = PACKET0(SOC15_REG_OFFSET(UVD, j, in uvd_v7_0_hw_init() 566 tmp = PACKET0(SOC15_REG_OFFSET(UVD, j, in uvd_v7_0_hw_init() 572 amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, j, in uvd_v7_0_hw_init() 576 amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, j, in uvd_v7_0_hw_init() 1162 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_CONTEXT_ID), 0)); in uvd_v7_0_ring_emit_fence() 1165 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA0), 0)); in uvd_v7_0_ring_emit_fence() 1168 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA1), 0)); in uvd_v7_0_ring_emit_fence() 1171 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_CMD), 0)); in uvd_v7_0_ring_emit_fence() 1175 PACKET0(SOC15_REG_OFFSE in uvd_v7_0_ring_emit_fence() [all...]
H A D	vcn_v2_0.c	1381 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0)); in vcn_v2_0_dec_ring_insert_start() 1383 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0)); in vcn_v2_0_dec_ring_insert_start() 1398 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0)); in vcn_v2_0_dec_ring_insert_end() 1417 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.nop, 0)); in vcn_v2_0_dec_ring_insert_nop() 1436 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.context_id, 0)); in vcn_v2_0_dec_ring_emit_fence() 1439 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0)); in vcn_v2_0_dec_ring_emit_fence() 1442 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data1, 0)); in vcn_v2_0_dec_ring_emit_fence() 1445 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0)); in vcn_v2_0_dec_ring_emit_fence() 1448 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0)); in vcn_v2_0_dec_ring_emit_fence() 1451 amdgpu_ring_write(ring, PACKET0(ade in vcn_v2_0_dec_ring_emit_fence() [all...]
H A D	vcn_v1_0.c	1432 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0)); in vcn_v1_0_dec_ring_insert_start() 1435 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0)); in vcn_v1_0_dec_ring_insert_start() 1451 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0)); in vcn_v1_0_dec_ring_insert_end() 1471 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_CONTEXT_ID), 0)); in vcn_v1_0_dec_ring_emit_fence() 1474 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0)); in vcn_v1_0_dec_ring_emit_fence() 1477 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0)); in vcn_v1_0_dec_ring_emit_fence() 1480 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0)); in vcn_v1_0_dec_ring_emit_fence() 1484 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0)); in vcn_v1_0_dec_ring_emit_fence() 1487 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0)); in vcn_v1_0_dec_ring_emit_fence() 1490 PACKET0(SOC15_REG_OFFSE in vcn_v1_0_dec_ring_emit_fence() [all...]
H A D	amdgpu_vcn.c	`416 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.scratch9, 0)); in amdgpu_vcn_dec_ring_test_ring() 450 ib->ptr[0] = PACKET0(adev->vcn.internal.data0, 0); in amdgpu_vcn_dec_send_msg() 452 ib->ptr[2] = PACKET0(adev->vcn.internal.data1, 0); in amdgpu_vcn_dec_send_msg() 454 ib->ptr[4] = PACKET0(adev->vcn.internal.cmd, 0); in amdgpu_vcn_dec_send_msg() 457 ib->ptr[i] = PACKET0(adev->vcn.internal.nop, 0); in amdgpu_vcn_dec_send_msg()`
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/amdgpu/
H A D	uvd_v5_0.c	173 tmp = PACKET0(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL, 0); in uvd_v5_0_hw_init() 177 tmp = PACKET0(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL, 0); in uvd_v5_0_hw_init() 181 tmp = PACKET0(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL, 0); in uvd_v5_0_hw_init() 186 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_TIMEOUT_STATUS, 0)); in uvd_v5_0_hw_init() 189 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CNTL, 0)); in uvd_v5_0_hw_init() 493 amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0)); in uvd_v5_0_ring_emit_fence() 495 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); in uvd_v5_0_ring_emit_fence() 497 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0)); in uvd_v5_0_ring_emit_fence() 499 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0)); in uvd_v5_0_ring_emit_fence() 502 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA in uvd_v5_0_ring_emit_fence() [all...]
H A D	uvd_v6_0.c	485 tmp = PACKET0(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL, 0); in uvd_v6_0_hw_init() 489 tmp = PACKET0(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL, 0); in uvd_v6_0_hw_init() 493 tmp = PACKET0(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL, 0); in uvd_v6_0_hw_init() 498 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_TIMEOUT_STATUS, 0)); in uvd_v6_0_hw_init() 501 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CNTL, 0)); in uvd_v6_0_hw_init() 924 amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0)); in uvd_v6_0_ring_emit_fence() 926 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); in uvd_v6_0_ring_emit_fence() 928 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0)); in uvd_v6_0_ring_emit_fence() 930 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0)); in uvd_v6_0_ring_emit_fence() 933 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA in uvd_v6_0_ring_emit_fence() [all...]
H A D	uvd_v4_2.c	176 tmp = PACKET0(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL, 0); in uvd_v4_2_hw_init() 180 tmp = PACKET0(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL, 0); in uvd_v4_2_hw_init() 184 tmp = PACKET0(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL, 0); in uvd_v4_2_hw_init() 189 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_TIMEOUT_STATUS, 0)); in uvd_v4_2_hw_init() 192 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CNTL, 0)); in uvd_v4_2_hw_init() 477 amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0)); in uvd_v4_2_ring_emit_fence() 479 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); in uvd_v4_2_ring_emit_fence() 481 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0)); in uvd_v4_2_ring_emit_fence() 483 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0)); in uvd_v4_2_ring_emit_fence() 486 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA in uvd_v4_2_ring_emit_fence() [all...]
H A D	uvd_v3_1.c	94 amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_BASE, 0)); in uvd_v3_1_ring_emit_ib() 96 amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_SIZE, 0)); in uvd_v3_1_ring_emit_ib() 115 amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0)); in uvd_v3_1_ring_emit_fence() 117 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); in uvd_v3_1_ring_emit_fence() 119 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0)); in uvd_v3_1_ring_emit_fence() 121 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0)); in uvd_v3_1_ring_emit_fence() 124 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); in uvd_v3_1_ring_emit_fence() 126 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0)); in uvd_v3_1_ring_emit_fence() 128 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0)); in uvd_v3_1_ring_emit_fence() 151 amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_I in uvd_v3_1_ring_test_ring() [all...]
H A D	vcn_v1_0.c	1433 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0)); in vcn_v1_0_dec_ring_insert_start() 1436 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0)); in vcn_v1_0_dec_ring_insert_start() 1452 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0)); in vcn_v1_0_dec_ring_insert_end() 1474 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_CONTEXT_ID), 0)); in vcn_v1_0_dec_ring_emit_fence() 1477 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0)); in vcn_v1_0_dec_ring_emit_fence() 1480 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0)); in vcn_v1_0_dec_ring_emit_fence() 1483 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0)); in vcn_v1_0_dec_ring_emit_fence() 1487 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0)); in vcn_v1_0_dec_ring_emit_fence() 1490 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0)); in vcn_v1_0_dec_ring_emit_fence() 1493 PACKET0(SOC15_REG_OFFSE in vcn_v1_0_dec_ring_emit_fence() [all...]
H A D	uvd_v7_0.c	551 tmp = PACKET0(SOC15_REG_OFFSET(UVD, j, in uvd_v7_0_hw_init() 556 tmp = PACKET0(SOC15_REG_OFFSET(UVD, j, in uvd_v7_0_hw_init() 561 tmp = PACKET0(SOC15_REG_OFFSET(UVD, j, in uvd_v7_0_hw_init() 567 amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, j, in uvd_v7_0_hw_init() 571 amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, j, in uvd_v7_0_hw_init() 1185 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_CONTEXT_ID), 0)); in uvd_v7_0_ring_emit_fence() 1188 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA0), 0)); in uvd_v7_0_ring_emit_fence() 1191 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA1), 0)); in uvd_v7_0_ring_emit_fence() 1194 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_CMD), 0)); in uvd_v7_0_ring_emit_fence() 1198 PACKET0(SOC15_REG_OFFSE in uvd_v7_0_ring_emit_fence() [all...]
H A D	vcn_v2_0.c	1382 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0)); in vcn_v2_0_dec_ring_insert_start() 1384 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0)); in vcn_v2_0_dec_ring_insert_start() 1399 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0)); in vcn_v2_0_dec_ring_insert_end() 1419 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.nop, 0)); in vcn_v2_0_dec_ring_insert_nop() 1440 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.context_id, 0)); in vcn_v2_0_dec_ring_emit_fence() 1443 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0)); in vcn_v2_0_dec_ring_emit_fence() 1446 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data1, 0)); in vcn_v2_0_dec_ring_emit_fence() 1449 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0)); in vcn_v2_0_dec_ring_emit_fence() 1452 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0)); in vcn_v2_0_dec_ring_emit_fence() 1455 amdgpu_ring_write(ring, PACKET0(ade in vcn_v2_0_dec_ring_emit_fence() [all...]

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