Home
last modified time | relevance | path

Searched refs:GENMASK (Results 1 - 25 of 3807) sorted by relevance

12345678910>>...153

/kernel/linux/linux-5.10/drivers/net/ipa/
H A Dipa_reg.h71 #define ENABLE_FMASK GENMASK(0, 0)
72 #define GSI_SNOC_BYPASS_DIS_FMASK GENMASK(1, 1)
73 #define GEN_QMB_0_SNOC_BYPASS_DIS_FMASK GENMASK(2, 2)
74 #define GEN_QMB_1_SNOC_BYPASS_DIS_FMASK GENMASK(3, 3)
75 #define IPA_DCMP_FAST_CLK_EN_FMASK GENMASK(4, 4)
76 #define IPA_QMB_SELECT_CONS_EN_FMASK GENMASK(5, 5)
77 #define IPA_QMB_SELECT_PROD_EN_FMASK GENMASK(6, 6)
78 #define GSI_MULTI_INORDER_RD_DIS_FMASK GENMASK(7, 7)
79 #define GSI_MULTI_INORDER_WR_DIS_FMASK GENMASK(8, 8)
80 #define GEN_QMB_0_MULTI_INORDER_RD_DIS_FMASK GENMASK(
[all...]
/kernel/linux/linux-6.6/include/soc/mscc/
H A Docelot_ana.h15 #define ANA_ANAGEFIL_PID_VAL(x) (((x) << 14) & GENMASK(18, 14))
16 #define ANA_ANAGEFIL_PID_VAL_M GENMASK(18, 14)
17 #define ANA_ANAGEFIL_PID_VAL_X(x) (((x) & GENMASK(18, 14)) >> 14)
19 #define ANA_ANAGEFIL_VID_VAL(x) ((x) & GENMASK(12, 0))
20 #define ANA_ANAGEFIL_VID_VAL_M GENMASK(12, 0)
24 #define ANA_STORMLIMIT_CFG_STORM_RATE(x) (((x) << 3) & GENMASK(6, 3))
25 #define ANA_STORMLIMIT_CFG_STORM_RATE_M GENMASK(6, 3)
26 #define ANA_STORMLIMIT_CFG_STORM_RATE_X(x) (((x) & GENMASK(6, 3)) >> 3)
28 #define ANA_STORMLIMIT_CFG_STORM_MODE(x) ((x) & GENMASK(1, 0))
29 #define ANA_STORMLIMIT_CFG_STORM_MODE_M GENMASK(
[all...]
H A Docelot_hsio.h90 #define HSIO_PLL5G_CFG0_SELBGV820(x) (((x) << 23) & GENMASK(26, 23))
91 #define HSIO_PLL5G_CFG0_SELBGV820_M GENMASK(26, 23)
92 #define HSIO_PLL5G_CFG0_SELBGV820_X(x) (((x) & GENMASK(26, 23)) >> 23)
93 #define HSIO_PLL5G_CFG0_LOOP_BW_RES(x) (((x) << 18) & GENMASK(22, 18))
94 #define HSIO_PLL5G_CFG0_LOOP_BW_RES_M GENMASK(22, 18)
95 #define HSIO_PLL5G_CFG0_LOOP_BW_RES_X(x) (((x) & GENMASK(22, 18)) >> 18)
96 #define HSIO_PLL5G_CFG0_SELCPI(x) (((x) << 16) & GENMASK(17, 16))
97 #define HSIO_PLL5G_CFG0_SELCPI_M GENMASK(17, 16)
98 #define HSIO_PLL5G_CFG0_SELCPI_X(x) (((x) & GENMASK(17, 16)) >> 16)
103 #define HSIO_PLL5G_CFG0_CPU_CLK_DIV(x) (((x) << 6) & GENMASK(1
[all...]
H A Docelot_qsys.h25 #define QSYS_EEE_THRES_EEE_HIGH_BYTES(x) (((x) << 8) & GENMASK(15, 8))
26 #define QSYS_EEE_THRES_EEE_HIGH_BYTES_M GENMASK(15, 8)
27 #define QSYS_EEE_THRES_EEE_HIGH_BYTES_X(x) (((x) & GENMASK(15, 8)) >> 8)
28 #define QSYS_EEE_THRES_EEE_HIGH_FRAMES(x) ((x) & GENMASK(7, 0))
29 #define QSYS_EEE_THRES_EEE_HIGH_FRAMES_M GENMASK(7, 0)
33 #define QSYS_EXT_CPU_CFG_EXT_CPU_PORT(x) (((x) << 8) & GENMASK(12, 8))
34 #define QSYS_EXT_CPU_CFG_EXT_CPU_PORT_M GENMASK(12, 8)
35 #define QSYS_EXT_CPU_CFG_EXT_CPU_PORT_X(x) (((x) & GENMASK(12, 8)) >> 8)
36 #define QSYS_EXT_CPU_CFG_EXT_CPUQ_MSK(x) ((x) & GENMASK(7, 0))
37 #define QSYS_EXT_CPU_CFG_EXT_CPUQ_MSK_M GENMASK(
[all...]
H A Docelot_sys.h20 #define SYS_FRM_AGING_MAX_AGE(x) ((x) & GENMASK(19, 0))
21 #define SYS_FRM_AGING_MAX_AGE_M GENMASK(19, 0)
23 #define SYS_STAT_CFG_STAT_CLEAR_SHOT(x) (((x) << 10) & GENMASK(16, 10))
24 #define SYS_STAT_CFG_STAT_CLEAR_SHOT_M GENMASK(16, 10)
25 #define SYS_STAT_CFG_STAT_CLEAR_SHOT_X(x) (((x) & GENMASK(16, 10)) >> 10)
26 #define SYS_STAT_CFG_STAT_VIEW(x) ((x) & GENMASK(9, 0))
27 #define SYS_STAT_CFG_STAT_VIEW_M GENMASK(9, 0)
40 #define SYS_TIMESTAMP_OFFSET_ETH_TYPE_CFG(x) (((x) << 6) & GENMASK(21, 6))
41 #define SYS_TIMESTAMP_OFFSET_ETH_TYPE_CFG_M GENMASK(21, 6)
42 #define SYS_TIMESTAMP_OFFSET_ETH_TYPE_CFG_X(x) (((x) & GENMASK(2
[all...]
H A Docelot_dev.h17 #define DEV_CLOCK_CFG_LINK_SPEED(x) ((x) & GENMASK(1, 0))
18 #define DEV_CLOCK_CFG_LINK_SPEED_M GENMASK(1, 0)
27 #define DEV_EEE_CFG_EEE_TIMER_AGE(x) (((x) << 15) & GENMASK(21, 15))
28 #define DEV_EEE_CFG_EEE_TIMER_AGE_M GENMASK(21, 15)
29 #define DEV_EEE_CFG_EEE_TIMER_AGE_X(x) (((x) & GENMASK(21, 15)) >> 15)
30 #define DEV_EEE_CFG_EEE_TIMER_WAKEUP(x) (((x) << 8) & GENMASK(14, 8))
31 #define DEV_EEE_CFG_EEE_TIMER_WAKEUP_M GENMASK(14, 8)
32 #define DEV_EEE_CFG_EEE_TIMER_WAKEUP_X(x) (((x) & GENMASK(14, 8)) >> 8)
33 #define DEV_EEE_CFG_EEE_TIMER_HOLDOFF(x) (((x) << 1) & GENMASK(7, 1))
34 #define DEV_EEE_CFG_EEE_TIMER_HOLDOFF_M GENMASK(
[all...]
/kernel/linux/linux-5.10/include/soc/mscc/
H A Docelot_ana.h15 #define ANA_ANAGEFIL_PID_VAL(x) (((x) << 14) & GENMASK(18, 14))
16 #define ANA_ANAGEFIL_PID_VAL_M GENMASK(18, 14)
17 #define ANA_ANAGEFIL_PID_VAL_X(x) (((x) & GENMASK(18, 14)) >> 14)
19 #define ANA_ANAGEFIL_VID_VAL(x) ((x) & GENMASK(12, 0))
20 #define ANA_ANAGEFIL_VID_VAL_M GENMASK(12, 0)
24 #define ANA_STORMLIMIT_CFG_STORM_RATE(x) (((x) << 3) & GENMASK(6, 3))
25 #define ANA_STORMLIMIT_CFG_STORM_RATE_M GENMASK(6, 3)
26 #define ANA_STORMLIMIT_CFG_STORM_RATE_X(x) (((x) & GENMASK(6, 3)) >> 3)
28 #define ANA_STORMLIMIT_CFG_STORM_MODE(x) ((x) & GENMASK(1, 0))
29 #define ANA_STORMLIMIT_CFG_STORM_MODE_M GENMASK(
[all...]
H A Docelot_hsio.h90 #define HSIO_PLL5G_CFG0_SELBGV820(x) (((x) << 23) & GENMASK(26, 23))
91 #define HSIO_PLL5G_CFG0_SELBGV820_M GENMASK(26, 23)
92 #define HSIO_PLL5G_CFG0_SELBGV820_X(x) (((x) & GENMASK(26, 23)) >> 23)
93 #define HSIO_PLL5G_CFG0_LOOP_BW_RES(x) (((x) << 18) & GENMASK(22, 18))
94 #define HSIO_PLL5G_CFG0_LOOP_BW_RES_M GENMASK(22, 18)
95 #define HSIO_PLL5G_CFG0_LOOP_BW_RES_X(x) (((x) & GENMASK(22, 18)) >> 18)
96 #define HSIO_PLL5G_CFG0_SELCPI(x) (((x) << 16) & GENMASK(17, 16))
97 #define HSIO_PLL5G_CFG0_SELCPI_M GENMASK(17, 16)
98 #define HSIO_PLL5G_CFG0_SELCPI_X(x) (((x) & GENMASK(17, 16)) >> 16)
103 #define HSIO_PLL5G_CFG0_CPU_CLK_DIV(x) (((x) << 6) & GENMASK(1
[all...]
H A Docelot_qsys.h25 #define QSYS_EEE_THRES_EEE_HIGH_BYTES(x) (((x) << 8) & GENMASK(15, 8))
26 #define QSYS_EEE_THRES_EEE_HIGH_BYTES_M GENMASK(15, 8)
27 #define QSYS_EEE_THRES_EEE_HIGH_BYTES_X(x) (((x) & GENMASK(15, 8)) >> 8)
28 #define QSYS_EEE_THRES_EEE_HIGH_FRAMES(x) ((x) & GENMASK(7, 0))
29 #define QSYS_EEE_THRES_EEE_HIGH_FRAMES_M GENMASK(7, 0)
33 #define QSYS_EXT_CPU_CFG_EXT_CPU_PORT(x) (((x) << 8) & GENMASK(12, 8))
34 #define QSYS_EXT_CPU_CFG_EXT_CPU_PORT_M GENMASK(12, 8)
35 #define QSYS_EXT_CPU_CFG_EXT_CPU_PORT_X(x) (((x) & GENMASK(12, 8)) >> 8)
36 #define QSYS_EXT_CPU_CFG_EXT_CPUQ_MSK(x) ((x) & GENMASK(7, 0))
37 #define QSYS_EXT_CPU_CFG_EXT_CPUQ_MSK_M GENMASK(
[all...]
H A Docelot_sys.h20 #define SYS_FRM_AGING_MAX_AGE(x) ((x) & GENMASK(19, 0))
21 #define SYS_FRM_AGING_MAX_AGE_M GENMASK(19, 0)
23 #define SYS_STAT_CFG_STAT_CLEAR_SHOT(x) (((x) << 10) & GENMASK(16, 10))
24 #define SYS_STAT_CFG_STAT_CLEAR_SHOT_M GENMASK(16, 10)
25 #define SYS_STAT_CFG_STAT_CLEAR_SHOT_X(x) (((x) & GENMASK(16, 10)) >> 10)
26 #define SYS_STAT_CFG_STAT_VIEW(x) ((x) & GENMASK(9, 0))
27 #define SYS_STAT_CFG_STAT_VIEW_M GENMASK(9, 0)
40 #define SYS_TIMESTAMP_OFFSET_ETH_TYPE_CFG(x) (((x) << 6) & GENMASK(21, 6))
41 #define SYS_TIMESTAMP_OFFSET_ETH_TYPE_CFG_M GENMASK(21, 6)
42 #define SYS_TIMESTAMP_OFFSET_ETH_TYPE_CFG_X(x) (((x) & GENMASK(2
[all...]
H A Docelot_dev.h17 #define DEV_CLOCK_CFG_LINK_SPEED(x) ((x) & GENMASK(1, 0))
18 #define DEV_CLOCK_CFG_LINK_SPEED_M GENMASK(1, 0)
27 #define DEV_EEE_CFG_EEE_TIMER_AGE(x) (((x) << 15) & GENMASK(21, 15))
28 #define DEV_EEE_CFG_EEE_TIMER_AGE_M GENMASK(21, 15)
29 #define DEV_EEE_CFG_EEE_TIMER_AGE_X(x) (((x) & GENMASK(21, 15)) >> 15)
30 #define DEV_EEE_CFG_EEE_TIMER_WAKEUP(x) (((x) << 8) & GENMASK(14, 8))
31 #define DEV_EEE_CFG_EEE_TIMER_WAKEUP_M GENMASK(14, 8)
32 #define DEV_EEE_CFG_EEE_TIMER_WAKEUP_X(x) (((x) & GENMASK(14, 8)) >> 8)
33 #define DEV_EEE_CFG_EEE_TIMER_HOLDOFF(x) (((x) << 1) & GENMASK(7, 1))
34 #define DEV_EEE_CFG_EEE_TIMER_HOLDOFF_M GENMASK(
[all...]
/kernel/linux/linux-6.6/drivers/net/wireless/mediatek/mt76/
H A Dmt76_connac2_mac.h35 #define MT_TX_FREE_MSDU_CNT GENMASK(9, 0)
36 #define MT_TX_FREE_WLAN_ID GENMASK(23, 14)
37 #define MT_TX_FREE_COUNT GENMASK(12, 0)
39 #define MT_TX_FREE_STATUS GENMASK(14, 13)
40 #define MT_TX_FREE_MSDU_ID GENMASK(30, 16)
43 #define MT_TX_FREE_RATE GENMASK(13, 0)
45 #define MT_TXD0_Q_IDX GENMASK(31, 25)
46 #define MT_TXD0_PKT_FMT GENMASK(24, 23)
47 #define MT_TXD0_ETH_TYPE_OFFSET GENMASK(22, 16)
48 #define MT_TXD0_TX_BYTES GENMASK(1
[all...]
H A Dmt76_connac3_mac.h24 #define MT_RXD0_LENGTH GENMASK(15, 0)
25 #define MT_RXD0_PKT_FLAG GENMASK(19, 16)
26 #define MT_RXD0_PKT_TYPE GENMASK(31, 27)
30 #define MT_RXD0_NORMAL_ETH_TYPE_OFS GENMASK(22, 16)
34 #define MT_RXD0_SW_PKT_TYPE_MASK GENMASK(31, 16)
39 #define MT_RXD1_NORMAL_WLAN_IDX GENMASK(11, 0)
45 #define MT_RXD1_NORMAL_KEY_ID GENMASK(22, 21)
50 #define MT_RXD1_NORMAL_BAND_IDX GENMASK(28, 27)
56 #define MT_RXD2_NORMAL_BSSID GENMASK(5, 0)
57 #define MT_RXD2_NORMAL_MAC_HDR_LEN GENMASK(1
[all...]
/kernel/linux/linux-5.10/drivers/net/wireless/mediatek/mt76/mt7603/
H A Dmac.h6 #define MT_RXD0_LENGTH GENMASK(15, 0)
7 #define MT_RXD0_PKT_TYPE GENMASK(31, 29)
9 #define MT_RXD0_NORMAL_ETH_TYPE_OFS GENMASK(22, 16)
27 #define MT_RXD1_NORMAL_BSSID GENMASK(31, 26)
28 #define MT_RXD1_NORMAL_PAYLOAD_FORMAT GENMASK(25, 24)
31 #define MT_RXD1_NORMAL_MAC_HDR_LEN GENMASK(21, 16)
32 #define MT_RXD1_NORMAL_CH_FREQ GENMASK(15, 8)
33 #define MT_RXD1_NORMAL_KEY_ID GENMASK(7, 6)
57 #define MT_RXD2_NORMAL_SEC_MODE GENMASK(15, 12)
58 #define MT_RXD2_NORMAL_TID GENMASK(1
[all...]
H A Dregs.h14 #define MT_MCU_PCIE_REMAP_1_OFFSET GENMASK(17, 0)
15 #define MT_MCU_PCIE_REMAP_1_BASE GENMASK(31, 18)
18 #define MT_MCU_PCIE_REMAP_2_OFFSET GENMASK(18, 0)
19 #define MT_MCU_PCIE_REMAP_2_BASE GENMASK(31, 19)
29 #define MT_INT_RX_DONE_ALL GENMASK(1, 0)
30 #define MT_INT_TX_DONE_ALL GENMASK(19, 4)
44 #define MT_WPDMA_GLO_CFG_DMA_BURST_SIZE GENMASK(5, 4)
47 #define MT_WPDMA_GLO_CFG_HDR_SEG_LEN GENMASK(15, 8)
56 #define MT_WPDMA_DEBUG_VALUE GENMASK(17, 0)
58 #define MT_WPDMA_DEBUG_IDX GENMASK(3
[all...]
/kernel/linux/linux-6.6/drivers/net/wireless/mediatek/mt76/mt7603/
H A Dmac.h6 #define MT_RXD0_LENGTH GENMASK(15, 0)
7 #define MT_RXD0_PKT_TYPE GENMASK(31, 29)
9 #define MT_RXD0_NORMAL_ETH_TYPE_OFS GENMASK(22, 16)
27 #define MT_RXD1_NORMAL_BSSID GENMASK(31, 26)
28 #define MT_RXD1_NORMAL_PAYLOAD_FORMAT GENMASK(25, 24)
31 #define MT_RXD1_NORMAL_MAC_HDR_LEN GENMASK(21, 16)
32 #define MT_RXD1_NORMAL_CH_FREQ GENMASK(15, 8)
33 #define MT_RXD1_NORMAL_KEY_ID GENMASK(7, 6)
57 #define MT_RXD2_NORMAL_SEC_MODE GENMASK(15, 12)
58 #define MT_RXD2_NORMAL_TID GENMASK(1
[all...]
H A Dregs.h14 #define MT_MCU_PCIE_REMAP_1_OFFSET GENMASK(17, 0)
15 #define MT_MCU_PCIE_REMAP_1_BASE GENMASK(31, 18)
18 #define MT_MCU_PCIE_REMAP_2_OFFSET GENMASK(18, 0)
19 #define MT_MCU_PCIE_REMAP_2_BASE GENMASK(31, 19)
29 #define MT_INT_RX_DONE_ALL GENMASK(1, 0)
30 #define MT_INT_TX_DONE_ALL GENMASK(19, 4)
44 #define MT_WPDMA_GLO_CFG_DMA_BURST_SIZE GENMASK(5, 4)
47 #define MT_WPDMA_GLO_CFG_HDR_SEG_LEN GENMASK(15, 8)
56 #define MT_WPDMA_DEBUG_VALUE GENMASK(17, 0)
58 #define MT_WPDMA_DEBUG_IDX GENMASK(3
[all...]
/kernel/linux/linux-6.6/drivers/net/wireless/mediatek/mt76/mt7615/
H A Dmac.h10 #define MT_RXD0_LENGTH GENMASK(15, 0)
11 #define MT_RXD0_PKT_FLAG GENMASK(19, 16)
12 #define MT_RXD0_PKT_TYPE GENMASK(31, 29)
14 #define MT_RXD0_NORMAL_ETH_TYPE_OFS GENMASK(22, 16)
22 #define MT_RXD1_NORMAL_BSSID GENMASK(31, 26)
23 #define MT_RXD1_NORMAL_PAYLOAD_FORMAT GENMASK(25, 24)
24 #define MT_RXD1_FIRST_AMSDU_FRAME GENMASK(1, 0)
29 #define MT_RXD1_NORMAL_MAC_HDR_LEN GENMASK(21, 16)
30 #define MT_RXD1_NORMAL_CH_FREQ GENMASK(15, 8)
31 #define MT_RXD1_NORMAL_KEY_ID GENMASK(
[all...]
/kernel/linux/linux-5.10/drivers/infiniband/hw/hns/
H A Dhns_roce_hw_v2.h287 #define V2_CQC_BYTE_4_CQ_ST_M GENMASK(1, 0)
298 #define V2_CQC_BYTE_4_ARM_ST_M GENMASK(7, 6)
301 #define V2_CQC_BYTE_4_SHIFT_M GENMASK(12, 8)
304 #define V2_CQC_BYTE_4_CMD_SN_M GENMASK(14, 13)
307 #define V2_CQC_BYTE_4_CEQN_M GENMASK(23, 15)
310 #define V2_CQC_BYTE_4_PAGE_OFFSET_M GENMASK(31, 24)
313 #define V2_CQC_BYTE_8_CQN_M GENMASK(23, 0)
316 #define V2_CQC_BYTE_8_CQE_SIZE_M GENMASK(28, 27)
319 #define V2_CQC_BYTE_16_CQE_CUR_BLK_ADDR_M GENMASK(19, 0)
322 #define V2_CQC_BYTE_16_CQE_HOP_NUM_M GENMASK(3
[all...]
/kernel/linux/linux-5.10/drivers/net/wireless/mediatek/mt76/mt7615/
H A Dmac.h10 #define MT_RXD0_LENGTH GENMASK(15, 0)
11 #define MT_RXD0_PKT_FLAG GENMASK(19, 16)
12 #define MT_RXD0_PKT_TYPE GENMASK(31, 29)
14 #define MT_RXD0_NORMAL_ETH_TYPE_OFS GENMASK(22, 16)
34 #define MT_RXD1_NORMAL_BSSID GENMASK(31, 26)
35 #define MT_RXD1_NORMAL_PAYLOAD_FORMAT GENMASK(25, 24)
38 #define MT_RXD1_NORMAL_MAC_HDR_LEN GENMASK(21, 16)
39 #define MT_RXD1_NORMAL_CH_FREQ GENMASK(15, 8)
40 #define MT_RXD1_NORMAL_KEY_ID GENMASK(7, 6)
44 #define MT_RXD1_NORMAL_ADDR_TYPE GENMASK(
[all...]
/kernel/linux/linux-6.6/drivers/net/wireless/realtek/rtw89/
H A Dtxrx.h10 #define DATA_RATE_MODE_CTRL_MASK GENMASK(8, 7)
11 #define DATA_RATE_MODE_CTRL_MASK_V1 GENMASK(10, 8)
12 #define DATA_RATE_NOT_HT_IDX_MASK GENMASK(3, 0)
14 #define DATA_RATE_HT_IDX_MASK GENMASK(4, 0)
15 #define DATA_RATE_HT_IDX_MASK_V1 GENMASK(4, 0)
17 #define DATA_RATE_VHT_HE_NSS_MASK GENMASK(6, 4)
18 #define DATA_RATE_VHT_HE_IDX_MASK GENMASK(3, 0)
19 #define DATA_RATE_NSS_MASK_V1 GENMASK(7, 5)
20 #define DATA_RATE_MCS_MASK_V1 GENMASK(4, 0)
63 #define RTW89_TXWD_BODY0_WP_OFFSET GENMASK(3
[all...]
H A Dreg.h12 #define B_AX_PWC_EV2EF_MASK GENMASK(15, 14)
54 #define B_AX_EF_PGPD_MASK GENMASK(30, 28)
56 #define B_AX_EF_VDDQST_MASK GENMASK(26, 24)
57 #define B_AX_EF_PGTS_MASK GENMASK(23, 20)
60 #define B_AX_EF_CELL_SEL_MASK GENMASK(9, 8)
63 #define B_AX_EF_MODE_SEL_MASK GENMASK(31, 30)
66 #define B_AX_EF_ADDR_MASK GENMASK(26, 16)
67 #define B_AX_EF_DATA_MASK GENMASK(15, 0)
72 #define B_AX_EF_TEST_SEL_MASK GENMASK(18, 16)
92 #define B_AX_BTMODE_MASK GENMASK(
[all...]
H A Dfw.h25 #define RTW89_C2HREG_HDR_FUNC_MASK GENMASK(6, 0)
27 #define RTW89_C2HREG_HDR_LEN_MASK GENMASK(11, 8)
28 #define RTW89_C2HREG_HDR_SEQ_MASK GENMASK(15, 12)
37 #define RTW89_C2HREG_PHYCAP_W0_FUNC GENMASK(6, 0)
39 #define RTW89_C2HREG_PHYCAP_W0_LEN GENMASK(11, 8)
40 #define RTW89_C2HREG_PHYCAP_W0_SEQ GENMASK(15, 12)
41 #define RTW89_C2HREG_PHYCAP_W0_RX_NSS GENMASK(23, 16)
42 #define RTW89_C2HREG_PHYCAP_W0_BW GENMASK(31, 24)
43 #define RTW89_C2HREG_PHYCAP_W1_TX_NSS GENMASK(7, 0)
44 #define RTW89_C2HREG_PHYCAP_W1_PROT GENMASK(1
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/mediatek/
H A Dmtk_dp_reg.h17 #define RG_XTP_GLB_BIAS_INTR_CTRL GENMASK(20, 16)
19 #define RG_CKM_PT0_CKTX_IMPSEL GENMASK(23, 20)
38 #define RG_XTP_LN0_TX_IMPSEL_PMOS GENMASK(15, 12)
39 #define RG_XTP_LN0_TX_IMPSEL_NMOS GENMASK(19, 16)
41 #define RG_XTP_LN1_TX_IMPSEL_PMOS GENMASK(15, 12)
42 #define RG_XTP_LN1_TX_IMPSEL_NMOS GENMASK(19, 16)
44 #define RG_XTP_LN2_TX_IMPSEL_PMOS GENMASK(15, 12)
45 #define RG_XTP_LN2_TX_IMPSEL_NMOS GENMASK(19, 16)
47 #define RG_XTP_LN3_TX_IMPSEL_PMOS GENMASK(15, 12)
48 #define RG_XTP_LN3_TX_IMPSEL_NMOS GENMASK(1
[all...]
/kernel/linux/linux-5.10/drivers/net/wireless/mediatek/mt76/mt7915/
H A Dmac.h10 #define MT_RXD0_LENGTH GENMASK(15, 0)
11 #define MT_RXD0_PKT_TYPE GENMASK(31, 27)
13 #define MT_RXD0_NORMAL_ETH_TYPE_OFS GENMASK(22, 16)
29 #define MT_RXD1_NORMAL_WLAN_IDX GENMASK(9, 0)
35 #define MT_RXD1_NORMAL_SEC_MODE GENMASK(20, 16)
36 #define MT_RXD1_NORMAL_KEY_ID GENMASK(22, 21)
48 #define MT_RXD2_NORMAL_BSSID GENMASK(5, 0)
51 #define MT_RXD2_NORMAL_MAC_HDR_LEN GENMASK(12, 8)
53 #define MT_RXD2_NORMAL_HDR_OFFSET GENMASK(15, 14)
54 #define MT_RXD2_NORMAL_TID GENMASK(1
[all...]

Completed in 48 milliseconds

12345678910>>...153