Lines Matching refs:GENMASK
12 #define B_AX_PWC_EV2EF_MASK GENMASK(15, 14)
54 #define B_AX_EF_PGPD_MASK GENMASK(30, 28)
56 #define B_AX_EF_VDDQST_MASK GENMASK(26, 24)
57 #define B_AX_EF_PGTS_MASK GENMASK(23, 20)
60 #define B_AX_EF_CELL_SEL_MASK GENMASK(9, 8)
63 #define B_AX_EF_MODE_SEL_MASK GENMASK(31, 30)
66 #define B_AX_EF_ADDR_MASK GENMASK(26, 16)
67 #define B_AX_EF_DATA_MASK GENMASK(15, 0)
72 #define B_AX_EF_TEST_SEL_MASK GENMASK(18, 16)
92 #define B_AX_BTMODE_MASK GENMASK(7, 6)
100 #define B_AX_GPIOSEL_MASK GENMASK(1, 0)
103 #define B_AX_DBG_SEL1_4BIT GENMASK(31, 30)
105 #define B_AX_DBG_SEL1 GENMASK(23, 16)
106 #define B_AX_DBG_SEL0_4BIT GENMASK(15, 14)
108 #define B_AX_DBG_SEL0 GENMASK(7, 0)
127 #define B_AX_R_AX_BG GENMASK(1, 0)
130 #define B_AX_R_AX_VADJ_MASK GENMASK(3, 0)
146 #define B_MAC_AX_SB_FW_MASK GENMASK(30, 24)
147 #define B_MAC_AX_SB_DRV_MASK GENMASK(23, 0)
153 #define B_AX_DEBUG_ST_MASK GENMASK(31, 0)
159 #define B_AX_PCIE_MIO_ADDR_PAGE_V1_MASK GENMASK(20, 16)
162 #define B_AX_PCIE_MIO_WE_MASK GENMASK(11, 8)
164 #define B_AX_PCIE_MIO_ADDR_MASK GENMASK(7, 0)
165 #define MIO_ADDR_PAGE_MASK GENMASK(12, 8)
168 #define B_AX_PCIE_MIO_DATA_MASK GENMASK(31, 0)
171 #define B_AX_CHIP_VER_MASK GENMASK(15, 12)
174 #define B_AX_SEL_0XC0_MASK GENMASK(17, 16)
175 #define B_AX_PAD_HCI_SEL_V2_MASK GENMASK(5, 3)
189 #define B_AX_WCPU_FWDL_STS_MASK GENMASK(7, 5)
198 #define PS_RPWM_SEQ_NUM GENMASK(13, 12)
202 #define PS_CPWM_SEQ_NUM GENMASK(13, 12)
203 #define PS_CPWM_RSP_SEQ_NUM GENMASK(9, 8)
204 #define PS_CPWM_STATE GENMASK(2, 0)
208 #define B_AX_BOOT_REASON_MASK GENMASK(2, 0)
215 #define B_AX_UDM1_MASK GENMASK(31, 16)
216 #define B_AX_UDM1_HALMAC_C2H_ENQ_CNT_MASK GENMASK(15, 12)
217 #define B_AX_UDM1_HALMAC_H2C_DEQ_CNT_MASK GENMASK(11, 8)
218 #define B_AX_UDM1_WCPU_C2H_ENQ_CNT_MASK GENMASK(7, 4)
219 #define B_AX_UDM1_WCPU_H2C_DEQ_CNT_MASK GENMASK(3, 0)
224 #define B_AX_VREFPFM_L_MASK GENMASK(25, 22)
225 #define B_AX_REG_ZCDC_H_MASK GENMASK(18, 17)
226 #define B_AX_OCP_L1_MASK GENMASK(15, 13)
227 #define B_AX_VOL_L1_MASK GENMASK(3, 0)
242 #define B_AX_WL_XTAL_SI_MODE_MASK GENMASK(25, 24)
245 #define B_AX_WL_XTAL_SI_BITMASK_MASK GENMASK(23, 16)
246 #define B_AX_WL_XTAL_SI_DATA_MASK GENMASK(15, 8)
247 #define B_AX_WL_XTAL_SI_ADDR_MASK GENMASK(7, 0)
254 #define B_AX_XTAL_SC_XO_MASK GENMASK(23, 17)
255 #define B_AX_XTAL_SC_XI_MASK GENMASK(16, 10)
256 #define B_AX_XTAL_SC_MASK GENMASK(6, 0)
259 #define B_AX_XTAL_SC_INIT_A_BLOCK_MASK GENMASK(30, 24)
260 #define B_AX_XTAL_SC_LPS_A_BLOCK_MASK GENMASK(22, 16)
261 #define B_AX_XTAL_SC_XO_A_BLOCK_MASK GENMASK(14, 8)
262 #define B_AX_XTAL_SC_XI_A_BLOCK_MASK GENMASK(6, 0)
267 #define B_AX_PINMUX_EESK_FUNC_SEL_MASK GENMASK(7, 4)
270 #define B_AX_PINMUX_GPIO17_FUNC_SEL_MASK GENMASK(7, 4)
271 #define B_AX_PINMUX_GPIO16_FUNC_SEL_MASK GENMASK(3, 0)
274 #define B_AX_PINMUX_EESK_FUNC_SEL_V1_MASK GENMASK(27, 24)
294 #define B_AX_WHOLE_SYS_PWR_STE_MASK GENMASK(25, 16)
295 #define B_AX_WLMAC_PWR_STE_MASK GENMASK(9, 8)
296 #define B_AX_UART_HCISYS_PWR_STE_MASK GENMASK(7, 6)
297 #define B_AX_SDIO_HCISYS_PWR_STE_MASK GENMASK(5, 4)
298 #define B_AX_USB_HCISYS_PWR_STE_MASK GENMASK(3, 2)
299 #define B_AX_PCIE_HCISYS_PWR_STE_MASK GENMASK(1, 0)
302 #define B_AX_C3_L1_MASK GENMASK(5, 4)
303 #define B_AX_C1_L1_MASK GENMASK(1, 0)
306 #define B_AX_S1_LDO_VSEL_F_MASK GENMASK(25, 24)
308 #define B_AX_S0_LDO_VSEL_F_MASK GENMASK(22, 21)
311 #define B_AX_SEC_IDMEM_SIZE_CONFIG_MASK GENMASK(17, 16)
316 #define B_AX_WD_ITVL_IDLE_V1_MASK GENMASK(31, 28)
317 #define B_AX_WD_ITVL_ACT_V1_MASK GENMASK(27, 24)
318 #define B_AX_DMA_MODE_MASK GENMASK(19, 18)
327 #define B_AX_HAXI_MAX_RXDMA_MASK GENMASK(9, 8)
331 #define B_AX_HAXI_MAX_TXDMA_MASK GENMASK(1, 0)
363 #define B_AX_DBG_DUMMY_MASK GENMASK(23, 16)
364 #define B_AX_PCIE_DBG_SEL_MASK GENMASK(15, 13)
383 #define B_AX_LTR_CURR_IDX_DRV_MASK GENMASK(15, 14)
385 #define B_AX_LTR_CURR_IDX_FW_MASK GENMASK(12, 11)
387 #define B_AX_LTR_CURR_IDX_HW_MASK GENMASK(9, 8)
389 #define B_AX_LTR_IDX_DRV_MASK GENMASK(6, 5)
394 #define B_AX_LTR_SPACE_IDX_V1_MASK GENMASK(1, 0)
541 #define B_AX_LTR_SPACE_IDX_MASK GENMASK(13, 12)
542 #define B_AX_LTR_IDLE_TIMER_IDX_MASK GENMASK(10, 8)
551 #define B_AX_LTR_RX1_TH_MASK GENMASK(27, 16)
552 #define B_AX_LTR_RX0_TH_MASK GENMASK(11, 0)
559 #define B_AX_L0_TO_L1_EVENT_MASK GENMASK(31, 28)
608 #define DMAC_ERR_IMR_EN GENMASK(31, 0)
995 #define B_AX_DISPATCHER_DBG_SEL_MASK GENMASK(11, 8)
996 #define B_AX_DISPATCHER_INTN_SEL_MASK GENMASK(7, 4)
997 #define B_AX_DISPATCHER_CH_SEL_MASK GENMASK(3, 0)
1003 #define B_AX_HCI_FC_CH12_FULL_COND_MASK GENMASK(11, 10)
1004 #define B_AX_HCI_FC_WP_CH811_FULL_COND_MASK GENMASK(9, 8)
1005 #define B_AX_HCI_FC_WP_CH07_FULL_COND_MASK GENMASK(7, 6)
1006 #define B_AX_HCI_FC_WD_FULL_COND_MASK GENMASK(5, 4)
1008 #define B_AX_HCI_FC_MODE_MASK GENMASK(2, 1)
1012 #define B_AX_PREC_PAGE_CH12_MASK GENMASK(24, 16)
1013 #define B_AX_PREC_PAGE_CH011_MASK GENMASK(8, 0)
1015 #define B_AX_MAX_PG_MASK GENMASK(28, 16)
1016 #define B_AX_MIN_PG_MASK GENMASK(12, 0)
1031 #define B_AX_AVAL_PG_MASK GENMASK(27, 16)
1032 #define B_AX_USE_PG_MASK GENMASK(12, 0)
1048 #define B_AX_G1_AVAL_PG_MASK GENMASK(28, 16)
1049 #define B_AX_G0_AVAL_PG_MASK GENMASK(12, 0)
1052 #define B_AX_PUBPG_G1_MASK GENMASK(28, 16)
1053 #define B_AX_PUBPG_G0_MASK GENMASK(12, 0)
1056 #define B_AX_PUBPG_ALL_MASK GENMASK(12, 0)
1059 #define B_AX_G1_USE_PG_MASK GENMASK(28, 16)
1060 #define B_AX_G0_USE_PG_MASK GENMASK(12, 0)
1063 #define B_AX_PUB_AVAL_PG_MASK GENMASK(12, 0)
1066 #define B_AX_PREC_PAGE_WP_CH811_MASK GENMASK(24, 16)
1067 #define B_AX_PREC_PAGE_WP_CH07_MASK GENMASK(8, 0)
1070 #define B_AX_WP_THRD_MASK GENMASK(12, 0)
1073 #define B_AX_WP_AVAL_PG_MASK GENMASK(28, 16)
1076 #define B_AX_WDE_START_BOUND_MASK GENMASK(13, 8)
1077 #define B_AX_WDE_PAGE_SEL_MASK GENMASK(1, 0)
1078 #define B_AX_WDE_FREE_PAGE_NUM_MASK GENMASK(28, 16)
1081 #define B_AX_WDE_ERR_FLAG_MSG_MASK GENMASK(31, 0)
1085 #define B_AX_WDE_ERR_FLAG_NUM1_MSTIDX_MASK GENMASK(27, 24)
1086 #define B_AX_WDE_ERR_FLAG_NUM1_ISRIDX_MASK GENMASK(20, 16)
1243 #define B_AX_WDE_MAX_SIZE_MASK GENMASK(27, 16)
1244 #define B_AX_WDE_MIN_SIZE_MASK GENMASK(11, 0)
1251 #define B_AX_DLE_PUB_PGNUM GENMASK(12, 0)
1252 #define B_AX_DLE_FREE_HEADPG GENMASK(11, 0)
1253 #define B_AX_DLE_FREE_TAILPG GENMASK(27, 16)
1254 #define B_AX_DLE_USE_PGNUM GENMASK(27, 16)
1255 #define B_AX_DLE_RSV_PGNUM GENMASK(11, 0)
1256 #define B_AX_DLE_QEMPTY_GRP GENMASK(31, 0)
1264 #define B_AX_WDE_DFI_TRGSEL_MASK GENMASK(19, 16)
1265 #define B_AX_WDE_DFI_ADDR_MASK GENMASK(15, 0)
1267 #define B_AX_WDE_DFI_DATA_MASK GENMASK(31, 0)
1270 #define B_AX_PLE_START_BOUND_MASK GENMASK(13, 8)
1271 #define B_AX_PLE_PAGE_SEL_MASK GENMASK(1, 0)
1272 #define B_AX_PLE_FREE_PAGE_NUM_MASK GENMASK(28, 16)
1296 #define B_AX_PLE_ERR_FLAG_NUM1_MSTIDX_MASK GENMASK(27, 24)
1297 #define B_AX_PLE_ERR_FLAG_NUM1_ISRIDX_MASK GENMASK(20, 16)
1303 #define B_AX_PLE_ERR_FLAG_MSG_MASK GENMASK(31, 0)
1447 #define B_AX_PLE_MAX_SIZE_MASK GENMASK(27, 16)
1448 #define B_AX_PLE_MIN_SIZE_MASK GENMASK(11, 0)
1456 #define B_AX_PLE_Q6_MAX_SIZE_MASK GENMASK(27, 16)
1457 #define B_AX_PLE_Q6_MIN_SIZE_MASK GENMASK(11, 0)
1470 #define B_AX_PLE_DFI_TRGSEL_MASK GENMASK(19, 16)
1471 #define B_AX_PLE_DFI_ADDR_MASK GENMASK(15, 0)
1473 #define B_AX_PLE_DFI_DATA_MASK GENMASK(31, 0)
1476 #define B_AX_RLSRPT_BUFREQ_TO_MASK GENMASK(15, 8)
1477 #define B_AX_WDRLS_MODE_MASK GENMASK(1, 0)
1480 #define B_AX_RLSRPT0_FLTR_MAP_MASK GENMASK(27, 24)
1481 #define B_AX_RLSRPT0_PKTTYPE_MASK GENMASK(19, 16)
1482 #define B_AX_RLSRPT0_PID_MASK GENMASK(10, 8)
1483 #define B_AX_RLSRPT0_QID_MASK GENMASK(5, 0)
1486 #define B_AX_RLSRPT0_TO_MASK GENMASK(23, 16)
1487 #define B_AX_RLSRPT0_AGGNUM_MASK GENMASK(7, 0)
1610 #define B_AX_WD_BUF_REQ_QUOTA_ID_MASK GENMASK(23, 16)
1611 #define B_AX_WD_BUF_REQ_LEN_MASK GENMASK(15, 0)
1616 #define B_AX_WD_BUF_STAT_PKTID_MASK GENMASK(11, 0)
1617 #define S_WD_BUF_STAT_PKTID_INVALID GENMASK(11, 0)
1622 #define B_AX_CPUQ_OP_CMD_TYPE_MASK GENMASK(27, 24)
1623 #define B_AX_CPUQ_OP_MACID_MASK GENMASK(23, 16)
1624 #define B_AX_CPUQ_OP_PKTNUM_MASK GENMASK(7, 0)
1628 #define B_AX_CPUQ_OP_SRC_PID_MASK GENMASK(24, 22)
1629 #define B_AX_CPUQ_OP_SRC_QID_MASK GENMASK(21, 16)
1630 #define B_AX_CPUQ_OP_DST_PID_MASK GENMASK(8, 6)
1631 #define B_AX_CPUQ_OP_DST_QID_MASK GENMASK(5, 0)
1635 #define B_AX_WD_CPUQ_OP_STRT_PKTID_MASK GENMASK(27, 16)
1636 #define B_AX_WD_CPUQ_OP_END_PKTID_MASK GENMASK(11, 0)
1641 #define B_AX_WD_CPUQ_OP_PKTID_MASK GENMASK(11, 0)
1701 #define B_AX_FWD_PPDU_STAT_MASK GENMASK(1, 0)
1719 #define B_AX_SEC_DBG_PORT_FIELD_MASK GENMASK(19, 16)
1743 #define B_AX_TX_TIMEOUT_SEL_MASK GENMASK(31, 30)
1772 #define B_AX_SS_REL_QUEUE_MASK GENMASK(29, 24)
1773 #define B_AX_SS_REL_PORT_MASK GENMASK(18, 16)
1774 #define B_AX_SS_DEST_QUEUE_MASK GENMASK(13, 8)
1776 #define B_AX_SS_DEST_PORT_MASK GENMASK(2, 0)
1780 #define B_AX_SS_MACID31_0_PAUSE_MASK GENMASK(31, 0)
1784 #define B_AX_SS_MACID63_32_PAUSE_MASK GENMASK(31, 0)
1788 #define B_AX_SS_MACID95_64_PAUSE_MASK GENMASK(31, 0)
1792 #define B_AX_SS_MACID127_96_PAUSE_MASK GENMASK(31, 0)
1844 #define B_AX_DFI_TRGSEL_MASK GENMASK(19, 16)
1845 #define B_AX_DFI_ADDR_MASK GENMASK(15, 0)
1847 #define B_AX_DFI_DATA_MASK GENMASK(31, 0)
1851 #define B_AX_B0_PRELD_USEMAXSZ_MASK GENMASK(25, 16)
1854 #define B_AX_B0_PRELD_CAM_G1ENTNUM_MASK GENMASK(12, 8)
1855 #define B_AX_B0_PRELD_CAM_G0ENTNUM_MASK GENMASK(4, 0)
1858 #define B_AX_B0_PRELD_NXT_TXENDWIN_MASK GENMASK(11, 8)
1860 #define B_AX_B0_PRELD_NXT_RSVMINSZ_MASK GENMASK(7, 0)
1922 #define B_AX_B1_PRELD_USEMAXSZ_MASK GENMASK(25, 16)
1924 #define B_AX_B1_PRELD_CAM_G1ENTNUM_MASK GENMASK(12, 8)
1925 #define B_AX_B1_PRELD_CAM_G0ENTNUM_MASK GENMASK(4, 0)
1928 #define B_AX_B1_PRELD_NXT_TXENDWIN_MASK GENMASK(11, 8)
1929 #define B_AX_B1_PRELD_NXT_RSVMINSZ_MASK GENMASK(7, 0)
2021 #define B_AX_CMAC_ALLCKEN GENMASK(31, 0)
2032 #define B_AX_WMAC_RFMOD_MASK GENMASK(1, 0)
2053 #define B_AX_TXSC_80M_MASK GENMASK(11, 8)
2054 #define B_AX_TXSC_40M_MASK GENMASK(7, 4)
2055 #define B_AX_TXSC_20M_MASK GENMASK(3, 0)
2059 #define B_AX_RRSR_RATE_EN_MASK GENMASK(11, 8)
2061 #define B_AX_RSC_MASK GENMASK(7, 6)
2062 #define B_AX_RRSR_CCK_MASK GENMASK(3, 0)
2073 #define CMAC0_ERR_IMR_EN GENMASK(31, 0)
2074 #define CMAC1_ERR_IMR_EN GENMASK(31, 0)
2101 #define B_AX_SYNC_PORT_SRC GENMASK(26, 24)
2103 #define B_AX_SYNC_PORT_OFFSET_VAL GENMASK(17, 0)
2108 #define B_AX_MACID31_0_SLEEP_MASK GENMASK(31, 0)
2113 #define B_AX_MACID63_32_SLEEP_MASK GENMASK(31, 0)
2118 #define B_AX_MACID95_64_SLEEP_MASK GENMASK(31, 0)
2123 #define B_AX_MACID127_96_SLEEP_MASK GENMASK(31, 0)
2128 #define B_AX_PREBKF_TIME_MASK GENMASK(4, 0)
2132 #define B_AX_SIFS_TIMEOUT_TB_AGGR_MASK GENMASK(30, 24)
2133 #define B_AX_SIFS_PREBKF_MASK GENMASK(23, 16)
2134 #define B_AX_SIFS_TIMEOUT_T2_MASK GENMASK(14, 8)
2135 #define B_AX_SIFS_MACTXEN_T1_MASK GENMASK(6, 0)
2167 #define B_AX_CTN_TXEN_ALL_MASK GENMASK(15, 0)
2171 #define B_AX_MUEDCA_BE_PARAM_0_TIMER_MASK GENMASK(31, 16)
2172 #define B_AX_MUEDCA_BE_PARAM_0_CW_MASK GENMASK(15, 8)
2173 #define B_AX_MUEDCA_BE_PARAM_0_AIFS_MASK GENMASK(7, 0)
2218 #define B_AX_CTN_TXEN_ALL_MASK_V1 GENMASK(17, 0)
2230 #define B_AX_SCH_CFG_CMD_SEL GENMASK(15, 8)
2231 #define B_AX_SCH_DBG_SEL_MASK GENMASK(7, 0)
2235 #define B_AX_SCHEDULER_DBG_MASK GENMASK(31, 0)
2251 #define B_AX_NET_TYPE_MASK GENMASK(11, 10)
2268 #define B_AX_TBTT_HOLD_MASK GENMASK(27, 16)
2269 #define B_AX_TBTT_SETUP_MASK GENMASK(7, 0)
2276 #define B_AX_BCN_MSK_AREA_MASK GENMASK(27, 16)
2277 #define B_AX_BCN_CTN_AREA_MASK GENMASK(11, 0)
2284 #define B_AX_BCNERLY_MASK GENMASK(11, 0)
2291 #define B_AX_TBTTERLY_MASK GENMASK(11, 0)
2298 #define B_AX_TBTT_AGG_NUM_MASK GENMASK(15, 8)
2305 #define B_AX_SUB_BCN_SPACE_MASK GENMASK(23, 16)
2306 #define B_AX_BCN_SPACE_MASK GENMASK(15, 0)
2313 #define B_AX_FORCE_BCN_CURRCNT_MASK GENMASK(23, 16)
2314 #define B_AX_FORCE_BCN_NUM_MASK GENMASK(15, 0)
2315 #define B_AX_BCN_MAX_ERR_MASK GENMASK(7, 0)
2322 #define B_AX_BCN_ERR_CNT_SUM_MASK GENMASK(31, 24)
2323 #define B_AX_BCN_ERR_CNT_NAV_MASK GENMASK(23, 16)
2324 #define B_AX_BCN_ERR_CNT_EDCCA_MASK GENMASK(15, 0)
2325 #define B_AX_BCN_ERR_CNT_CCA_MASK GENMASK(7, 0)
2345 #define B_AX_DTIM_NUM_MASK GENMASK(15, 8)
2346 #define B_AX_DTIM_CURRCNT_MASK GENMASK(7, 0)
2353 #define B_AX_TBTT_SHIFT_OFST_MASK GENMASK(11, 0)
2355 #define B_AX_TBTT_SHIFT_OFST_MAG GENMASK(10, 0)
2362 #define B_AX_BCN_CNT_TMR_MASK GENMASK(31, 0)
2369 #define B_AX_TSFTR_LOW_MASK GENMASK(31, 0)
2376 #define B_AX_TSFTR_HIGH_MASK GENMASK(31, 0)
2380 #define B_AX_P0MB_ALL_MASK GENMASK(23, 1)
2381 #define B_AX_P0MB_NUM_MASK GENMASK(19, 16)
2405 #define B_AX_PCIE_MODE_MASK GENMASK(15, 14)
2416 #define B_AX_AMPDU_MAX_TIME_MASK GENMASK(31, 24)
2417 #define B_AX_RA_TRY_RATE_AGG_LMT_MASK GENMASK(23, 16)
2418 #define B_AX_RTS_MAX_AGG_NUM_MASK GENMASK(15, 8)
2419 #define B_AX_MAX_AGG_NUM_MASK GENMASK(7, 0)
2423 #define B_AX_AMPDU_MAX_LEN_HT_MASK GENMASK(31, 16)
2424 #define B_AX_RTS_TXTIME_TH_MASK GENMASK(15, 8)
2425 #define B_AX_RTS_LEN_TH_MASK GENMASK(7, 0)
2430 #define B_AX_HW_CTS2SELF_PKT_LEN_TH_MASK GENMASK(31, 24)
2431 #define B_AX_HW_CTS2SELF_PKT_LEN_TH_TWW_MASK GENMASK(23, 18)
2434 #define B_AX_SPEC_SIFS_OFDM_PTCL_MASK GENMASK(15, 8)
2435 #define B_AX_SPEC_SIFS_CCK_PTCL_MASK GENMASK(7, 0)
2440 #define B_AX_DEFT_RATE_MASK GENMASK(15, 7)
2442 #define B_AX_MAX_TXNSS_MASK GENMASK(3, 2)
2449 #define B_AX_S_TXCNT_LMT_MASK GENMASK(29, 24)
2450 #define B_AX_L_TXCNT_LMT_MASK GENMASK(21, 16)
2455 #define B_AX_RATE_SEL_MASK GENMASK(29, 24)
2456 #define B_AX_PORT_DROP_4_0_MASK GENMASK(20, 16)
2457 #define B_AX_MBSSID_DROP_15_0_MASK GENMASK(15, 0)
2461 #define B_AX_RPT_LATCH_PHY_TIME_MASK GENMASK(15, 12)
2464 #define B_AX_BCN_RPT_PATH_MASK GENMASK(7, 6)
2465 #define B_AX_SPE_RPT_PATH_MASK GENMASK(5, 4)
2467 #define B_AX_TX_RPT_PATH_MASK GENMASK(3, 2)
2473 #define B_AX_BT_PLT_PKT_CNT_MASK GENMASK(31, 16)
2487 #define B_AX_BSS_COLOB_AX_PORT_3_MASK GENMASK(29, 24)
2488 #define B_AX_BSS_COLOB_AX_PORT_2_MASK GENMASK(21, 16)
2489 #define B_AX_BSS_COLOB_AX_PORT_1_MASK GENMASK(13, 8)
2490 #define B_AX_BSS_COLOB_AX_PORT_0_MASK GENMASK(5, 0)
2494 #define B_AX_BSS_COLOB_AX_PORT_4_MASK GENMASK(5, 0)
2516 #define B_AX_PTCL_IMR_CLR_ALL GENMASK(31, 0)
2549 #define B_AX_PTCL_TX_ARB_TO_THR_MASK GENMASK(5, 0)
2557 #define B_AX_PTCL_DBG_INFO_MASK GENMASK(31, 0)
2561 #define B_AX_PTCL_DBG_SEL_MASK GENMASK(7, 0)
2612 #define B_AX_RXDMA_DBG_SEL_MASK GENMASK(30, 29)
2613 #define B_AX_RXDMA_FIFO_DBG_SEL_MASK GENMASK(28, 25)
2614 #define B_AX_RXDMA_DEFAULT_PAGE_MASK GENMASK(22, 21)
2615 #define B_AX_RXDMA_BUFF_REQ_PRI_MASK GENMASK(20, 19)
2616 #define B_AX_RXDMA_TGT_QUEID_MASK GENMASK(18, 13)
2617 #define B_AX_RXDMA_TGT_PRID_MASK GENMASK(12, 10)
2636 #define B_AX_RXDMA_DEFAULT_PAGE_V1_MASK GENMASK(28, 24)
2637 #define B_AX_RXDMA_CSI_TGT_QUEID_MASK GENMASK(23, 18)
2638 #define B_AX_RXDMA_CSI_TGT_PRID_MASK GENMASK(17, 15)
2643 #define B_AX_TXRPT_FULL_RSV_DEPTH_V1_MASK GENMASK(10, 8)
2644 #define B_AX_RXDATA_FULL_RSV_DEPTH_MASK GENMASK(7, 5)
2645 #define B_AX_RXSTS_FULL_RSV_DEPTH_V1_MASK GENMASK(4, 2)
2646 #define B_AX_ORDER_FIFO_MASK GENMASK(1, 0)
2651 #define B_AX_RXDMA_TXRPT_QUEUE_ID_SW_V1_MASK GENMASK(30, 25)
2653 #define B_AX_RXDMA_F2PCMD_QUEUE_ID_SW_V1_MASK GENMASK(23, 18)
2655 #define B_AX_RXDMA_TXRPT_QUEUE_ID_TGT_SW_1_MASK GENMASK(16, 11)
2657 #define B_AX_RXDMA_F2PCMD_QUEUE_ID_TGT_SW_1_MASK GENMASK(9, 4)
2660 #define B_AX_DBG_SEL_MASK GENMASK(1, 0)
2664 #define B_AX_DLE_WDE_STATE_V1_MASK GENMASK(31, 30)
2665 #define B_AX_DLE_PLE_STATE_V1_MASK GENMASK(29, 28)
2666 #define B_AX_DLE_REQ_BUF_STATE_MASK GENMASK(27, 26)
2668 #define B_AX_RX_DBG_SEL_MASK GENMASK(24, 19)
2669 #define B_AX_MACRX_CS_MASK GENMASK(18, 14)
2670 #define B_AX_RXSTS_CS_MASK GENMASK(13, 9)
2672 #define B_AX_TXRPT_CS_MASK GENMASK(4, 0)
2805 #define B_AX_TCR_ZLD_NUM_MASK GENMASK(31, 24)
2807 #define B_AX_TCR_UDF_THSD_MASK GENMASK(22, 16)
2809 #define B_AX_TCR_ERRSTEN_MASK GENMASK(15, 10)
2823 #define B_AX_TXDFIFO_THRESHOLD GENMASK(31, 28)
2826 #define B_AX_TCR_USTIME GENMASK(23, 16)
2831 #define B_AX_TCR_ZLD_USTIME_AFTERPHYTXON GENMASK(11, 8)
2832 #define B_AX_TCR_TXTIMEOUT GENMASK(7, 0)
2836 #define B_AX_TSFT_OFS_MASK GENMASK(31, 16)
2837 #define B_AX_STMP_THSD_MASK GENMASK(15, 8)
2846 #define B_AX_NON_LEGACY_PPDU_ZLD_USTIMER_MASK GENMASK(28, 24)
2847 #define B_AX_LEGACY_PPDU_ZLD_USTIMER_MASK GENMASK(20, 16)
2848 #define B_AX_TXDFIFO_HIGH_MCS_THRE_MASK GENMASK(15, 12)
2850 #define B_AX_TXDFIFO_LOW_MCS_THRE_MASK GENMASK(11, 8)
2852 #define B_AX_HIGH_MCS_PHY_RATE_MASK GENMASK(7, 4)
2853 #define B_AX_BW_PHY_RATE_MASK GENMASK(1, 0)
2857 #define B_AX_MACTX_MPDU_CNT GENMASK(31, 24)
2858 #define B_AX_MACTX_DMA_CNT GENMASK(23, 16)
2863 #define B_AX_DBGSEL_MACTX_MASK GENMASK(5, 0)
2867 #define B_AX_TX_CTRL_DEBUG_SEL_MASK GENMASK(3, 0)
2871 #define B_AX_TX_CTRL_INFO_P0_MASK GENMASK(31, 0)
2875 #define B_AX_TX_CTRL_INFO_P1_MASK GENMASK(31, 0)
2887 #define B_AX_ACKTO_CCK_MASK GENMASK(15, 8)
2888 #define B_AX_ACKTO_MASK GENMASK(7, 0)
2905 #define B_AX_WMAC_SPEC_SIFS_OFDM_MASK GENMASK(15, 8)
2906 #define B_AX_WMAC_SPEC_SIFS_CCK_MASK GENMASK(7, 0)
2915 #define B_AX_RESP_TX_PWRMODE_MASK GENMASK(30, 28)
2916 #define B_AX_FTM_RRSR_RATE_EN_MASK GENMASK(27, 24)
2917 #define B_AX_NESS_MASK GENMASK(23, 22)
2920 #define B_AX_WMAC_RRSB_AX_CCK_MASK GENMASK(19, 16)
2921 #define B_AX_WMAC_RESP_RATE_EN_MASK GENMASK(15, 12)
2922 #define B_AX_WMAC_RESP_RSC_MASK GENMASK(11, 10)
2924 #define B_AX_WMAC_RESP_REF_RATE_MASK GENMASK(8, 0)
2933 #define B_AX_WMAC_0P125US_TIMER_MASK GENMASK(25, 18)
2936 #define B_AX_WMAC_NAV_UPPER_MASK GENMASK(15, 8)
2939 #define B_AX_WMAC_RTS_RST_DUR_MASK GENMASK(7, 0)
2943 #define B_AX_RXTRIG_MACID_MASK GENMASK(31, 24)
2946 #define B_AX_RXTRIG_PORT_SEL_MASK GENMASK(19, 17)
2948 #define B_AX_RXTRIG_USERINFO_2_MASK GENMASK(15, 0)
2953 #define B_AX_WMAC_TIMETOUT_THR_MASK GENMASK(21, 16)
2995 #define B_AX_WMAC_TX_TF_INFO_SEL_MASK GENMASK(2, 0)
2999 #define B_AX_WMAC_TX_TF_INFO_P0_MASK GENMASK(31, 0)
3003 #define B_AX_WMAC_TX_TF_INFO_P1_MASK GENMASK(31, 0)
3020 #define B_AX_TMAC_TIMETOUT_THR_MASK GENMASK(5, 0)
3032 #define B_AX_DBGSEL_TRXPTCL_MASK GENMASK(7, 0)
3036 #define B_AX_PHYINTF_TIMEOUT_THR_MSAK_V1 GENMASK(21, 16)
3070 #define B_AX_PHYINTF_TIMEOUT_THR_MSAK GENMASK(5, 0)
3083 #define B_AX_BFMER_HE_CSI_OFFSET_MASK GENMASK(31, 24)
3084 #define B_AX_BFMER_VHT_CSI_OFFSET_MASK GENMASK(23, 16)
3085 #define B_AX_BFMER_HT_CSI_OFFSET_MASK GENMASK(15, 8)
3091 #define B_AX_BFMEE_NDP_RX_STANDBY_TIMER_MASK GENMASK(31, 24)
3092 #define B_AX_BFMEE_BFRP_RX_STANDBY_TIMER_MASK GENMASK(23, 20)
3095 #define B_AX_MU_BFRPTSEG_SEL_MASK GENMASK(18, 17)
3109 #define B_AX_BFMEE_OFDM_LEN_TH_MASK GENMASK(27, 24)
3114 #define B_AX_BFMEE_CSI_RSC_MASK GENMASK(19, 18)
3121 #define B_AX_BFMEE_CSIINFO0_CS_MASK GENMASK(11, 10)
3122 #define B_AX_BFMEE_CSIINFO0_CB_MASK GENMASK(9, 8)
3123 #define B_AX_BFMEE_CSIINFO0_NG_MASK GENMASK(7, 6)
3124 #define B_AX_BFMEE_CSIINFO0_NR_MASK GENMASK(5, 3)
3125 #define B_AX_BFMEE_CSIINFO0_NC_MASK GENMASK(2, 0)
3133 #define B_AX_BFMEE_HE_CSI_RATE_MASK GENMASK(22, 16)
3134 #define B_AX_BFMEE_VHT_CSI_RATE_MASK GENMASK(14, 8)
3135 #define B_AX_BFMEE_HT_CSI_RATE_MASK GENMASK(6, 0)
3143 #define B_AX_DRV_INFO_SIZE_MASK GENMASK(10, 8)
3144 #define B_AX_CH_EN_MASK GENMASK(3, 0)
3148 #define B_AX_RX_DLK_CCA_TIME_MASK GENMASK(15, 8)
3149 #define B_AX_RX_DLK_DATA_TIME_MASK GENMASK(7, 4)
3164 #define B_AX_UID_FILTER_MASK GENMASK(31, 24)
3166 #define B_AX_UNSPT_FILTER_MASK GENMASK(23, 22)
3167 #define B_AX_RX_MPDU_MAX_LEN_MASK GENMASK(21, 16)
3174 #define B_AX_A_BCN_CHK_RULE_MASK GENMASK(9, 8)
3202 #define B_AX_ADDR_CAM_RANGE_MASK GENMASK(23, 16)
3203 #define B_AX_ADDR_CAM_CMPLIMT_MASK GENMASK(15, 12)
3212 #define B_AX_BACAM_RST_MASK GENMASK(1, 0)
3236 #define B_AX_RX_STATE_MONITOR_MASK GENMASK(31, 0)
3237 #define B_AX_STATE_CUR_MASK GENMASK(31, 16)
3238 #define B_AX_STATE_NXT_MASK GENMASK(13, 8)
3240 #define B_AX_STATE_SEL_MASK GENMASK(4, 0)
3309 #define B_AX_RMAC_PLCP_MON_MASK GENMASK(31, 0)
3310 #define B_AX_PCLP_MON_SEL_MASK GENMASK(31, 28)
3311 #define B_AX_PCLP_MON_CONT_MASK GENMASK(27, 0)
3315 #define B_AX_DEBUG_SEL_MASK GENMASK(7, 0)
3319 #define B_AX_PWR_REF GENMASK(27, 10)
3321 #define B_AX_FORCE_PWR_BY_RATE_VALUE_MASK GENMASK(8, 0)
3326 #define B_AX_TXAGC_BT_MASK GENMASK(11, 3)
3330 #define B_AX_CFIR_BY_RATE_OFF_MASK GENMASK(17, 0)
3334 #define B_AX_PWR_UL_CFO_MASK GENMASK(2, 0)
3340 #define B_AX_TXAGC_BF_PWR_BOOST_FORCE_VAL_MASK GENMASK(28, 24)
3352 #define B_AX_FORCE_TXSC_VALUE_MASK GENMASK(12, 9)
3356 #define B_AX_FORCE_PWR_MODE_VALUE_MASK GENMASK(2, 0)
3361 #define B_AX_PWR_UL_TB_1T_MASK GENMASK(4, 0)
3362 #define B_AX_PWR_UL_TB_1T_V1_MASK GENMASK(7, 0)
3364 #define B_AX_PWR_UL_TB_2T_MASK GENMASK(4, 0)
3365 #define B_AX_PWR_UL_TB_2T_V1_MASK GENMASK(7, 0)
3430 #define B_AX_BANDEDGE_CFG_IDX_MASK GENMASK(31, 30)
3443 #define B_AX_BTC_MODE_MASK GENMASK(25, 24)
3446 #define B_AX_COEX_DLY_CLK_MASK GENMASK(15, 8)
3450 #define B_AX_BTC_DBG_SEL_MASK GENMASK(4, 3)
3459 #define B_AX_BT_L_RX_ULTRA_MASK GENMASK(15, 14)
3460 #define B_AX_BT_L_TX_ULTRA_MASK GENMASK(13, 12)
3461 #define B_AX_BT_H_RX_ULTRA_MASK GENMASK(11, 10)
3462 #define B_AX_BT_H_TX_ULTRA_MASK GENMASK(9, 8)
3463 #define B_AX_SAMPLE_CLK_MASK GENMASK(7, 0)
3496 #define B_AX_TIMER_MASK GENMASK(7, 0)
3502 #define B_AX_BT_STAT_DELAY_MASK GENMASK(15, 12)
3504 #define B_AX_BT_TRX_INIT_DETECT_MASK GENMASK(11, 8)
3506 #define B_AX_BT_PRI_DETECT_TO_MASK GENMASK(7, 4)
3516 #define B_AX_STATIS_BT_HI_RX_MASK GENMASK(31, 16)
3517 #define B_AX_STATIS_BT_HI_TX_MASK GENMASK(15, 0)
3519 #define B_AX_STATIS_BT_LO_TX_1_MASK GENMASK(15, 0)
3520 #define B_AX_STATIS_BT_LO_RX_1_MASK GENMASK(31, 16)
3561 #define B_AX_R_BT_CMD_RPT_MASK GENMASK(31, 16)
3562 #define B_AX_R_RPT_FROM_BT_MASK GENMASK(15, 8)
3563 #define B_AX_BT_HID_ISR_SET_MASK GENMASK(7, 6)
3573 #define B_AX_BT_TIME_MASK GENMASK(31, 6)
3574 #define B_AX_BT_RPT_SAMPLE_RATE_MASK GENMASK(5, 0)
3612 #define B_AX_LTECOEX_OP_MODE_SEL_MASK GENMASK(5, 4)
3614 #define B_AX_LTECOEX_UART_MODE_SEL_MASK GENMASK(2, 0)
3632 #define B_BE_UID_FILTER_MASK GENMASK(31, 24)
3634 #define B_BE_RX_MPDU_MAX_LEN_MASK GENMASK(21, 16)
3639 #define B_BE_A_BCN_CHK_RULE_MASK GENMASK(9, 8)
3651 #define RR_MOD_IQK GENMASK(19, 4)
3652 #define RR_MOD_DPK GENMASK(19, 5)
3653 #define RR_MOD_MASK GENMASK(19, 16)
3654 #define RR_MOD_DCK GENMASK(14, 10)
3655 #define RR_MOD_RGM GENMASK(13, 4)
3656 #define RR_MOD_RXB GENMASK(9, 5)
3666 #define RR_MOD_NBW GENMASK(15, 14)
3667 #define RR_MOD_M_RXG GENMASK(13, 4)
3668 #define RR_MOD_M_RXBB GENMASK(9, 5)
3671 #define RR_MODOPT_M_TXPWR GENMASK(5, 0)
3673 #define RR_WLSEL_AG GENMASK(18, 16)
3681 #define RR_LOKVB_COI GENMASK(19, 14)
3682 #define RR_LOKVB_COQ GENMASK(9, 4)
3684 #define RR_TXIG_TG GENMASK(16, 12)
3685 #define RR_TXIG_GR1 GENMASK(6, 4)
3686 #define RR_TXIG_GR0 GENMASK(1, 0)
3688 #define RR_CHTR_MOD GENMASK(11, 10)
3689 #define RR_CHTR_TXRX GENMASK(9, 0)
3692 #define RR_CFGCH_BAND1 GENMASK(17, 16)
3700 #define RR_CFGCH_BAND0 GENMASK(9, 8)
3704 #define RR_CFGCH_BW GENMASK(11, 10)
3705 #define RR_CFGCH_CH GENMASK(7, 0)
3711 #define RR_APK_MOD GENMASK(5, 4)
3713 #define RR_BTC_TXBB GENMASK(14, 12)
3714 #define RR_BTC_RXBB GENMASK(11, 10)
3716 #define RR_RCKC_CA GENMASK(14, 10)
3719 #define RR_RCKO_OFF GENMASK(13, 9)
3721 #define RR_RXKPLL_OFF GENMASK(5, 0)
3724 #define RR_RSV4_AGH GENMASK(17, 16)
3725 #define RR_RSV4_PLLCH GENMASK(9, 0)
3731 #define RR_LUTWA_MASK GENMASK(9, 0)
3732 #define RR_LUTWA_M1 GENMASK(7, 0)
3733 #define RR_LUTWA_M2 GENMASK(4, 0)
3736 #define RR_LUTWD0_MB GENMASK(11, 6)
3737 #define RR_LUTWD0_LB GENMASK(5, 0)
3740 #define RR_TM_VAL GENMASK(6, 1)
3742 #define RR_TM2_OFF GENMASK(19, 16)
3751 #define RR_TXGA_LOK_EXT GENMASK(4, 0)
3756 #define RR_GAINTX_ALL GENMASK(15, 0)
3757 #define RR_GAINTX_PAD GENMASK(9, 5)
3758 #define RR_GAINTX_BB GENMASK(4, 0)
3760 #define RR_TXMO_COI GENMASK(19, 15)
3761 #define RR_TXMO_COQ GENMASK(14, 10)
3762 #define RR_TXMO_FII GENMASK(9, 6)
3763 #define RR_TXMO_FIQ GENMASK(5, 2)
3765 #define RR_TXA_TRK GENMASK(19, 14)
3771 #define RR_TXAC_IQG GENMASK(3, 0)
3773 #define RR_BIASA_TXG GENMASK(15, 12)
3774 #define RR_BIASA_TXA GENMASK(19, 16)
3775 #define RR_BIASA_A GENMASK(2, 0)
3777 #define RR_BIASA2_LB GENMASK(4, 2)
3779 #define RR_TXATANK_LBSW2 GENMASK(17, 15)
3780 #define RR_TXATANK_LBSW GENMASK(16, 15)
3782 #define RR_TXA2_LDO GENMASK(19, 16)
3792 #define RR_RXPOW_IQK GENMASK(17, 16)
3794 #define RR_RXBB_VOBUF GENMASK(15, 12)
3795 #define RR_RXBB_C2G GENMASK(16, 10)
3796 #define RR_RXBB_C2 GENMASK(11, 8)
3797 #define RR_RXBB_C1G GENMASK(9, 8)
3798 #define RR_RXBB_FATT GENMASK(7, 0)
3799 #define RR_RXBB_ATTR GENMASK(7, 4)
3800 #define RR_RXBB_ATTC GENMASK(2, 0)
3802 #define RR_RXG_IQKMOD GENMASK(19, 16)
3804 #define RR_XGLNA2_SW GENMASK(1, 0)
3806 #define RR_RXAE_IQKMOD GENMASK(3, 0)
3808 #define RR_RXA_DPK GENMASK(9, 8)
3811 #define RR_RAA2_SATT GENMASK(15, 13)
3812 #define RR_RAA2_SWATT GENMASK(15, 9)
3813 #define RR_RXA2_C1 GENMASK(12, 10)
3814 #define RR_RXA2_C2 GENMASK(9, 3)
3815 #define RR_RXA2_CC2 GENMASK(8, 7)
3816 #define RR_RXA2_IATT GENMASK(7, 4)
3817 #define RR_RXA2_HATT GENMASK(6, 0)
3818 #define RR_RXA2_ATT GENMASK(3, 0)
3820 #define RR_RXIQGEN_ATTL GENMASK(12, 8)
3821 #define RR_RXIQGEN_ATTH GENMASK(14, 13)
3825 #define RR_EN_TIA_IDA GENMASK(11, 10)
3826 #define RR_RXBB2_IDAC GENMASK(11, 9)
3827 #define RR_RXBB2_EBW GENMASK(6, 5)
3829 #define RR_XALNA2_SW2 GENMASK(9, 8)
3830 #define RR_XALNA2_SW GENMASK(1, 0)
3832 #define RR_DCK_S1 GENMASK(19, 16)
3833 #define RR_DCK_TIA GENMASK(15, 9)
3834 #define RR_DCK_DONE GENMASK(7, 5)
3838 #define RR_DCK1_S1 GENMASK(19, 16)
3839 #define RR_DCK1_TIA GENMASK(15, 9)
3841 #define RR_DCK1_CLR GENMASK(3, 0)
3844 #define RR_DCK2_CYCLE GENMASK(7, 2)
3848 #define RR_IQGEN_BIAS GENMASK(11, 8)
3850 #define RR_TXIQK_ATT2 GENMASK(15, 12)
3851 #define RR_TXIQK_ATT1 GENMASK(6, 0)
3855 #define RR_MIXER_GN GENMASK(4, 3)
3857 #define RR_POW_SYN GENMASK(3, 2)
3859 #define RR_LOGEN_RPT GENMASK(19, 16)
3862 #define RR_IBD_VAL GENMASK(4, 0)
3864 #define RR_LDO_SEL GENMASK(8, 6)
3866 #define RR_VCO_SEL GENMASK(9, 8)
3885 #define RR_IQKPLL_MOD GENMASK(9, 8)
3889 #define RR_RCKD_POW GENMASK(19, 13)
3912 #define B_ANAPAR_PW15 GENMASK(31, 24)
3913 #define B_ANAPAR_PW15_H GENMASK(27, 24)
3914 #define B_ANAPAR_PW15_H2 GENMASK(27, 26)
3916 #define B_ANAPAR_15 GENMASK(31, 16)
3919 #define B_ANAPAR_CRXBB GENMASK(18, 16)
3921 #define B_ANAPAR_14 GENMASK(15, 0)
3925 #define B_RFE_SEL0_MASK GENMASK(1, 0)
3928 #define B_CIRST_SYN GENMASK(11, 10)
3930 #define B_SWSI_DATA_VAL_V1 GENMASK(19, 0)
3931 #define B_SWSI_DATA_ADDR_V1 GENMASK(27, 20)
3932 #define B_SWSI_DATA_PATH_V1 GENMASK(30, 28)
3935 #define B_SWSI_BIT_MASK_V1 GENMASK(19, 0)
3937 #define B_SWSI_READ_ADDR_ADDR_V1 GENMASK(7, 0)
3938 #define B_SWSI_READ_ADDR_PATH_V1 GENMASK(10, 8)
3939 #define B_SWSI_READ_ADDR_V1 GENMASK(10, 0)
3941 #define B_UPD_CLK_ADC_VAL GENMASK(26, 25)
3948 #define B_P0_TRSW_TX_EXTEND GENMASK(3, 0)
3950 #define B_CH_IDX_SEG0 GENMASK(23, 16)
3952 #define B_STS_PARSING_TIME GENMASK(19, 16)
3956 #define B_PHY_STS_BITMAP_ADDR_MASK GENMASK(6, 2)
3976 #define B_PMAC_GNT_P1 GENMASK(20, 17)
3977 #define B_PMAC_GNT_P2 GENMASK(29, 26)
3979 #define B_PMAC_OPT1_MSK GENMASK(11, 0)
3981 #define B_PMAC_RXMOD_MSK GENMASK(7, 4)
3986 #define B_MAC_SEL_MOD GENMASK(4, 2)
3990 #define B_PMAC_TX_PRD_MSK GENMASK(31, 8)
3994 #define B_PMAC_TX_CNT_MSK GENMASK(31, 0)
4000 #define B_CCX_EDCCA_OPT_MSK GENMASK(6, 4)
4001 #define B_CCX_EDCCA_OPT_MSK_V1 GENMASK(7, 4)
4006 #define B_IFS_CLM_PERIOD_MSK GENMASK(31, 16)
4007 #define B_IFS_CLM_COUNTER_UNIT_MSK GENMASK(15, 14)
4011 #define B_IFS_T1_TH_HIGH_MSK GENMASK(31, 16)
4013 #define B_IFS_T1_TH_LOW_MSK GENMASK(14, 0)
4015 #define B_IFS_T2_TH_HIGH_MSK GENMASK(31, 16)
4017 #define B_IFS_T2_TH_LOW_MSK GENMASK(14, 0)
4019 #define B_IFS_T3_TH_HIGH_MSK GENMASK(31, 16)
4021 #define B_IFS_T3_TH_LOW_MSK GENMASK(14, 0)
4023 #define B_IFS_T4_TH_HIGH_MSK GENMASK(31, 16)
4025 #define B_IFS_T4_TH_LOW_MSK GENMASK(14, 0)
4035 #define B_SNDCCA_A1_EN GENMASK(19, 12)
4037 #define B_SNDCCA_A2_VAL GENMASK(19, 12)
4039 #define B_RXHT_MCS_LIMIT GENMASK(9, 8)
4041 #define B_RXVHT_MCS_LIMIT GENMASK(22, 21)
4045 #define B_RXHETB_MAX_NSS GENMASK(25, 23)
4046 #define B_RXHE_MAX_NSS GENMASK(16, 14)
4047 #define B_RXHE_USER_MAX GENMASK(13, 6)
4057 #define B_S0_HW_SI_DIS_W_R_TRIG GENMASK(30, 28)
4059 #define B_P0_RXCK_ADJ GENMASK(31, 23)
4061 #define B_P0_TXCK_ALL GENMASK(19, 12)
4063 #define B_P0_RXCK_VAL GENMASK(18, 16)
4065 #define B_P0_TXCK_VAL GENMASK(14, 12)
4067 #define B_P0_RFMODE_ORI_TXRX_FTM_TX GENMASK(31, 4)
4068 #define B_P0_RFMODE_MUX GENMASK(11, 4)
4070 #define B_P0_RFMODE_ORI_RX_ALL GENMASK(23, 12)
4072 #define B_P0_RFMODE_FTM_RX GENMASK(11, 0)
4076 #define B_S0_RXDC_I GENMASK(25, 16)
4077 #define B_S0_RXDC_Q GENMASK(31, 26)
4079 #define B_S0_RXDC2_SEL GENMASK(9, 8)
4080 #define B_S0_RXDC2_AVG GENMASK(7, 6)
4081 #define B_S0_RXDC2_MEN GENMASK(5, 4)
4082 #define B_S0_RXDC2_Q2 GENMASK(3, 0)
4094 #define B_IFS_CLM_EDCCA_EXCLUDE_CCA_FA_MSK GENMASK(31, 16)
4095 #define B_IFS_CLM_TX_CNT_MSK GENMASK(15, 0)
4098 #define B_IFS_CLM_OFDMCCA_EXCLUDE_FA_MSK GENMASK(31, 16)
4099 #define B_IFS_CLM_CCKCCA_EXCLUDE_FA_MSK GENMASK(15, 0)
4102 #define B_IFS_CLM_OFDM_FA_MSK GENMASK(31, 16)
4103 #define B_IFS_CLM_CCK_FA_MSK GENMASK(15, 0)
4106 #define B_IFS_T4_HIS_MSK GENMASK(31, 24)
4107 #define B_IFS_T3_HIS_MSK GENMASK(23, 16)
4108 #define B_IFS_T2_HIS_MSK GENMASK(15, 8)
4109 #define B_IFS_T1_HIS_MSK GENMASK(7, 0)
4112 #define B_IFS_T2_AVG_MSK GENMASK(31, 16)
4113 #define B_IFS_T1_AVG_MSK GENMASK(15, 0)
4116 #define B_IFS_T4_AVG_MSK GENMASK(31, 16)
4117 #define B_IFS_T3_AVG_MSK GENMASK(15, 0)
4120 #define B_IFS_T2_CCA_MSK GENMASK(31, 16)
4121 #define B_IFS_T1_CCA_MSK GENMASK(15, 0)
4124 #define B_IFS_T4_CCA_MSK GENMASK(31, 16)
4125 #define B_IFS_T3_CCA_MSK GENMASK(15, 0)
4129 #define B_IFSCNT_TOTAL_CNT_MSK GENMASK(15, 0)
4131 #define B_TXAGC_TP GENMASK(2, 0)
4133 #define B_TSSI_THER GENMASK(29, 24)
4136 #define B_TSSI_CWRPT GENMASK(8, 0)
4138 #define B_TXAGC_BTP GENMASK(31, 24)
4140 #define B_TXAGC_BB_OFT GENMASK(31, 16)
4141 #define B_TXAGC_BB GENMASK(31, 24)
4142 #define B_TXAGC_RF GENMASK(5, 0)
4144 #define B_PATH0_TXPWR GENMASK(8, 0)
4146 #define B_S0_ADDCK_I GENMASK(9, 0)
4147 #define B_S0_ADDCK_Q GENMASK(19, 10)
4149 #define B_ADC_FIFO_RST GENMASK(31, 24)
4150 #define B_ADC_FIFO_RXK GENMASK(31, 16)
4156 #define B_TXFIR_C01 GENMASK(23, 0)
4158 #define B_TXFIR_C23 GENMASK(23, 0)
4160 #define B_TXFIR_C45 GENMASK(23, 0)
4162 #define B_TXFIR_C67 GENMASK(23, 0)
4164 #define B_TXFIR_C89 GENMASK(23, 0)
4166 #define B_TXFIR_CAB GENMASK(23, 0)
4168 #define B_TXFIR_CCD GENMASK(23, 0)
4170 #define B_TXFIR_CEF GENMASK(23, 0)
4174 #define B_RPL_OFST_MASK GENMASK(14, 8)
4182 #define B_RX_RPL_OFST_CCK_MASK GENMASK(6, 0)
4184 #define B_RXSCOBC_TH GENMASK(18, 0)
4186 #define B_RXSCOCCK_TH GENMASK(18, 0)
4195 #define B_S1_HW_SI_DIS_W_R_TRIG GENMASK(30, 28)
4198 #define B_P1_TXCK_ALL GENMASK(19, 12)
4200 #define B_P1_RXCK_VAL GENMASK(18, 16)
4202 #define B_P1_RFMODE_ORI_TXRX_FTM_TX GENMASK(31, 4)
4203 #define B_P1_RFMODE_MUX GENMASK(11, 4)
4205 #define B_P1_RFMODE_ORI_RX_ALL GENMASK(23, 12)
4207 #define B_P1_RFMODE_FTM_RX GENMASK(11, 0)
4211 #define B_S1_RXDC_I GENMASK(25, 16)
4212 #define B_S1_RXDC_Q GENMASK(31, 26)
4214 #define B_S1_RXDC2_EN GENMASK(5, 4)
4215 #define B_S1_RXDC2_SEL GENMASK(9, 8)
4216 #define B_S1_RXDC2_Q2 GENMASK(3, 0)
4218 #define B_TXAGC_BB_S1_OFT GENMASK(31, 16)
4219 #define B_TXAGC_BB_S1 GENMASK(31, 24)
4221 #define B_PATH1_TXPWR GENMASK(8, 0)
4223 #define B_S1_ADDCK_I GENMASK(9, 0)
4224 #define B_S1_ADDCK_Q GENMASK(19, 10)
4228 #define B_DCFO GENMASK(7, 0)
4231 #define B_SEG0CSI_IDX GENMASK(10, 0)
4238 #define B_BSS_CLR_MAP_TGT GENMASK(27, 22)
4239 #define B_BSS_CLR_MAP_STAID GENMASK(21, 11)
4242 #define B_CFO_TRK_MSK GENMASK(14, 10)
4253 #define B_DCFO_COMP_S0_MSK GENMASK(11, 0)
4255 #define B_DCFO_WEIGHT_MSK GENMASK(27, 24)
4258 #define B_TXSHAPE_TRIANGULAR_CFG GENMASK(25, 24)
4262 #define B_DPD_BF_OFDM GENMASK(16, 12)
4263 #define B_DPD_BF_SCA GENMASK(6, 0)
4265 #define B_TXPATH_SEL_MSK GENMASK(31, 28)
4267 #define B_TXPWR_MSK GENMASK(30, 22)
4269 #define B_TXNSS_MAP_MSK GENMASK(20, 17)
4271 #define B_PCOEFF01_MSK_V1 GENMASK(23, 0)
4273 #define B_PCOEFF23_MSK_V1 GENMASK(23, 0)
4275 #define B_PCOEFF45_MSK_V1 GENMASK(23, 0)
4277 #define B_PCOEFF67_MSK_V1 GENMASK(23, 0)
4279 #define B_PCOEFF89_MSK_V1 GENMASK(23, 0)
4281 #define B_PCOEFFAB_MSK_V1 GENMASK(23, 0)
4283 #define B_PCOEFFCD_MSK_V1 GENMASK(23, 0)
4285 #define B_PCOEFFEF_MSK_V1 GENMASK(23, 0)
4287 #define B_PATH0_IB_PKPW_MSK GENMASK(11, 6)
4289 #define B_PATH0_LNA_ERR_G1_A_MSK GENMASK(29, 24)
4290 #define B_PATH0_LNA_ERR_G0_G_MSK GENMASK(17, 12)
4291 #define B_PATH0_LNA_ERR_G0_A_MSK GENMASK(11, 6)
4293 #define B_PATH0_LNA_ERR_G2_G_MSK GENMASK(23, 18)
4294 #define B_PATH0_LNA_ERR_G2_A_MSK GENMASK(17, 12)
4295 #define B_PATH0_LNA_ERR_G1_G_MSK GENMASK(5, 0)
4297 #define B_PATH0_LNA_ERR_G4_G_MSK GENMASK(29, 24)
4298 #define B_PATH0_LNA_ERR_G4_A_MSK GENMASK(23, 18)
4299 #define B_PATH0_LNA_ERR_G3_G_MSK GENMASK(11, 6)
4300 #define B_PATH0_LNA_ERR_G3_A_MSK GENMASK(5, 0)
4302 #define B_PATH0_LNA_ERR_G6_A_MSK GENMASK(29, 24)
4303 #define B_PATH0_LNA_ERR_G5_G_MSK GENMASK(17, 12)
4304 #define B_PATH0_LNA_ERR_G5_A_MSK GENMASK(11, 6)
4306 #define B_PATH0_LNA_ERR_G6_G_MSK GENMASK(5, 0)
4308 #define B_PATH0_TIA_ERR_G0_G_MSK GENMASK(23, 18)
4309 #define B_PATH0_TIA_ERR_G0_A_MSK GENMASK(17, 12)
4311 #define B_PATH0_TIA_ERR_G1_SEL GENMASK(31, 30)
4312 #define B_PATH0_TIA_ERR_G1_G_MSK GENMASK(11, 6)
4313 #define B_PATH0_TIA_ERR_G1_A_MSK GENMASK(5, 0)
4315 #define B_PATH0_IB_PBK_MSK GENMASK(14, 10)
4317 #define B_PATH0_RXB_INIT_IDX_MSK GENMASK(9, 5)
4320 #define B_PATH0_LNA_INIT_IDX_MSK GENMASK(26, 24)
4322 #define B_PATH0_BTG_SHEN GENMASK(18, 17)
4334 #define B_PATH0_RXB_INIT_IDX_MSK_V1 GENMASK(14, 10)
4336 #define B_PATH0_G_LNA6_OP1DB_V1 GENMASK(31, 24)
4338 #define B_PATH0_G_TIA0_LNA6_OP1DB_V1 GENMASK(7, 0)
4340 #define B_PATH0_R_G_OFST_MASK GENMASK(23, 16)
4341 #define B_PATH0_G_TIA1_LNA6_OP1DB_V1 GENMASK(15, 8)
4351 #define B_P0_NBIIDX_VAL GENMASK(11, 0)
4354 #define B_P0_BACKOFF_IBADC_V1 GENMASK(31, 26)
4357 #define B_P1_MODE_SEL GENMASK(31, 30)
4362 #define B_PATH1_LNA_INIT_IDX_MSK GENMASK(26, 24)
4368 #define B_PATH1_BTG_SHEN GENMASK(18, 17)
4370 #define B_PATH1_RXB_INIT_IDX_MSK GENMASK(9, 5)
4372 #define B_PATH1_G_LNA6_OP1DB_V1 GENMASK(31, 24)
4382 #define B_PATH1_G_TIA0_LNA6_OP1DB_V1 GENMASK(7, 0)
4384 #define B_PATH1_G_TIA1_LNA6_OP1DB_V1 GENMASK(15, 8)
4392 #define B_P1_NBIIDX_VAL GENMASK(11, 0)
4401 #define B_SEG0R_PPDU_LVL_MSK GENMASK(31, 24)
4402 #define B_SEG0R_EDCCA_LVL_P_MSK GENMASK(15, 8)
4403 #define B_SEG0R_EDCCA_LVL_A_MSK GENMASK(7, 0)
4406 #define B_SEG0R_PD_LOWER_BOUND_MSK GENMASK(10, 6)
4411 #define B_FC0_BW_SET GENMASK(31, 30)
4412 #define B_ANT_RX_BT_SEG0 GENMASK(25, 22)
4413 #define B_ANT_RX_1RCCA_SEG1 GENMASK(21, 18)
4414 #define B_ANT_RX_1RCCA_SEG0 GENMASK(17, 14)
4415 #define B_FC0_BW_INV GENMASK(6, 0)
4419 #define B_CHBW_MOD_SBW GENMASK(13, 12)
4420 #define B_CHBW_MOD_PRICH GENMASK(11, 8)
4421 #define B_ANT_RX_SEG0 GENMASK(3, 0)
4423 #define B_P0_RPL1_41_MASK GENMASK(31, 24)
4424 #define B_P0_RPL1_40_MASK GENMASK(23, 16)
4425 #define B_P0_RPL1_20_MASK GENMASK(15, 8)
4428 #define B_P0_RPL1_BIAS_MASK GENMASK(7, 0)
4430 #define B_P0_RTL2_8A_MASK GENMASK(31, 24)
4431 #define B_P0_RTL2_81_MASK GENMASK(23, 16)
4432 #define B_P0_RTL2_80_MASK GENMASK(15, 8)
4433 #define B_P0_RTL2_42_MASK GENMASK(7, 0)
4435 #define B_P0_RTL3_89_MASK GENMASK(31, 24)
4436 #define B_P0_RTL3_84_MASK GENMASK(23, 16)
4437 #define B_P0_RTL3_83_MASK GENMASK(15, 8)
4438 #define B_P0_RTL3_82_MASK GENMASK(7, 0)
4442 #define B_P1_BACKOFF_IBADC_V1 GENMASK(31, 26)
4447 #define B_BK_FC0_INV_MSK_V1 GENMASK(18, 0)
4449 #define B_CCK_FC0_INV_MSK_V1 GENMASK(18, 0)
4451 #define B_PATH1_RXB_INIT_IDX_MSK_V1 GENMASK(14, 10)
4458 #define B_PATH0_RXBB_MSK_V1 GENMASK(31, 0)
4461 #define B_PATH1_RXBB_MSK_V1 GENMASK(31, 0)
4463 #define B_PATH0_BT_BACKOFF_V1 GENMASK(23, 0)
4465 #define B_PATH1_BT_BACKOFF_V1 GENMASK(23, 0)
4467 #define B_DCFO_COMP_S0_MSK_V2 GENMASK(13, 0)
4469 #define B_PATH0_TX_CFR_LGC1 GENMASK(19, 10)
4470 #define B_PATH0_TX_CFR_LGC0 GENMASK(9, 0)
4472 #define B_PATH0_TX_POLAR_CLIPPING_LGC1 GENMASK(19, 16)
4473 #define B_PATH0_TX_POLAR_CLIPPING_LGC0 GENMASK(15, 12)
4475 #define B_PATH0_FRC_FIR_TYPE_MSK_V1 GENMASK(1, 0)
4478 #define B_PATH0_NOTCH_VAL GENMASK(11, 0)
4481 #define B_PATH0_NOTCH2_VAL GENMASK(11, 0)
4487 #define B_PATH0_5MDET_TH GENMASK(5, 0)
4489 #define B_PATH1_FRC_FIR_TYPE_MSK_V1 GENMASK(1, 0)
4492 #define B_PATH1_NOTCH_VAL GENMASK(11, 0)
4495 #define B_PATH1_NOTCH2_VAL GENMASK(11, 0)
4501 #define B_PATH1_5MDET_TH GENMASK(5, 0)
4503 #define B_RPL_BIAS_COMP_MASK GENMASK(7, 0)
4505 #define B_RPL_PATHB_MASK GENMASK(23, 16)
4506 #define B_RPL_PATHA_MASK GENMASK(15, 8)
4508 #define B_RSSI_M_PATHB_MASK GENMASK(15, 8)
4509 #define B_RSSI_M_PATHA_MASK GENMASK(7, 0)
4511 #define B_FC0_MSK_V1 GENMASK(12, 0)
4515 #define B_DCFO_COMP_S0_V1_MSK GENMASK(13, 0)
4518 #define B_BMODE_PDTH_LOWER_BOUND_MSK_V1 GENMASK(31, 24)
4526 #define B_CFO_COMP_WEIGHT_MSK GENMASK(27, 24)
4527 #define B_CFO_COMP_VAL_MSK GENMASK(11, 0)
4531 #define B_P0_TSSI_ALIM1 GENMASK(29, 0)
4532 #define B_P0_TSSI_ALIM11 GENMASK(29, 20)
4533 #define B_P0_TSSI_ALIM12 GENMASK(19, 10)
4534 #define B_P0_TSSI_ALIM13 GENMASK(9, 0)
4536 #define B_P0_TSSI_ALIM31 GENMASK(9, 0)
4539 #define B_P0_TSSI_ALIM2 GENMASK(29, 0)
4544 #define B_ACK_VAL GENMASK(30, 29)
4550 #define B_TXPWRB_VAL GENMASK(27, 19)
4553 #define B_DPD_TSSI_CW GENMASK(26, 18)
4554 #define B_DPD_PWR_CW GENMASK(17, 9)
4555 #define B_DPD_REF GENMASK(8, 0)
4559 #define B_DPD_OFT_ADDR GENMASK(31, 27)
4563 #define B_P0_TMETER GENMASK(15, 10)
4570 #define B_P0_TSSI_RFC GENMASK(28, 27)
4572 #define B_P0_TSSI_OFT GENMASK(7, 0)
4575 #define B_P0_TSSI_AVG GENMASK(15, 12)
4578 #define B_P0_RFCTM_VAL GENMASK(25, 20)
4587 #define B_P0_TRSW_SO_A2 GENMASK(7, 5)
4594 #define B_P0_ANTSEL_TX_ORI GENMASK(15, 12)
4595 #define B_P0_ANTSEL_RX_ALT GENMASK(11, 8)
4596 #define B_P0_ANTSEL_RX_ORI GENMASK(7, 4)
4598 #define B_RFSW_CTRL_ANT_MAPPING GENMASK(15, 0)
4600 #define B_RFE_SEL0_SRC_MASK GENMASK(3, 0)
4608 #define B_P0_RFM_OUT GENMASK(4, 0)
4611 #define B_P0_TXDPD GENMASK(31, 28)
4616 #define B_P0_TSSI_MV_MIX GENMASK(19, 11)
4617 #define B_P0_TSSI_MV_AVG GENMASK(13, 11)
4621 #define B_TXGAIN_SCALE_OFT GENMASK(31, 24)
4624 #define B_S0_DACKI_AR GENMASK(31, 28)
4627 #define B_S0_DACKI2_K GENMASK(21, 12)
4629 #define B_S0_DACKI7_K GENMASK(15, 8)
4631 #define B_S0_DACKI8_K GENMASK(15, 8)
4633 #define B_S0_DACKQ_AR GENMASK(31, 28)
4636 #define B_S0_DACKQ2_K GENMASK(21, 12)
4638 #define B_S0_DACKQ7_K GENMASK(15, 8)
4640 #define B_S0_DACKQ8_K GENMASK(15, 8)
4642 #define B_RPL_BIAS_COMP1_MASK GENMASK(7, 0)
4644 #define B_P1_TSSI_ALIM1 GENMASK(29, 0)
4645 #define B_P1_TSSI_ALIM11 GENMASK(29, 20)
4646 #define B_P1_TSSI_ALIM12 GENMASK(19, 10)
4647 #define B_P1_TSSI_ALIM13 GENMASK(9, 0)
4649 #define B_P1_TSSI_ALIM31 GENMASK(9, 0)
4651 #define B_P1_TSSI_ALIM2 GENMASK(29, 0)
4655 #define B_P1_TMETER GENMASK(15, 10)
4660 #define B_P1_TSSI_RFC GENMASK(28, 27)
4662 #define B_P1_TSSI_OFT GENMASK(7, 0)
4665 #define B_P1_TSSI_AVG GENMASK(15, 12)
4668 #define B_P1_RFCTM_VAL GENMASK(25, 20)
4669 #define B_P1_RFCTM_DEL GENMASK(19, 11)
4675 #define B_P1_TSSI_MV_MIX GENMASK(19, 11)
4676 #define B_P1_TSSI_MV_AVG GENMASK(13, 11)
4680 #define B_S1_DACKI_AR GENMASK(31, 28)
4683 #define B_S1_DACKI2_K GENMASK(21, 12)
4685 #define B_S1_DACKI_K GENMASK(15, 8)
4687 #define B_S1_DACKI8_K GENMASK(15, 8)
4689 #define B_S1_DACKQ_AR GENMASK(31, 28)
4692 #define B_S1_DACKQ2_K GENMASK(21, 12)
4694 #define B_S1_DACKQ7_K GENMASK(15, 8)
4696 #define B_S1_DACKQ8_K GENMASK(15, 8)
4698 #define B_NCTL_CFG_SPAGE GENMASK(2, 1)
4702 #define B_NCTL_N1_CIP GENMASK(7, 0)
4706 #define B_IQK_DIF_TRX GENMASK(1, 0)
4708 #define B_IQK_DIF1_TXPI GENMASK(19, 0)
4710 #define B_IQK_DIF2_RXPI GENMASK(19, 0)
4712 #define B_IQK_DIF4_RXT GENMASK(27, 16)
4713 #define B_IQK_DIF4_TXT GENMASK(11, 0)
4716 #define B_IQK_CFG_SET GENMASK(5, 4)
4718 #define B_IQK_RXAGC GENMASK(15, 13)
4721 #define B_TPG_MOD_F GENMASK(2, 1)
4724 #define B_MDPK_SYNC_MAN GENMASK(31, 28)
4725 #define B_MDPK_SYNC_DMAN GENMASK(30, 28)
4729 #define B_KIP_MOD GENMASK(19, 0)
4734 #define B_DPK_IDL_SEL GENMASK(10, 9)
4738 #define B_LDL_NORM_PN GENMASK(12, 8)
4739 #define B_LDL_NORM_OP GENMASK(1, 0)
4743 #define B_DPK_CFG_IDX GENMASK(14, 12)
4748 #define B_KPATH_CFG_ED GENMASK(21, 20)
4750 #define B_KIP_RPT1_SEL GENMASK(21, 16)
4751 #define B_KIP_RPT1_SEL_V1 GENMASK(19, 16)
4770 #define B_PRT_COM_DCI GENMASK(27, 16)
4771 #define B_PRT_COM_CORV GENMASK(15, 8)
4772 #define B_RPT_COM_RDY GENMASK(15, 0)
4773 #define B_PRT_COM_DCQ GENMASK(11, 0)
4775 #define B_PRT_COM_GL GENMASK(7, 4)
4776 #define B_PRT_COM_CORI GENMASK(7, 0)
4777 #define B_PRT_COM_RXBB GENMASK(5, 0)
4778 #define B_PRT_COM_RXBB_V1 GENMASK(4, 0)
4786 #define B_IQK_RES_TXCFIR GENMASK(11, 8)
4787 #define B_IQK_RES_RXCFIR GENMASK(3, 0)
4792 #define B_RXIQC_NEWP GENMASK(19, 8)
4793 #define B_RXIQC_NEWX GENMASK(31, 20)
4798 #define B_RFGAIN_PAD GENMASK(4, 0)
4799 #define B_RFGAIN_TXBB GENMASK(12, 8)
4801 #define B_RFGAIN_BND GENMASK(4, 0)
4808 #define B_CFIR_LUT_GP_V1 GENMASK(2, 0)
4809 #define B_CFIR_LUT_GP GENMASK(1, 0)
4811 #define B_DPK_GN_EN GENMASK(17, 16)
4812 #define B_DPK_GN_AG GENMASK(9, 0)
4817 #define B_DPD_BND_1 GENMASK(24, 16)
4818 #define B_DPD_BND_0 GENMASK(8, 0)
4820 #define B_DPD_MEN GENMASK(31, 28)
4821 #define B_DPD_ORDER GENMASK(26, 24)
4822 #define B_DPD_ORDER_V1 GENMASK(26, 25)
4823 #define B_DPD_CFG GENMASK(22, 0)
4824 #define B_DPD_SEL GENMASK(13, 8)
4826 #define B_TXAGC_RFK_CH0 GENMASK(5, 0)
4830 #define B_KIP_IQP_SW GENMASK(13, 12)
4831 #define B_KIP_IQP_IQSW GENMASK(5, 0)
4833 #define B_KIP_RPT_SEL GENMASK(21, 16)
4837 #define B_LOAD_COEF_CFIR GENMASK(1, 0)
4841 #define B_DPK_GL_A0 GENMASK(31, 28)
4842 #define B_DPK_GL_A1 GENMASK(17, 0)
4844 #define B_RPT_PER_KSET GENMASK(31, 29)
4845 #define B_RPT_PER_TSSI GENMASK(28, 16)
4846 #define B_RPT_PER_OF GENMASK(15, 8)
4847 #define B_RPT_PER_TH GENMASK(5, 0)
4868 #define B_IQKINF_VER GENMASK(31, 24)
4869 #define B_IQKINF_FAIL_RXGRP GENMASK(23, 16)
4870 #define B_IQKINF_FAIL_TXGRP GENMASK(15, 8)
4871 #define B_IQKINF_FAIL GENMASK(3, 0)
4877 #define B_IQKCH_CH GENMASK(15, 8)
4878 #define B_IQKCH_BW GENMASK(7, 4)
4879 #define B_IQKCH_BAND GENMASK(3, 0)
4881 #define B_IQKINF2_FCNT GENMASK(23, 16)
4882 #define B_IQKINF2_KCNT GENMASK(15, 8)
4883 #define B_IQKINF2_NCTLV GENMASK(7, 0)
4886 #define B_DCOF0_V GENMASK(4, 1)
4891 #define B_DCOF8_V GENMASK(4, 1)
4897 #define B_DACK_BIAS00 GENMASK(11, 2)
4899 #define B_DACK_S0M0 GENMASK(31, 24)
4902 #define B_DACK_DADCK00 GENMASK(31, 24)
4906 #define B_DACK_BIAS01 GENMASK(11, 2)
4908 #define B_DACK_S0M1 GENMASK(31, 24)
4911 #define B_DACK_DADCK01 GENMASK(31, 24)
4915 #define B_DRCK_MUL GENMASK(21, 17)
4918 #define B_DRCK_VAL GENMASK(4, 0)
4920 #define B_DRCK_RES GENMASK(19, 15)
4925 #define B_DRCK_V1_CV GENMASK(4, 0)
4927 #define B_DRCK_RS_LPS GENMASK(19, 15)
4930 #define B_PATH0_SAMPL_DLY_T_MSK_V1 GENMASK(27, 26)
4932 #define B_P0_CFCH_BW0 GENMASK(27, 26)
4933 #define B_P0_CFCH_EN GENMASK(14, 11)
4934 #define B_P0_CFCH_CTL GENMASK(10, 7)
4937 #define B_P0_CFCH_BW1 GENMASK(8, 5)
4939 #define B_WDADC_SEL GENMASK(5, 4)
4941 #define B_ADCMOD_LP GENMASK(31, 16)
4943 #define B_DCIM_FR GENMASK(14, 13)
4945 #define B_ADDCK0D_VAL2 GENMASK(31, 26)
4946 #define B_ADDCK0D_VAL GENMASK(25, 16)
4951 #define B_ADDCK0 GENMASK(9, 8)
4952 #define B_ADDCK0_MAN GENMASK(5, 4)
4954 #define B_ADDCK0_VAL GENMASK(3, 0)
4957 #define B_ADDCK0_RLS GENMASK(29, 28)
4958 #define B_ADDCK0_RL1 GENMASK(27, 18)
4959 #define B_ADDCK0_RL0 GENMASK(17, 8)
4961 #define B_ADDCKR0_A0 GENMASK(19, 10)
4962 #define B_ADDCKR0_DC GENMASK(15, 4)
4963 #define B_ADDCKR0_A1 GENMASK(9, 0)
4965 #define B_DACK10 GENMASK(4, 1)
4969 #define B_DACK11 GENMASK(4, 1)
4973 #define B_DACK_BIAS10 GENMASK(11, 2)
4975 #define B_DACK10S GENMASK(31, 24)
4979 #define B_DACK_DADCK10 GENMASK(31, 24)
4983 #define B_DACK_BIAS11 GENMASK(11, 2)
4985 #define B_DACK11S GENMASK(31, 24)
4989 #define B_DACK_DADCK11 GENMASK(31, 24)
4991 #define B_PATH1_SAMPL_DLY_T_MSK_V1 GENMASK(27, 26)
4993 #define B_PATH0_BW_SEL_MSK_V1 GENMASK(8, 5)
4996 #define B_PATH1_BW_SEL_MSK_V1 GENMASK(8, 5)
4998 #define B_ADDCK1D_VAL2 GENMASK(31, 26)
4999 #define B_ADDCK1D_VAL GENMASK(25, 16)
5002 #define B_ADDCK1 GENMASK(9, 8)
5003 #define B_ADDCK1_MAN GENMASK(5, 4)
5007 #define B_ADDCK1_RLS GENMASK(29, 28)
5008 #define B_ADDCK1_RL1 GENMASK(27, 18)
5009 #define B_ADDCK1_RL0 GENMASK(17, 8)
5011 #define B_ADDCKR1_A0 GENMASK(19, 10)
5012 #define B_ADDCKR1_A1 GENMASK(9, 0)
5015 #define B_DACKN0_V GENMASK(21, 14)
5017 #define B_DACKN1_V GENMASK(21, 14)
5027 #define B_AX_WDT_COUNT_MASK GENMASK(15, 0)