Lines Matching refs:GENMASK
10 #define DATA_RATE_MODE_CTRL_MASK GENMASK(8, 7)
11 #define DATA_RATE_MODE_CTRL_MASK_V1 GENMASK(10, 8)
12 #define DATA_RATE_NOT_HT_IDX_MASK GENMASK(3, 0)
14 #define DATA_RATE_HT_IDX_MASK GENMASK(4, 0)
15 #define DATA_RATE_HT_IDX_MASK_V1 GENMASK(4, 0)
17 #define DATA_RATE_VHT_HE_NSS_MASK GENMASK(6, 4)
18 #define DATA_RATE_VHT_HE_IDX_MASK GENMASK(3, 0)
19 #define DATA_RATE_NSS_MASK_V1 GENMASK(7, 5)
20 #define DATA_RATE_MCS_MASK_V1 GENMASK(4, 0)
63 #define RTW89_TXWD_BODY0_WP_OFFSET GENMASK(31, 24)
64 #define RTW89_TXWD_BODY0_WP_OFFSET_V1 GENMASK(28, 24)
68 #define RTW89_TXWD_BODY0_CHANNEL_DMA GENMASK(19, 16)
69 #define RTW89_TXWD_BODY0_HDR_LLC_LEN GENMASK(15, 11)
72 #define RTW89_TXWD_BODY0_HW_SSN_SEL GENMASK(3, 2)
73 #define RTW89_TXWD_BODY0_HW_SSN_MODE GENMASK(1, 0)
76 #define RTW89_TXWD_BODY1_ADDR_INFO_NUM GENMASK(31, 26)
77 #define RTW89_TXWD_BODY1_PAYLOAD_ID GENMASK(31, 16)
78 #define RTW89_TXWD_BODY1_SEC_KEYID GENMASK(5, 4)
79 #define RTW89_TXWD_BODY1_SEC_TYPE GENMASK(3, 0)
82 #define RTW89_TXWD_BODY2_MACID GENMASK(30, 24)
84 #define RTW89_TXWD_BODY2_QSEL GENMASK(22, 17)
85 #define RTW89_TXWD_BODY2_TXPKT_SIZE GENMASK(13, 0)
90 #define RTW89_TXWD_BODY3_SW_SEQ GENMASK(11, 0)
93 #define RTW89_TXWD_BODY4_SEC_IV_L1 GENMASK(31, 24)
94 #define RTW89_TXWD_BODY4_SEC_IV_L0 GENMASK(23, 16)
97 #define RTW89_TXWD_BODY5_SEC_IV_H5 GENMASK(31, 24)
98 #define RTW89_TXWD_BODY5_SEC_IV_H4 GENMASK(23, 16)
99 #define RTW89_TXWD_BODY5_SEC_IV_H3 GENMASK(15, 8)
100 #define RTW89_TXWD_BODY5_SEC_IV_H2 GENMASK(7, 0)
106 #define RTW89_TXWD_BODY7_DATA_BW GENMASK(29, 28)
107 #define RTW89_TXWD_BODY7_GI_LTF GENMASK(27, 25)
108 #define RTW89_TXWD_BODY7_DATA_RATE GENMASK(24, 16)
112 #define RTW89_TXWD_INFO0_DATA_BW GENMASK(29, 28)
113 #define RTW89_TXWD_INFO0_GI_LTF GENMASK(27, 25)
114 #define RTW89_TXWD_INFO0_DATA_RATE GENMASK(24, 16)
118 #define RTW89_TXWD_INFO0_MULTIPORT_ID GENMASK(6, 4)
121 #define RTW89_TXWD_INFO1_DATA_RTY_LOWEST_RATE GENMASK(24, 16)
123 #define RTW89_TXWD_INFO1_MAX_AGGNUM GENMASK(7, 0)
126 #define RTW89_TXWD_INFO2_AMPDU_DENSITY GENMASK(20, 18)
127 #define RTW89_TXWD_INFO2_SEC_TYPE GENMASK(12, 9)
130 #define RTW89_TXWD_INFO2_SEC_CAM_IDX GENMASK(7, 0)
141 #define AX_RXD_RPKT_LEN_MASK GENMASK(13, 0)
142 #define AX_RXD_SHIFT_MASK GENMASK(15, 14)
143 #define AX_RXD_WL_HD_IV_LEN_MASK GENMASK(21, 16)
146 #define AX_RXD_RPKT_TYPE_MASK GENMASK(27, 24)
147 #define AX_RXD_DRV_INFO_SIZE_MASK GENMASK(30, 28)
151 #define AX_RXD_PPDU_TYPE_MASK GENMASK(3, 0)
152 #define AX_RXD_PPDU_CNT_MASK GENMASK(6, 4)
154 #define AX_RXD_USER_ID_MASK GENMASK(15, 8)
155 #define AX_RXD_USER_ID_v1_MASK GENMASK(13, 8)
156 #define AX_RXD_RX_DATARATE_MASK GENMASK(24, 16)
157 #define AX_RXD_RX_GI_LTF_MASK GENMASK(27, 25)
162 #define AX_RXD_BW_MASK GENMASK(31, 30)
163 #define AX_RXD_BW_v1_MASK GENMASK(31, 29)
166 #define AX_RXD_FREERUN_CNT_MASK GENMASK(31, 0)
183 #define AX_RXD_GET_CH_INFO_MASK GENMASK(15, 14)
184 #define AX_RXD_PATTERN_IDX_MASK GENMASK(20, 16)
185 #define AX_RXD_TARGET_IDC_MASK GENMASK(23, 21)
191 #define AX_RXD_TYPE_MASK GENMASK(1, 0)
198 #define AX_RXD_TID_MASK GENMASK(11, 8)
202 #define AX_RXD_SEQ_MASK GENMASK(27, 16)
203 #define AX_RXD_FRAG_MASK GENMASK(31, 28)
206 #define AX_RXD_SEC_CAM_IDX_MASK GENMASK(7, 0)
207 #define AX_RXD_ADDR_CAM_MASK GENMASK(15, 8)
208 #define AX_RXD_MAC_ID_MASK GENMASK(23, 16)
209 #define AX_RXD_RX_PL_ID_MASK GENMASK(27, 24)
215 #define AX_RXD_MAC_ADDR_MASK GENMASK(31, 0)
218 #define AX_RXD_MAC_ADDR_H_MASK GENMASK(15, 0)
220 #define AX_RXD_SEC_TYPE_MASK GENMASK(20, 17)
222 #define AX_RXD_HDR_OFFSET_MASK GENMASK(26, 22)
235 #define RTW89_RXINFO_USER_MACID GENMASK(15, 8)
243 #define RTW89_RXINFO_W0_USR_NUM GENMASK(3, 0)
244 #define RTW89_RXINFO_W0_FW_DEFINE GENMASK(15, 8)
245 #define RTW89_RXINFO_W0_LSIG_LEN GENMASK(27, 16)
248 #define RTW89_RXINFO_W0_LONG_RXD GENMASK(31, 30)
249 #define RTW89_RXINFO_W1_SERVICE GENMASK(15, 0)
250 #define RTW89_RXINFO_W1_PLCP_LEN GENMASK(23, 16)
257 #define RTW89_PHY_STS_HDR_W0_IE_MAP GENMASK(4, 0)
258 #define RTW89_PHY_STS_HDR_W0_LEN GENMASK(15, 8)
259 #define RTW89_PHY_STS_HDR_W0_RSSI_AVG GENMASK(31, 24)
260 #define RTW89_PHY_STS_HDR_W1_RSSI_A GENMASK(7, 0)
261 #define RTW89_PHY_STS_HDR_W1_RSSI_B GENMASK(15, 8)
262 #define RTW89_PHY_STS_HDR_W1_RSSI_C GENMASK(23, 16)
263 #define RTW89_PHY_STS_HDR_W1_RSSI_D GENMASK(31, 24)
269 #define RTW89_PHY_STS_IEHDR_TYPE GENMASK(4, 0)
270 #define RTW89_PHY_STS_IEHDR_LEN GENMASK(11, 5)
278 #define RTW89_PHY_STS_IE01_W0_CH_IDX GENMASK(23, 16)
279 #define RTW89_PHY_STS_IE01_W1_FD_CFO GENMASK(19, 8)
280 #define RTW89_PHY_STS_IE01_W1_PREMB_CFO GENMASK(31, 20)
281 #define RTW89_PHY_STS_IE01_W2_AVG_SNR GENMASK(5, 0)
282 #define RTW89_PHY_STS_IE01_W2_EVM_MAX GENMASK(15, 8)
283 #define RTW89_PHY_STS_IE01_W2_EVM_MIN GENMASK(23, 16)