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Searched refs:APBC_TWSI0 (Results 1 - 9 of 9) sorted by relevance

/kernel/linux/linux-6.6/drivers/clk/mmp/
H A Dclk-of-pxa168.c30 #define APBC_TWSI0 0x2c macro
163 {0, "twsi0_mux", twsi_parent_names, ARRAY_SIZE(twsi_parent_names), CLK_SET_RATE_PARENT, APBC_TWSI0, 4, 3, 0, &twsi0_lock},
182 {PXA168_CLK_TWSI0, "twsi0_clk", "twsi0_mux", CLK_SET_RATE_PARENT, APBC_TWSI0, 0x3, 0x3, 0x0, 0, &twsi0_lock},
H A Dclk-of-pxa910.c23 #define APBC_TWSI0 0x2c macro
141 {PXA910_CLK_TWSI0, "twsi0_clk", "pll1_13_1_5", CLK_SET_RATE_PARENT, APBC_TWSI0, 0x3, 0x3, 0x0, 0, &reset_lock},
H A Dclk-of-mmp2.c26 #define APBC_TWSI0 0x4 macro
251 {MMP2_CLK_TWSI0, "twsi0_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_TWSI0, 0x7, 0x3, 0x0, 0, &reset_lock},
/kernel/linux/linux-5.10/drivers/clk/mmp/
H A Dclk-pxa910.c24 #define APBC_TWSI0 0x2c macro
170 apbc_base + APBC_TWSI0, 10, 0, &clk_lock); in pxa910_clk_init()
H A Dclk-of-pxa168.c26 #define APBC_TWSI0 0x2c macro
143 {PXA168_CLK_TWSI0, "twsi0_clk", "pll1_13_1_5", CLK_SET_RATE_PARENT, APBC_TWSI0, 0x3, 0x3, 0x0, 0, &reset_lock},
H A Dclk-of-pxa910.c26 #define APBC_TWSI0 0x2c macro
142 {PXA910_CLK_TWSI0, "twsi0_clk", "pll1_13_1_5", CLK_SET_RATE_PARENT, APBC_TWSI0, 0x3, 0x3, 0x0, 0, &reset_lock},
H A Dclk-mmp2.c24 #define APBC_TWSI0 0x4 macro
194 apbc_base + APBC_TWSI0, 10, 0, &clk_lock); in mmp2_clk_init()
H A Dclk-pxa168.c24 #define APBC_TWSI0 0x2c macro
165 apbc_base + APBC_TWSI0, 10, 0, &clk_lock); in pxa168_clk_init()
H A Dclk-of-mmp2.c29 #define APBC_TWSI0 0x4 macro
252 {MMP2_CLK_TWSI0, "twsi0_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_TWSI0, 0x7, 0x3, 0x0, 0, &reset_lock},

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