| /kernel/linux/linux-5.10/drivers/clk/mmp/ |
| H A D | clk-pxa910.c | 34 #define APBC_SSP1 0x20 macro
251 apbc_base + APBC_SSP1, 4, 3, 0, &clk_lock); in pxa910_clk_init()
255 apbc_base + APBC_SSP1, 10, 0, &clk_lock); in pxa910_clk_init()
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| H A D | clk-of-pxa168.c | 37 #define APBC_SSP1 0x820 macro
135 {0, "ssp1_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP1, 4, 3, 0, &ssp1_lock},
157 {PXA168_CLK_SSP1, "ssp1_clk", "ssp1_mux", CLK_SET_RATE_PARENT, APBC_SSP1, 0x3, 0x3, 0x0, 0, &ssp1_lock},
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| H A D | clk-of-pxa910.c | 36 #define APBC_SSP1 0x20 macro
132 {0, "ssp1_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP1, 4, 3, 0, &ssp1_lock},
154 {PXA910_CLK_SSP1, "ssp1_clk", "ssp1_mux", CLK_SET_RATE_PARENT, APBC_SSP1, 0x3, 0x3, 0x0, 0, &ssp1_lock},
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| H A D | clk-mmp2.c | 41 #define APBC_SSP1 0x54 macro
302 apbc_base + APBC_SSP1, 4, 3, 0, &clk_lock); in mmp2_clk_init()
306 apbc_base + APBC_SSP1, 10, 0, &clk_lock); in mmp2_clk_init()
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| H A D | clk-pxa168.c | 34 #define APBC_SSP1 0x820 macro
246 apbc_base + APBC_SSP1, 4, 3, 0, &clk_lock); in pxa168_clk_init()
249 clk = mmp_clk_register_apbc("ssp1", "ssp1_mux", apbc_base + APBC_SSP1, in pxa168_clk_init()
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| H A D | clk-of-mmp2.c | 47 #define APBC_SSP1 0x54 macro
245 {0, "ssp1_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP1, 4, 3, 0, &ssp1_lock},
271 {MMP2_CLK_SSP1, "ssp1_clk", "ssp1_mux", CLK_SET_RATE_PARENT, APBC_SSP1, 0x7, 0x3, 0x0, 0, &ssp1_lock},
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| /kernel/linux/linux-6.6/drivers/clk/mmp/ |
| H A D | clk-of-pxa168.c | 40 #define APBC_SSP1 0x820 macro
174 {0, "ssp1_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP1, 4, 3, 0, &ssp1_lock},
195 {PXA168_CLK_SSP1, "ssp1_clk", "ssp1_mux", CLK_SET_RATE_PARENT, APBC_SSP1, 0x3, 0x3, 0x0, 0, &ssp1_lock},
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| H A D | clk-of-pxa910.c | 33 #define APBC_SSP1 0x20 macro
131 {0, "ssp1_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP1, 4, 3, 0, &ssp1_lock},
153 {PXA910_CLK_SSP1, "ssp1_clk", "ssp1_mux", CLK_SET_RATE_PARENT, APBC_SSP1, 0x3, 0x3, 0x0, 0, &ssp1_lock},
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| H A D | clk-of-mmp2.c | 44 #define APBC_SSP1 0x54 macro
244 {0, "ssp1_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP1, 4, 3, 0, &ssp1_lock},
270 {MMP2_CLK_SSP1, "ssp1_clk", "ssp1_mux", CLK_SET_RATE_PARENT, APBC_SSP1, 0x7, 0x3, 0x0, 0, &ssp1_lock},
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