Home
last modified time | relevance | path

Searched refs:control (Results 1 - 25 of 51) sorted by relevance

123

/device/soc/rockchip/common/sdk_linux/drivers/thermal/
H A Drockchip_thermal.c112 * @control: enable/disable method for the tsadc controller
134 void (*control)(void __iomem *reg, bool on); member
569 * (1) The tsadc control power sequence.
585 /* The tsadc control power sequence */ in rk_tsadcv3_initialize()
859 .control = rk_tsadcv3_control,
884 .control = rk_tsadcv3_control,
909 .control = rk_tsadcv2_control,
936 .control = rk_tsadcv3_control,
961 .control = rk_tsadcv3_control,
987 .control
[all...]
/device/soc/rockchip/common/sdk_linux/include/linux/usb/
H A Daudio-v2.h37 static inline bool uac_v2v3_control_is_readable(u32 bmControls, u8 control) in uac_v2v3_control_is_readable() argument
39 return (bmControls >> ((control - 1) * 0x2)) & 0x1; in uac_v2v3_control_is_readable()
42 static inline bool uac_v2v3_control_is_writeable(u32 bmControls, u8 control) in uac_v2v3_control_is_writeable() argument
44 return (bmControls >> ((control - 1) * 0x2)) & 0x2; in uac_v2v3_control_is_writeable()
H A Daudio.h37 struct list_head control; member
/device/soc/rockchip/common/kernel/drivers/net/wireless/rockchip_wlan/rkwifi/bcmdhd_wifi6/include/
H A Dnan.h68 /* Service Response Filter (SRF) control field masks */
86 #define NAN_ENTRY_CTRL_LEN 1 /* Entry control field length from FAM attribute */
285 map control:, bits:
321 entry control
334 /* Map control Field */
375 map control:, bits:
413 map control:, bits:
484 /* Ranging control flags */
548 #define NAN_DEFAULT_MAP_CTRL 0 /* nan default map control */
573 uint16 ctrl; /* attribute control */
1131 uint8 control; /* ndp control field */ global() member
1277 uint16 control; global() member
[all...]
/device/soc/rockchip/rk3568/hardware/omx_il/component/video/enc/
H A DRkvpu_OMX_Venc.c283 pVideoEnc->vpu_ctx->control(pVideoEnc->vpu_ctx, VPU_API_ENC_GETCFG, &preEncParam); in Rkvpu_Enc_ReConfig()
328 p_vpu_ctx->control(p_vpu_ctx, VPU_API_ENC_SETCFG, EncParam); in Rkvpu_Enc_ReConfig()
329 p_vpu_ctx->control(p_vpu_ctx, VPU_API_ENC_SETFORMAT, (void *)&encType); in Rkvpu_Enc_ReConfig()
410 pVideoEnc->vpu_ctx->control(pVideoEnc->vpu_ctx, VPU_API_ENC_SETFORMAT, (void *)&encType); in Rkvpu_ProcessStoreMetaData()
413 pVideoEnc->vpu_ctx->control(pVideoEnc->vpu_ctx, VPU_API_ENC_SETFORMAT, (void *)&encType); in Rkvpu_ProcessStoreMetaData()
492 pVideoEnc->vpu_ctx->control(pVideoEnc->vpu_ctx, VPU_API_ENC_SETFORMAT, (void *)&encType); in Rkvpu_ProcessStoreMetaData()
577 p_vpu_ctx->control(p_vpu_ctx, VPU_API_ENC_SETFORMAT, (void *)&encType); in Rkvpu_SendInputData()
579 p_vpu_ctx->control(p_vpu_ctx, VPU_API_ENC_GETCFG, (void*)&vpug); in Rkvpu_SendInputData()
583 p_vpu_ctx->control(p_vpu_ctx, VPU_API_ENC_SETCFG, (void*)&vpug); in Rkvpu_SendInputData()
586 p_vpu_ctx->control(p_vpu_ct in Rkvpu_SendInputData()
[all...]
/device/soc/hisilicon/common/platform/wifi/hi3881v100/driver/hcc/
H A Dhcc_hmac_if.h51 hcc_hmac_rx_control_event control; member
H A Dhcc_hmac.c88 if (g_s_handle.control == NULL) { in hcc_to_hmac_control_event_dispatch()
89 oam_warning_log0(0, 0, "hcc_to_hmac_control_event_dispatch: control is NULL"); in hcc_to_hmac_control_event_dispatch()
93 return g_s_handle.control(event_mem); in hcc_to_hmac_control_event_dispatch()
564 handle.control = hmac_from_dmac_rx_control_handle; in hcc_hmac_init()
/device/soc/rockchip/rk3588/hardware/mpp/src/
H A Dmpi_enc_utils.c285 /* jpeg use special codec config to control qtable */ in test_mpp_enc_cfg_setup()
343 ret = mpi->control(ctx, MPP_ENC_SET_CFG, cfg); in test_mpp_enc_cfg_setup()
345 mpp_err("mpi control enc set cfg failed ret %d\n", ret); in test_mpp_enc_cfg_setup()
351 ret = mpi->control(ctx, MPP_ENC_SET_SEI_CFG, &p->sei_mode); in test_mpp_enc_cfg_setup()
353 mpp_err("mpi control enc set sei cfg failed ret %d\n", ret); in test_mpp_enc_cfg_setup()
359 ret = mpi->control(ctx, MPP_ENC_SET_HEADER_MODE, &p->header_mode); in test_mpp_enc_cfg_setup()
361 mpp_err("mpi control enc set header mode failed ret %d\n", ret); in test_mpp_enc_cfg_setup()
379 ret = mpi->control(ctx, MPP_ENC_SET_REF_CFG, ref); in test_mpp_enc_cfg_setup()
381 mpp_err("mpi control enc set ref cfg failed ret %d\n", ret); in test_mpp_enc_cfg_setup()
410 mpp_err("mpi control en in hal_mpp_get_sps()
[all...]
/device/soc/rockchip/rk3568/hardware/codec/jpeg/src/
H A Dcodec_jpeg_decoder.cpp261 auto err = mpi_->control(mppCtx_, MPP_DEC_SET_OUTPUT_FORMAT, &format_); in SetFormat()
297 ret = mpi_->control(mppCtx_, MPP_SET_OUTPUT_TIMEOUT, &timeout); in PrePare()
302 ret = mpi_->control(mppCtx_, MPP_SET_INPUT_TIMEOUT, &timeout); in PrePare()
/device/soc/rockchip/rk3588/hardware/codec/jpeg/src/
H A Dcodec_jpeg_decoder.cpp306 auto err = mpi_->control(mppCtx_, MPP_DEC_SET_OUTPUT_FORMAT, &format_); in SetFormat()
342 ret = mpi_->control(mppCtx_, MPP_SET_OUTPUT_TIMEOUT, &timeout); in PrePare()
347 ret = mpi_->control(mppCtx_, MPP_SET_INPUT_TIMEOUT, &timeout); in PrePare()
/device/soc/rockchip/rk3588/kernel/drivers/pci/
H A Dpci.h190 u16 control; in pci_msi_set_enable() local
192 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control); in pci_msi_set_enable()
193 control &= ~PCI_MSI_FLAGS_ENABLE; in pci_msi_set_enable()
195 control |= PCI_MSI_FLAGS_ENABLE; in pci_msi_set_enable()
196 pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control); in pci_msi_set_enable()
/device/soc/rockchip/rk3399/hardware/mpp/src/
H A Dmpi_enc_utils.c511 /* jpeg use special codec config to control qtable */ in test_mpp_enc_cfg_setup()
570 ret = mpi->control(ctx, MPP_ENC_SET_CFG, cfg); in test_mpp_enc_cfg_setup()
572 mpp_err("mpi control enc set cfg failed ret %d\n", ret); in test_mpp_enc_cfg_setup()
578 ret = mpi->control(ctx, MPP_ENC_SET_SEI_CFG, &p->sei_mode); in test_mpp_enc_cfg_setup()
580 mpp_err("mpi control enc set sei cfg failed ret %d\n", ret); in test_mpp_enc_cfg_setup()
586 ret = mpi->control(ctx, MPP_ENC_SET_HEADER_MODE, &p->header_mode); in test_mpp_enc_cfg_setup()
588 mpp_err("mpi control enc set header mode failed ret %d\n", ret); in test_mpp_enc_cfg_setup()
606 ret = mpi->control(ctx, MPP_ENC_SET_REF_CFG, ref); in test_mpp_enc_cfg_setup()
608 mpp_err("mpi control enc set ref cfg failed ret %d\n", ret); in test_mpp_enc_cfg_setup()
670 mpp_err("mpi control en in hal_mpp_get_sps()
[all...]
/device/soc/rockchip/rk3568/hardware/mpp/src/
H A Dmpi_enc_utils.c503 /* jpeg use special codec config to control qtable */ in test_mpp_enc_cfg_setup()
562 ret = mpi->control(ctx, MPP_ENC_SET_CFG, cfg); in test_mpp_enc_cfg_setup()
564 mpp_err("mpi control enc set cfg failed ret %d\n", ret); in test_mpp_enc_cfg_setup()
570 ret = mpi->control(ctx, MPP_ENC_SET_SEI_CFG, &p->sei_mode); in test_mpp_enc_cfg_setup()
572 mpp_err("mpi control enc set sei cfg failed ret %d\n", ret); in test_mpp_enc_cfg_setup()
578 ret = mpi->control(ctx, MPP_ENC_SET_HEADER_MODE, &p->header_mode); in test_mpp_enc_cfg_setup()
580 mpp_err("mpi control enc set header mode failed ret %d\n", ret); in test_mpp_enc_cfg_setup()
598 ret = mpi->control(ctx, MPP_ENC_SET_REF_CFG, ref); in test_mpp_enc_cfg_setup()
600 mpp_err("mpi control enc set ref cfg failed ret %d\n", ret); in test_mpp_enc_cfg_setup()
662 mpp_err("mpi control en in hal_mpp_get_sps()
[all...]
/device/soc/rockchip/common/hardware/mpp/src/
H A Dmpi_enc_utils.c489 /* jpeg use special codec config to control qtable */ in test_mpp_enc_cfg_setup()
548 ret = mpi->control(ctx, MPP_ENC_SET_CFG, cfg); in test_mpp_enc_cfg_setup()
550 mpp_err("mpi control enc set cfg failed ret %d\n", ret); in test_mpp_enc_cfg_setup()
556 ret = mpi->control(ctx, MPP_ENC_SET_SEI_CFG, &p->sei_mode); in test_mpp_enc_cfg_setup()
558 mpp_err("mpi control enc set sei cfg failed ret %d\n", ret); in test_mpp_enc_cfg_setup()
564 ret = mpi->control(ctx, MPP_ENC_SET_HEADER_MODE, &p->header_mode); in test_mpp_enc_cfg_setup()
566 mpp_err("mpi control enc set header mode failed ret %d\n", ret); in test_mpp_enc_cfg_setup()
584 ret = mpi->control(ctx, MPP_ENC_SET_REF_CFG, ref); in test_mpp_enc_cfg_setup()
586 mpp_err("mpi control enc set ref cfg failed ret %d\n", ret); in test_mpp_enc_cfg_setup()
648 mpp_err("mpi control en in hal_mpp_get_sps()
[all...]
/device/soc/rockchip/rk3399/hardware/mpp/include/
H A Drk_mpi.h37 * and control api set
65 * (2). the control api set is for mpp context control including:
67 * control : similiar to ioctl in kernel driver, setup or get mpp internal parameter
187 // control interface
198 * @brief control function for mpp property setting
206 MPP_RET (*control)(MppCtx ctx, MpiCmd cmd, MppParam param); member
/device/soc/rockchip/rk3568/hardware/mpp/include/
H A Drk_mpi.h37 * and control api set
65 * (2). the control api set is for mpp context control including:
67 * control : similiar to ioctl in kernel driver, setup or get mpp internal parameter
187 // control interface
198 * @brief control function for mpp property setting
206 MPP_RET (*control)(MppCtx ctx, MpiCmd cmd, MppParam param); member
/device/soc/rockchip/rk3588/hardware/mpp/include/
H A Drk_mpi.h38 * and control api set
66 * (2). the control api set is for mpp context control including:
68 * control : similiar to ioctl in kernel driver, setup or get mpp internal parameter
188 // control interface
199 * @brief control function for mpp property setting
207 MPP_RET (*control)(MppCtx ctx, MpiCmd cmd, MppParam param); member
/device/soc/rockchip/common/hardware/mpp/include/
H A Drk_mpi.h37 * and control api set
65 * (2). the control api set is for mpp context control including:
67 * control : similiar to ioctl in kernel driver, setup or get mpp internal parameter
187 // control interface
198 * @brief control function for mpp property setting
206 MPP_RET (*control)(MppCtx ctx, MpiCmd cmd, MppParam param); member
/device/soc/rockchip/common/vendor/drivers/gpu/arm/midgard/
H A Dmali_kbase_device.c662 void kbase_set_profiling_control(struct kbase_device *kbdev, u32 control, u32 value) in kbase_set_profiling_control() argument
664 switch (control) { in kbase_set_profiling_control()
672 kbdev->kbase_profiling_controls[control] = value; in kbase_set_profiling_control()
675 dev_err(kbdev->dev, "Profiling control %d not found\n", control); in kbase_set_profiling_control()
681 * Called by gator to control the production of
/device/soc/rockchip/common/kernel/drivers/gpu/arm/midgard/
H A Dmali_kbase_device.c640 void kbase_set_profiling_control(struct kbase_device *kbdev, u32 control, u32 value) in kbase_set_profiling_control() argument
642 switch (control) { in kbase_set_profiling_control()
650 kbdev->kbase_profiling_controls[control] = value; in kbase_set_profiling_control()
653 dev_err(kbdev->dev, "Profiling control %d not found\n", control); in kbase_set_profiling_control()
659 * Called by gator to control the production of
/device/soc/rockchip/common/vendor/drivers/net/usb/
H A Dmeig_cdc_driver.c528 struct usb_interface *control; member
626 struct usb_interface *control; member
1567 * especially now that control transfers can be queued.
2006 control_if = ctx->control->cur_altsetting->desc.bInterfaceNumber; in cdc_ncm_config()
2846 * probes control interface, claims data interface, collects the bulk
2901 info->control = intf;
2930 /* we need a master/control interface (what we're
2934 info->control = usb_ifnum_to_if(dev->udev, info->u->bMasterInterface0);
2936 if (!info->control || !info->data) {
2937 dev_dbg(&intf->dev, "master #%u/%p slave #%u/%p\n", info->u->bMasterInterface0, info->control,
[all...]
/device/soc/rockchip/rk3568/hardware/codec/src/
H A Dhdi_mpp_config.c145 ret = pBaseComponent->mpi->control(ctx, MPP_ENC_GET_CFG, pBaseComponent->cfg); in GetDefaultConfig()
151 ret = pBaseComponent->mpi->control(ctx, MPP_DEC_GET_CFG, pBaseComponent->cfg); in GetDefaultConfig()
547 ret = pBaseComponent->mpi->control(pBaseComponent->ctx, MPP_ENC_SET_REF_CFG, ref); in SetGop()
549 HDF_LOGE("%{public}s: mpi control enc set ref cfg failed, ret %{public}d", __func__, ret); in SetGop()
628 ret = pBaseComponent->mpi->control(ctx, MPP_DEC_SET_CFG, pBaseComponent->cfg); in SetDecCfg()
806 ret = pBaseComponent->mpi->control(pBaseComponent->ctx, MPP_ENC_SET_CFG, pBaseComponent->cfg); in ValidateEncSetup()
808 HDF_LOGE("%{public}s: mpi control enc set cfg failed ret %{public}d", __func__, ret); in ValidateEncSetup()
814 ret = pBaseComponent->mpi->control(pBaseComponent->ctx, MPP_ENC_SET_SEI_CFG, &seiMode); in ValidateEncSetup()
816 HDF_LOGE("%{public}s: mpi control enc set sei cfg failed ret %{public}d", __func__, ret); in ValidateEncSetup()
822 ret = pBaseComponent->mpi->control(pBaseComponen in ValidateEncSetup()
[all...]
/device/soc/rockchip/rk3588/hardware/codec/src/
H A Dhdi_mpp_config.c145 ret = pBaseComponent->mpi->control(ctx, MPP_ENC_GET_CFG, pBaseComponent->cfg); in GetDefaultConfig()
151 ret = pBaseComponent->mpi->control(ctx, MPP_DEC_GET_CFG, pBaseComponent->cfg); in GetDefaultConfig()
547 ret = pBaseComponent->mpi->control(pBaseComponent->ctx, MPP_ENC_SET_REF_CFG, ref); in SetGop()
549 HDF_LOGE("%{public}s: mpi control enc set ref cfg failed, ret %{public}d", __func__, ret); in SetGop()
628 ret = pBaseComponent->mpi->control(ctx, MPP_DEC_SET_CFG, pBaseComponent->cfg); in SetDecCfg()
806 ret = pBaseComponent->mpi->control(pBaseComponent->ctx, MPP_ENC_SET_CFG, pBaseComponent->cfg); in ValidateEncSetup()
808 HDF_LOGE("%{public}s: mpi control enc set cfg failed ret %{public}d", __func__, ret); in ValidateEncSetup()
814 ret = pBaseComponent->mpi->control(pBaseComponent->ctx, MPP_ENC_SET_SEI_CFG, &seiMode); in ValidateEncSetup()
816 HDF_LOGE("%{public}s: mpi control enc set sei cfg failed ret %{public}d", __func__, ret); in ValidateEncSetup()
822 ret = pBaseComponent->mpi->control(pBaseComponen in ValidateEncSetup()
[all...]
/device/soc/rockchip/rk3568/hardware/mpp/mpp/legacy/
H A Dvpu_api_mlvec.cpp144 /* start control mpp */ in vpu_api_mlvec_set_st_cfg()
150 ret = mpi->control(mpp_ctx, MPP_ENC_SET_HEADER_MODE, &mode); in vpu_api_mlvec_set_st_cfg()
417 ret = mpi->control(mpp_ctx, MPP_ENC_SET_REF_CFG, ref); in vpu_api_mlvec_set_dy_max_tid()
419 HDF_LOGE("%s mpi control enc set ref cfg failed ret %d", __func__, ret); in vpu_api_mlvec_set_dy_max_tid()
423 ret = mpi->control(mpp_ctx, MPP_ENC_SET_REF_CFG, nullptr); in vpu_api_mlvec_set_dy_max_tid()
425 HDF_LOGE("%s mpi control enc set ref cfg failed ret %d", __func__, ret); in vpu_api_mlvec_set_dy_max_tid()
H A Dvpu_api.cpp197 return api->control(ctx, cmdType, param); in vpu_api_control()
384 s->control = vpu_api_control; in vpu_open_context()

Completed in 30 milliseconds

123