1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2014-2016, Fuzhou Rockchip Electronics Co., Ltd
4 * Caesar Wang <wxt@rock-chips.com>
5 */
6
7 #include <linux/clk.h>
8 #include <linux/delay.h>
9 #include <linux/interrupt.h>
10 #include <linux/io.h>
11 #include <linux/module.h>
12 #include <linux/of.h>
13 #include <linux/of_address.h>
14 #include <linux/of_irq.h>
15 #include <linux/platform_device.h>
16 #include <linux/regmap.h>
17 #include <linux/reset.h>
18 #include <linux/thermal.h>
19 #include <linux/mfd/syscon.h>
20 #include <linux/pinctrl/consumer.h>
21 #include <linux/nvmem-consumer.h>
22
23 #define ROCKCHIP_THERMAL_TWO 2
24 #define ROCKCHIP_THERMAL_EIGHT 8
25 #define ROCKCHIP_THERMAL_TEN 10
26 #define ROCKCHIP_THERMAL_FIFTEEN 15
27 #define ROCKCHIP_THERMAL_TWENTY 20
28 #define ROCKCHIP_THERMAL_THIRTYTWO 32
29 #define ROCKCHIP_THERMAL_NINETY 90
30 #define ROCKCHIP_THERMAL_ONEHUNDRED 100
31 #define ROCKCHIP_THERMAL_TWOHUNDRED 200
32 #define ROCKCHIP_THERMAL_FIVEHUNDRED 500
33 #define ROCKCHIP_THERMAL_ONETHOUSAND 1000
34 #define ROCKCHIP_THERMAL_TENTHOUSAND 10000
35 #define ROCKCHIP_THERMAL_NINETYFIVETHOUSAND 95000
36
37 /*
38 * If the temperature over a period of time High,
39 * the resulting TSHUT gave CRU module,let it reset the entire chip,
40 * or via GPIO give PMIC.
41 */
42 enum tshut_mode {
43 TSHUT_MODE_CRU = 0,
44 TSHUT_MODE_OTP,
45 };
46
47 /*
48 * The system Temperature Sensors tshut(tshut) polarity
49 * the bit 8 is tshut polarity.
50 * 0: low active, 1: high active
51 */
52 enum tshut_polarity {
53 TSHUT_LOW_ACTIVE = 0,
54 TSHUT_HIGH_ACTIVE,
55 };
56
57 /*
58 * The system has two Temperature Sensors.
59 * sensor0 is for CPU, and sensor1 is for GPU.
60 */
61 enum sensor_id {
62 SENSOR_CPU = 0,
63 SENSOR_GPU,
64 };
65
66 /*
67 * The conversion table has the adc value and temperature.
68 * ADC_DECREMENT: the adc value is of diminishing.(e.g. rk3288_code_table)
69 * ADC_INCREMENT: the adc value is incremental.(e.g. rk3368_code_table)
70 */
71 enum adc_sort_mode {
72 ADC_DECREMENT = 0,
73 ADC_INCREMENT,
74 };
75
76 #include "thermal_hwmon.h"
77
78 /**
79 * The max sensors is two in rockchip SoCs.
80 * Two sensors: CPU and GPU sensor.
81 */
82 #define SOC_MAX_SENSORS 2
83
84 /**
85 * struct chip_tsadc_table - hold information about chip-specific differences
86 * @id: conversion table
87 * @length: size of conversion table
88 * @data_mask: mask to apply on data inputs
89 * @kNum: linear parameter k
90 * @bNum: linear parameter b
91 * @mode: sort mode of this adc variant (incrementing or decrementing)
92 */
93 struct chip_tsadc_table {
94 const struct tsadc_table *id;
95 unsigned int length;
96 u32 data_mask;
97 /* Tsadc is linear, using linear parameters */
98 int kNum;
99 int bNum;
100 enum adc_sort_mode mode;
101 };
102
103 /**
104 * struct rockchip_tsadc_chip - hold the private data of tsadc chip
105 * @chn_id: array of sensor ids of chip corresponding to the channel
106 * @chn_num: the channel number of tsadc chip
107 * @tshut_temp: the hardware-controlled shutdown temperature value
108 * @tshut_mode: the hardware-controlled shutdown mode (0:CRU 1:GPIO)
109 * @tshut_polarity: the hardware-controlled active polarity (0:LOW 1:HIGH)
110 * @initialize: SoC special initialize tsadc controller method
111 * @irq_ack: clear the interrupt
112 * @control: enable/disable method for the tsadc controller
113 * @get_temp: get the temperature
114 * @set_alarm_temp: set the high temperature interrupt
115 * @set_tshut_temp: set the hardware-controlled shutdown temperature
116 * @set_tshut_mode: set the hardware-controlled shutdown mode
117 * @get_trim_code: get the trim code by otp value
118 * @trim_temp: get trim temp by trim code
119 * @table: the chip-specific conversion table
120 */
121 struct rockchip_tsadc_chip {
122 /* The sensor id of chip correspond to the ADC channel */
123 int chn_id[SOC_MAX_SENSORS];
124 int chn_num;
125
126 /* The hardware-controlled tshut property */
127 int tshut_temp;
128 enum tshut_mode tshut_mode;
129 enum tshut_polarity tshut_polarity;
130
131 /* Chip-wide methods */
132 void (*initialize)(struct regmap *grf, void __iomem *reg, enum tshut_polarity p);
133 void (*irq_ack)(void __iomem *reg);
134 void (*control)(void __iomem *reg, bool on);
135
136 /* Per-sensor methods */
137 int (*get_temp)(const struct chip_tsadc_table *table, int chn, void __iomem *reg, int *temp);
138 int (*set_alarm_temp)(const struct chip_tsadc_table *table, int chn, void __iomem *reg, int temp);
139 int (*set_tshut_temp)(const struct chip_tsadc_table *table, int chn, void __iomem *reg, int temp);
140 void (*set_tshut_mode)(struct regmap *grf, int chn, void __iomem *reg, enum tshut_mode m);
141 int (*get_trim_code)(struct platform_device *pdev, int code, int trim_base);
142 int (*trim_temp)(struct platform_device *pdev);
143
144 /* Per-table methods */
145 struct chip_tsadc_table table;
146 };
147
148 /**
149 * struct rockchip_thermal_sensor - hold the information of thermal sensor
150 * @thermal: pointer to the platform/configuration data
151 * @tzd: pointer to a thermal zone
152 * @id: identifier of the thermal sensor
153 */
154 struct rockchip_thermal_sensor {
155 struct rockchip_thermal_data *thermal;
156 struct thermal_zone_device *tzd;
157 int id;
158 };
159
160 /**
161 * struct rockchip_thermal_data - hold the private data of thermal driver
162 * @chip: pointer to the platform/configuration data
163 * @pdev: platform device of thermal
164 * @reset: the reset controller of tsadc
165 * @sensors: array of thermal sensors
166 * @clk: the bulk clk of tsadc, include controller clock and peripherals bus clock
167 * @num_clks: the number of tsadc clks
168 * @grf: the general register file will be used to do static set by software
169 * @regs: the base address of tsadc controller
170 * @tshut_temp: the hardware-controlled shutdown temperature value
171 * @trim: trimmed value
172 * @tshut_mode: the hardware-controlled shutdown mode (0:CRU 1:GPIO)
173 * @tshut_polarity: the hardware-controlled active polarity (0:LOW 1:HIGH)
174 * @pinctrl: the pinctrl of tsadc
175 * @gpio_state: pinctrl select gpio function
176 * @otp_state: pinctrl select otp out function
177 * @panic_nb: panic notifier block
178 */
179 struct rockchip_thermal_data {
180 const struct rockchip_tsadc_chip *chip;
181 struct platform_device *pdev;
182 struct reset_control *reset;
183
184 struct rockchip_thermal_sensor sensors[SOC_MAX_SENSORS];
185
186 struct clk_bulk_data *clks;
187 int num_clks;
188
189 struct regmap *grf;
190 void __iomem *regs;
191
192 int tshut_temp;
193 int trim;
194 enum tshut_mode tshut_mode;
195 enum tshut_polarity tshut_polarity;
196 struct pinctrl *pinctrl;
197 struct pinctrl_state *gpio_state;
198 struct pinctrl_state *otp_state;
199
200 struct notifier_block panic_nb;
201 };
202
203 /**
204 * TSADC Sensor Register description:
205 *
206 * TSADCV2_* are used for RK3288 SoCs, the other chips can reuse it.
207 * TSADCV3_* are used for newer SoCs than RK3288. (e.g: RK3228, RK3399)
208 *
209 */
210 #define TSADCV2_USER_CON 0x00
211 #define TSADCV2_AUTO_CON 0x04
212 #define TSADCV2_INT_EN 0x08
213 #define TSADCV2_INT_PD 0x0c
214 #define TSADCV2_DATA(chn) (0x20 + (chn)*0x04)
215 #define TSADCV2_COMP_INT(chn) (0x30 + (chn)*0x04)
216 #define TSADCV2_COMP_SHUT(chn) (0x40 + (chn)*0x04)
217 #define TSADCV2_HIGHT_INT_DEBOUNCE 0x60
218 #define TSADCV2_HIGHT_TSHUT_DEBOUNCE 0x64
219 #define TSADCV2_AUTO_PERIOD 0x68
220 #define TSADCV2_AUTO_PERIOD_HT 0x6c
221
222 #define TSADCV2_AUTO_EN BIT(0)
223 #define TSADCV2_AUTO_SRC_EN(chn) BIT(4 + (chn))
224 #define TSADCV2_AUTO_TSHUT_POLARITY_HIGH BIT(8)
225
226 #define TSADCV3_AUTO_Q_SEL_EN BIT(1)
227
228 #define TSADCV2_INT_SRC_EN(chn) BIT(chn)
229 #define TSADCV2_SHUT_2GPIO_SRC_EN(chn) BIT(4 + (chn))
230 #define TSADCV2_SHUT_2CRU_SRC_EN(chn) BIT(8 + (chn))
231
232 #define TSADCV2_INT_PD_CLEAR_MASK ~BIT(8)
233 #define TSADCV3_INT_PD_CLEAR_MASK ~BIT(16)
234
235 #define TSADCV2_DATA_MASK 0xfff
236 #define TSADCV3_DATA_MASK 0x3ff
237
238 #define TSADCV2_HIGHT_INT_DEBOUNCE_COUNT 4
239 #define TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT 4
240 #define TSADCV2_AUTO_PERIOD_TIME 250 /* 250ms */
241 #define TSADCV2_AUTO_PERIOD_HT_TIME 50 /* 50ms */
242 #define TSADCV3_AUTO_PERIOD_TIME 1875 /* 2.5ms */
243 #define TSADCV3_AUTO_PERIOD_HT_TIME 1875 /* 2.5ms */
244 #define TSADCV5_AUTO_PERIOD_TIME 1622 /* 2.5ms */
245 #define TSADCV5_AUTO_PERIOD_HT_TIME 1622 /* 2.5ms */
246
247 #define TSADCV2_USER_INTER_PD_SOC 0x340 /* 13 clocks */
248 #define TSADCV5_USER_INTER_PD_SOC 0xfc0 /* 97us, at least 90us */
249
250 #define GRF_SARADC_TESTBIT 0x0e644
251 #define GRF_TSADC_TESTBIT_L 0x0e648
252 #define GRF_TSADC_TESTBIT_H 0x0e64c
253
254 #define PX30_GRF_SOC_CON2 0x0408
255
256 #define RK1808_BUS_GRF_SOC_CON0 0x0400
257
258 #define RK3568_GRF_TSADC_CON 0x0600
259 #define RK3568_GRF_TSADC_ANA_REG0 (0x10001 << 0)
260 #define RK3568_GRF_TSADC_ANA_REG1 (0x10001 << 1)
261 #define RK3568_GRF_TSADC_ANA_REG2 (0x10001 << 2)
262 #define RK3568_GRF_TSADC_TSEN (0x10001 << 8)
263
264 #define RV1126_GRF0_TSADC_CON 0x0100
265
266 #define RV1126_GRF0_TSADC_TRM (0xff0077 << 0)
267 #define RV1126_GRF0_TSADC_SHUT_2CRU (0x30003 << 10)
268 #define RV1126_GRF0_TSADC_SHUT_2GPIO (0x70007 << 12)
269
270 #define GRF_SARADC_TESTBIT_ON (0x10001 << 2)
271 #define GRF_TSADC_TESTBIT_H_ON (0x10001 << 2)
272 #define GRF_TSADC_BANDGAP_CHOPPER_EN (0x10001 << 2)
273 #define GRF_TSADC_VCM_EN_L (0x10001 << 7)
274 #define GRF_TSADC_VCM_EN_H (0x10001 << 7)
275
276 #define GRF_CON_TSADC_CH_INV (0x10001 << 1)
277
278 #define MIN_TEMP (-40000)
279 #define LOWEST_TEMP (-273000)
280 #define MAX_TEMP (125000)
281 #define MAX_ENV_TEMP (85000)
282
283 /**
284 * struct tsadc_table - code to temperature conversion table
285 * @code: the value of adc channel
286 * @temp: the temperature
287 * Note:
288 * code to temperature mapping of the temperature sensor is a piece wise linear
289 * curve.Any temperature, code faling between to 2 give temperatures can be
290 * linearly interpolated.
291 * Code to Temperature mapping should be updated based on manufacturer results.
292 */
293 struct tsadc_table {
294 u32 code;
295 int temp;
296 };
297
298 static const struct tsadc_table rv1108_table[] = {
299 {0, -40000}, {374, -40000}, {382, -35000}, {389, -30000}, {397, -25000}, {405, -20000},
300 {413, -15000}, {421, -10000}, {429, -5000}, {436, 0}, {444, 5000}, {452, 10000},
301 {460, 15000}, {468, 20000}, {476, 25000}, {483, 30000}, {491, 35000}, {499, 40000},
302 {507, 45000}, {515, 50000}, {523, 55000}, {531, 60000}, {539, 65000}, {547, 70000},
303 {555, 75000}, {562, 80000}, {570, 85000}, {578, 90000}, {586, 95000}, {594, 100000},
304 {602, 105000}, {610, 110000}, {618, 115000}, {626, 120000}, {634, 125000}, {TSADCV2_DATA_MASK, 125000},
305 };
306
307 static const struct tsadc_table rk1808_code_table[] = {
308 {0, -40000}, {3455, -40000}, {3463, -35000}, {3471, -30000}, {3479, -25000}, {3487, -20000},
309 {3495, -15000}, {3503, -10000}, {3511, -5000}, {3519, 0}, {3527, 5000}, {3535, 10000},
310 {3543, 15000}, {3551, 20000}, {3559, 25000}, {3567, 30000}, {3576, 35000}, {3584, 40000},
311 {3592, 45000}, {3600, 50000}, {3609, 55000}, {3617, 60000}, {3625, 65000}, {3633, 70000},
312 {3642, 75000}, {3650, 80000}, {3659, 85000}, {3667, 90000}, {3675, 95000}, {3684, 100000},
313 {3692, 105000}, {3701, 110000}, {3709, 115000}, {3718, 120000}, {3726, 125000}, {TSADCV2_DATA_MASK, 125000},
314 };
315
316 static const struct tsadc_table rk3228_code_table[] = {
317 {0, -40000}, {588, -40000}, {593, -35000}, {598, -30000}, {603, -25000}, {608, -20000},
318 {613, -15000}, {618, -10000}, {623, -5000}, {629, 0}, {634, 5000}, {639, 10000},
319 {644, 15000}, {649, 20000}, {654, 25000}, {660, 30000}, {665, 35000}, {670, 40000},
320 {675, 45000}, {681, 50000}, {686, 55000}, {691, 60000}, {696, 65000}, {702, 70000},
321 {707, 75000}, {712, 80000}, {717, 85000}, {723, 90000}, {728, 95000}, {733, 100000},
322 {738, 105000}, {744, 110000}, {749, 115000}, {754, 120000}, {760, 125000}, {TSADCV2_DATA_MASK, 125000},
323 };
324
325 static const struct tsadc_table rk3288_code_table[] = {
326 {TSADCV2_DATA_MASK, -40000},
327 {3800, -40000},
328 {3792, -35000},
329 {3783, -30000},
330 {3774, -25000},
331 {3765, -20000},
332 {3756, -15000},
333 {3747, -10000},
334 {3737, -5000},
335 {3728, 0},
336 {3718, 5000},
337 {3708, 10000},
338 {3698, 15000},
339 {3688, 20000},
340 {3678, 25000},
341 {3667, 30000},
342 {3656, 35000},
343 {3645, 40000},
344 {3634, 45000},
345 {3623, 50000},
346 {3611, 55000},
347 {3600, 60000},
348 {3588, 65000},
349 {3575, 70000},
350 {3563, 75000},
351 {3550, 80000},
352 {3537, 85000},
353 {3524, 90000},
354 {3510, 95000},
355 {3496, 100000},
356 {3482, 105000},
357 {3467, 110000},
358 {3452, 115000},
359 {3437, 120000},
360 {3421, 125000},
361 {0, 125000},
362 };
363
364 static const struct tsadc_table rk3328_code_table[] = {
365 {0, -40000}, {296, -40000}, {304, -35000}, {313, -30000}, {331, -20000},
366 {340, -15000}, {349, -10000}, {359, -5000}, {368, 0}, {378, 5000},
367 {388, 10000}, {398, 15000}, {408, 20000}, {418, 25000}, {429, 30000},
368 {440, 35000}, {451, 40000}, {462, 45000}, {473, 50000}, {485, 55000},
369 {496, 60000}, {508, 65000}, {521, 70000}, {533, 75000}, {546, 80000},
370 {559, 85000}, {572, 90000}, {586, 95000}, {600, 100000}, {614, 105000},
371 {629, 110000}, {644, 115000}, {659, 120000}, {675, 125000}, {TSADCV2_DATA_MASK, 125000},
372 };
373
374 static const struct tsadc_table rk3368_code_table[] = {
375 {0, -40000}, {106, -40000}, {108, -35000}, {110, -30000}, {112, -25000}, {114, -20000},
376 {116, -15000}, {118, -10000}, {120, -5000}, {122, 0}, {124, 5000}, {126, 10000},
377 {128, 15000}, {130, 20000}, {132, 25000}, {134, 30000}, {136, 35000}, {138, 40000},
378 {140, 45000}, {142, 50000}, {144, 55000}, {146, 60000}, {148, 65000}, {150, 70000},
379 {152, 75000}, {154, 80000}, {156, 85000}, {158, 90000}, {160, 95000}, {162, 100000},
380 {163, 105000}, {165, 110000}, {167, 115000}, {169, 120000}, {171, 125000}, {TSADCV3_DATA_MASK, 125000},
381 };
382
383 static const struct tsadc_table rk3399_code_table[] = {
384 {0, -40000}, {402, -40000}, {410, -35000}, {419, -30000}, {427, -25000}, {436, -20000},
385 {444, -15000}, {453, -10000}, {461, -5000}, {470, 0}, {478, 5000}, {487, 10000},
386 {496, 15000}, {504, 20000}, {513, 25000}, {521, 30000}, {530, 35000}, {538, 40000},
387 {547, 45000}, {555, 50000}, {564, 55000}, {573, 60000}, {581, 65000}, {590, 70000},
388 {599, 75000}, {607, 80000}, {616, 85000}, {624, 90000}, {633, 95000}, {642, 100000},
389 {650, 105000}, {659, 110000}, {668, 115000}, {677, 120000}, {685, 125000}, {TSADCV3_DATA_MASK, 125000},
390 };
391
392 static const struct tsadc_table rk3568_code_table[] = {
393 {0, -40000}, {1584, -40000}, {1620, -35000}, {1652, -30000}, {1688, -25000}, {1720, -20000},
394 {1756, -15000}, {1788, -10000}, {1824, -5000}, {1856, 0}, {1892, 5000}, {1924, 10000},
395 {1956, 15000}, {1992, 20000}, {2024, 25000}, {2060, 30000}, {2092, 35000}, {2128, 40000},
396 {2160, 45000}, {2196, 50000}, {2228, 55000}, {2264, 60000}, {2300, 65000}, {2332, 70000},
397 {2368, 75000}, {2400, 80000}, {2436, 85000}, {2468, 90000}, {2500, 95000}, {2536, 100000},
398 {2572, 105000}, {2604, 110000}, {2636, 115000}, {2672, 120000}, {2704, 125000}, {TSADCV2_DATA_MASK, 125000},
399 };
400
rk_tsadcv2_temp_to_code(const struct chip_tsadc_table *table, int temp)401 static u32 rk_tsadcv2_temp_to_code(const struct chip_tsadc_table *table, int temp)
402 {
403 int high, low, mid;
404 unsigned long num;
405 unsigned int denom;
406 u32 error = table->data_mask;
407
408 if (table->kNum) {
409 return (((temp / ROCKCHIP_THERMAL_ONETHOUSAND) * table->kNum) / ROCKCHIP_THERMAL_ONETHOUSAND + table->bNum);
410 }
411
412 low = 0;
413 high = (table->length - 1) - 1; /* ignore the last check for table */
414 mid = (high + low) / ROCKCHIP_THERMAL_TWO;
415
416 /* Return mask code data when the temp is over table range */
417 if (temp < table->id[low].temp || temp > table->id[high].temp) {
418 goto exit;
419 }
420
421 while (low <= high) {
422 if (temp == table->id[mid].temp) {
423 return table->id[mid].code;
424 } else if (temp < table->id[mid].temp) {
425 high = mid - 1;
426 } else {
427 low = mid + 1;
428 }
429 mid = (low + high) / ROCKCHIP_THERMAL_TWO;
430 }
431
432 /*
433 * The conversion code granularity provided by the table. Let's
434 * assume that the relationship between temperature and
435 * analog value between 2 table entries is linear and interpolate
436 * to produce less granular result.
437 */
438 num = abs(table->id[mid + 1].code - table->id[mid].code);
439 num *= temp - table->id[mid].temp;
440 denom = table->id[mid + 1].temp - table->id[mid].temp;
441
442 switch (table->mode) {
443 case ADC_DECREMENT:
444 return table->id[mid].code - (num / denom);
445 case ADC_INCREMENT:
446 return table->id[mid].code + (num / denom);
447 default:
448 pr_err("%s: unknown table mode: %d\n", __func__, table->mode);
449 return error;
450 }
451
452 exit:
453 pr_err("%s: invalid temperature, temp=%d error=%d\n", __func__, temp, error);
454 return error;
455 }
456
rk_tsadcv2_code_to_temp(const struct chip_tsadc_table *table, u32 code, int *temp)457 static int rk_tsadcv2_code_to_temp(const struct chip_tsadc_table *table, u32 code, int *temp)
458 {
459 unsigned int low = 1;
460 unsigned int high = table->length - 1;
461 unsigned int mid = (low + high) / ROCKCHIP_THERMAL_TWO;
462 unsigned int num;
463 unsigned long denom;
464
465 if (table->kNum) {
466 *temp = (((int)code - table->bNum) * ROCKCHIP_THERMAL_TENTHOUSAND / table->kNum) * ROCKCHIP_THERMAL_ONEHUNDRED;
467 if (*temp < MIN_TEMP || *temp > MAX_TEMP) {
468 return -EAGAIN;
469 }
470 return 0;
471 }
472
473 WARN_ON(table->length < ROCKCHIP_THERMAL_TWO);
474
475 switch (table->mode) {
476 case ADC_DECREMENT:
477 code &= table->data_mask;
478 if (code <= table->id[high].code) {
479 return -EAGAIN; /* Incorrect reading */
480 }
481
482 while (low <= high) {
483 if (code >= table->id[mid].code && code < table->id[mid - 1].code) {
484 break;
485 } else if (code < table->id[mid].code) {
486 low = mid + 1;
487 } else {
488 high = mid - 1;
489 }
490
491 mid = (low + high) / ROCKCHIP_THERMAL_TWO;
492 }
493 break;
494 case ADC_INCREMENT:
495 code &= table->data_mask;
496 if (code < table->id[low].code) {
497 return -EAGAIN; /* Incorrect reading */
498 }
499
500 while (low <= high) {
501 if (code <= table->id[mid].code && code > table->id[mid - 1].code) {
502 break;
503 } else if (code > table->id[mid].code) {
504 low = mid + 1;
505 } else {
506 high = mid - 1;
507 }
508
509 mid = (low + high) / ROCKCHIP_THERMAL_TWO;
510 }
511 break;
512 default:
513 pr_err("%s: unknown table mode: %d\n", __func__, table->mode);
514 return -EINVAL;
515 }
516
517 /*
518 * The 5C granularity provided by the table is too much. Let's
519 * assume that the relationship between sensor readings and
520 * temperature between 2 table entries is linear and interpolate
521 * to produce less granular result.
522 */
523 num = table->id[mid].temp - table->id[mid - 1].temp;
524 num *= abs(table->id[mid - 1].code - code);
525 denom = abs(table->id[mid - 1].code - table->id[mid].code);
526 *temp = table->id[mid - 1].temp + (num / denom);
527
528 return 0;
529 }
530
531 /**
532 * rk_tsadcv2_initialize - initialize TASDC Controller.
533 * @grf: the general register file will be used to do static set by software
534 * @regs: the base address of tsadc controller
535 * @tshut_polarity: the hardware-controlled active polarity (0:LOW 1:HIGH)
536 *
537 * (1) Set TSADC_V2_AUTO_PERIOD:
538 * Configure the interleave between every two accessing of
539 * TSADC in normal operation.
540 *
541 * (2) Set TSADCV2_AUTO_PERIOD_HT:
542 * Configure the interleave between every two accessing of
543 * TSADC after the temperature is higher than COM_SHUT or COM_INT.
544 *
545 * (3) Set TSADCV2_HIGH_INT_DEBOUNCE and TSADC_HIGHT_TSHUT_DEBOUNCE:
546 * If the temperature is higher than COMP_INT or COMP_SHUT for
547 * "debounce" times, TSADC controller will generate interrupt or TSHUT.
548 */
rk_tsadcv2_initialize(struct regmap *grf, void __iomem *regs, enum tshut_polarity tshut_polarity)549 static void rk_tsadcv2_initialize(struct regmap *grf, void __iomem *regs, enum tshut_polarity tshut_polarity)
550 {
551 if (tshut_polarity == TSHUT_HIGH_ACTIVE) {
552 writel_relaxed(0U | TSADCV2_AUTO_TSHUT_POLARITY_HIGH, regs + TSADCV2_AUTO_CON);
553 } else {
554 writel_relaxed(0U & ~TSADCV2_AUTO_TSHUT_POLARITY_HIGH, regs + TSADCV2_AUTO_CON);
555 }
556
557 writel_relaxed(TSADCV2_AUTO_PERIOD_TIME, regs + TSADCV2_AUTO_PERIOD);
558 writel_relaxed(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT, regs + TSADCV2_HIGHT_INT_DEBOUNCE);
559 writel_relaxed(TSADCV2_AUTO_PERIOD_HT_TIME, regs + TSADCV2_AUTO_PERIOD_HT);
560 writel_relaxed(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT, regs + TSADCV2_HIGHT_TSHUT_DEBOUNCE);
561 }
562
563 /**
564 * rk_tsadcv3_initialize - initialize TASDC Controller.
565 * @grf: the general register file will be used to do static set by software
566 * @regs: the base address of tsadc controller
567 * @tshut_polarity: the hardware-controlled active polarity (0:LOW 1:HIGH)
568 *
569 * (1) The tsadc control power sequence.
570 *
571 * (2) Set TSADC_V2_AUTO_PERIOD:
572 * Configure the interleave between every two accessing of
573 * TSADC in normal operation.
574 *
575 * (2) Set TSADCV2_AUTO_PERIOD_HT:
576 * Configure the interleave between every two accessing of
577 * TSADC after the temperature is higher than COM_SHUT or COM_INT.
578 *
579 * (3) Set TSADCV2_HIGH_INT_DEBOUNCE and TSADC_HIGHT_TSHUT_DEBOUNCE:
580 * If the temperature is higher than COMP_INT or COMP_SHUT for
581 * "debounce" times, TSADC controller will generate interrupt or TSHUT.
582 */
rk_tsadcv3_initialize(struct regmap *grf, void __iomem *regs, enum tshut_polarity tshut_polarity)583 static void rk_tsadcv3_initialize(struct regmap *grf, void __iomem *regs, enum tshut_polarity tshut_polarity)
584 {
585 /* The tsadc control power sequence */
586 if (IS_ERR(grf)) {
587 /* Set interleave value to workround ic time sync issue */
588 writel_relaxed(TSADCV2_USER_INTER_PD_SOC, regs + TSADCV2_USER_CON);
589
590 writel_relaxed(TSADCV2_AUTO_PERIOD_TIME, regs + TSADCV2_AUTO_PERIOD);
591 writel_relaxed(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT, regs + TSADCV2_HIGHT_INT_DEBOUNCE);
592 writel_relaxed(TSADCV2_AUTO_PERIOD_HT_TIME, regs + TSADCV2_AUTO_PERIOD_HT);
593 writel_relaxed(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT, regs + TSADCV2_HIGHT_TSHUT_DEBOUNCE);
594
595 } else {
596 /* Enable the voltage common mode feature */
597 regmap_write(grf, GRF_TSADC_TESTBIT_L, GRF_TSADC_VCM_EN_L);
598 regmap_write(grf, GRF_TSADC_TESTBIT_H, GRF_TSADC_VCM_EN_H);
599
600 usleep_range(ROCKCHIP_THERMAL_FIFTEEN, ROCKCHIP_THERMAL_ONEHUNDRED); /* The spec note says at least 15 us */
601 regmap_write(grf, GRF_SARADC_TESTBIT, GRF_SARADC_TESTBIT_ON);
602 regmap_write(grf, GRF_TSADC_TESTBIT_H, GRF_TSADC_TESTBIT_H_ON);
603 usleep_range(ROCKCHIP_THERMAL_NINETY, ROCKCHIP_THERMAL_TWOHUNDRED); /* The spec note says at least 90 us */
604
605 writel_relaxed(TSADCV3_AUTO_PERIOD_TIME, regs + TSADCV2_AUTO_PERIOD);
606 writel_relaxed(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT, regs + TSADCV2_HIGHT_INT_DEBOUNCE);
607 writel_relaxed(TSADCV3_AUTO_PERIOD_HT_TIME, regs + TSADCV2_AUTO_PERIOD_HT);
608 writel_relaxed(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT, regs + TSADCV2_HIGHT_TSHUT_DEBOUNCE);
609 }
610
611 if (tshut_polarity == TSHUT_HIGH_ACTIVE) {
612 writel_relaxed(0U | TSADCV2_AUTO_TSHUT_POLARITY_HIGH, regs + TSADCV2_AUTO_CON);
613 } else {
614 writel_relaxed(0U & ~TSADCV2_AUTO_TSHUT_POLARITY_HIGH, regs + TSADCV2_AUTO_CON);
615 }
616 }
617
rk_tsadcv4_initialize(struct regmap *grf, void __iomem *regs, enum tshut_polarity tshut_polarity)618 static void rk_tsadcv4_initialize(struct regmap *grf, void __iomem *regs, enum tshut_polarity tshut_polarity)
619 {
620 rk_tsadcv2_initialize(grf, regs, tshut_polarity);
621 regmap_write(grf, PX30_GRF_SOC_CON2, GRF_CON_TSADC_CH_INV);
622 }
623
rk_tsadcv5_initialize(struct regmap *grf, void __iomem *regs, enum tshut_polarity tshut_polarity)624 static void rk_tsadcv5_initialize(struct regmap *grf, void __iomem *regs, enum tshut_polarity tshut_polarity)
625 {
626 if (tshut_polarity == TSHUT_HIGH_ACTIVE) {
627 writel_relaxed(0U | TSADCV2_AUTO_TSHUT_POLARITY_HIGH, regs + TSADCV2_AUTO_CON);
628 } else {
629 writel_relaxed(0U & ~TSADCV2_AUTO_TSHUT_POLARITY_HIGH, regs + TSADCV2_AUTO_CON);
630 }
631
632 writel_relaxed(TSADCV5_USER_INTER_PD_SOC, regs + TSADCV2_USER_CON);
633
634 writel_relaxed(TSADCV5_AUTO_PERIOD_TIME, regs + TSADCV2_AUTO_PERIOD);
635 writel_relaxed(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT, regs + TSADCV2_HIGHT_INT_DEBOUNCE);
636 writel_relaxed(TSADCV5_AUTO_PERIOD_HT_TIME, regs + TSADCV2_AUTO_PERIOD_HT);
637 writel_relaxed(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT, regs + TSADCV2_HIGHT_TSHUT_DEBOUNCE);
638
639 if (!IS_ERR(grf)) {
640 regmap_write(grf, RK1808_BUS_GRF_SOC_CON0, GRF_TSADC_BANDGAP_CHOPPER_EN);
641 }
642 }
643
rk_tsadcv6_initialize(struct regmap *grf, void __iomem *regs, enum tshut_polarity tshut_polarity)644 static void rk_tsadcv6_initialize(struct regmap *grf, void __iomem *regs, enum tshut_polarity tshut_polarity)
645 {
646 rk_tsadcv2_initialize(grf, regs, tshut_polarity);
647
648 if (!IS_ERR(grf)) {
649 regmap_write(grf, RV1126_GRF0_TSADC_CON, RV1126_GRF0_TSADC_TRM);
650 }
651 }
652
rk_tsadcv7_initialize(struct regmap *grf, void __iomem *regs, enum tshut_polarity tshut_polarity)653 static void rk_tsadcv7_initialize(struct regmap *grf, void __iomem *regs, enum tshut_polarity tshut_polarity)
654 {
655 writel_relaxed(TSADCV5_USER_INTER_PD_SOC, regs + TSADCV2_USER_CON);
656 writel_relaxed(TSADCV5_AUTO_PERIOD_TIME, regs + TSADCV2_AUTO_PERIOD);
657 writel_relaxed(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT, regs + TSADCV2_HIGHT_INT_DEBOUNCE);
658 writel_relaxed(TSADCV5_AUTO_PERIOD_HT_TIME, regs + TSADCV2_AUTO_PERIOD_HT);
659 writel_relaxed(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT, regs + TSADCV2_HIGHT_TSHUT_DEBOUNCE);
660
661 if (tshut_polarity == TSHUT_HIGH_ACTIVE) {
662 writel_relaxed(0U | TSADCV2_AUTO_TSHUT_POLARITY_HIGH, regs + TSADCV2_AUTO_CON);
663 } else {
664 writel_relaxed(0U & ~TSADCV2_AUTO_TSHUT_POLARITY_HIGH, regs + TSADCV2_AUTO_CON);
665 }
666
667 if (!IS_ERR(grf)) {
668 regmap_write(grf, RK3568_GRF_TSADC_CON, RK3568_GRF_TSADC_TSEN);
669 udelay(ROCKCHIP_THERMAL_FIFTEEN);
670 regmap_write(grf, RK3568_GRF_TSADC_CON, RK3568_GRF_TSADC_ANA_REG0);
671 regmap_write(grf, RK3568_GRF_TSADC_CON, RK3568_GRF_TSADC_ANA_REG1);
672 regmap_write(grf, RK3568_GRF_TSADC_CON, RK3568_GRF_TSADC_ANA_REG2);
673 usleep_range(ROCKCHIP_THERMAL_ONEHUNDRED, ROCKCHIP_THERMAL_TWOHUNDRED);
674 }
675 }
676
rk_tsadcv2_irq_ack(void __iomem *regs)677 static void rk_tsadcv2_irq_ack(void __iomem *regs)
678 {
679 u32 val;
680
681 val = readl_relaxed(regs + TSADCV2_INT_PD);
682 writel_relaxed(val & TSADCV2_INT_PD_CLEAR_MASK, regs + TSADCV2_INT_PD);
683 }
684
rk_tsadcv3_irq_ack(void __iomem *regs)685 static void rk_tsadcv3_irq_ack(void __iomem *regs)
686 {
687 u32 val;
688
689 val = readl_relaxed(regs + TSADCV2_INT_PD);
690 writel_relaxed(val & TSADCV3_INT_PD_CLEAR_MASK, regs + TSADCV2_INT_PD);
691 }
692
rk_tsadcv2_control(void __iomem *regs, bool enable)693 static void rk_tsadcv2_control(void __iomem *regs, bool enable)
694 {
695 u32 val;
696
697 val = readl_relaxed(regs + TSADCV2_AUTO_CON);
698 if (enable) {
699 val |= TSADCV2_AUTO_EN;
700 } else {
701 val &= ~TSADCV2_AUTO_EN;
702 }
703
704 writel_relaxed(val, regs + TSADCV2_AUTO_CON);
705 }
706
707 /**
708 * rk_tsadcv3_control - the tsadc controller is enabled or disabled.
709 * @regs: the base address of tsadc controller
710 * @enable: boolean flag to enable the controller
711 *
712 * NOTE: TSADC controller works at auto mode, and some SoCs need set the
713 * tsadc_q_sel bit on TSADCV2_AUTO_CON[1]. The (1024 - tsadc_q) as output
714 * adc value if setting this bit to enable.
715 */
rk_tsadcv3_control(void __iomem *regs, bool enable)716 static void rk_tsadcv3_control(void __iomem *regs, bool enable)
717 {
718 u32 val;
719
720 val = readl_relaxed(regs + TSADCV2_AUTO_CON);
721 if (enable) {
722 val |= TSADCV2_AUTO_EN | TSADCV3_AUTO_Q_SEL_EN;
723 } else {
724 val &= ~TSADCV2_AUTO_EN;
725 }
726
727 writel_relaxed(val, regs + TSADCV2_AUTO_CON);
728 }
729
rk_tsadcv2_get_temp(const struct chip_tsadc_table *table, int chn, void __iomem *regs, int *temp)730 static int rk_tsadcv2_get_temp(const struct chip_tsadc_table *table, int chn, void __iomem *regs, int *temp)
731 {
732 u32 val;
733
734 val = readl_relaxed(regs + TSADCV2_DATA(chn));
735
736 return rk_tsadcv2_code_to_temp(table, val, temp);
737 }
738
rk_tsadcv2_alarm_temp(const struct chip_tsadc_table *table, int chn, void __iomem *regs, int temp)739 static int rk_tsadcv2_alarm_temp(const struct chip_tsadc_table *table, int chn, void __iomem *regs, int temp)
740 {
741 u32 alarm_value;
742 u32 int_en, int_clr;
743
744 /*
745 * In some cases, some sensors didn't need the trip points, the
746 * set_trips will pass {-INT_MAX, INT_MAX} to trigger tsadc alarm
747 * in the end, ignore this case and disable the high temperature
748 * interrupt.
749 */
750 if (temp == INT_MAX) {
751 int_clr = readl_relaxed(regs + TSADCV2_INT_EN);
752 int_clr &= ~TSADCV2_INT_SRC_EN(chn);
753 writel_relaxed(int_clr, regs + TSADCV2_INT_EN);
754 return 0;
755 }
756
757 /* Make sure the value is valid */
758 alarm_value = rk_tsadcv2_temp_to_code(table, temp);
759 if (alarm_value == table->data_mask) {
760 return -ERANGE;
761 }
762
763 writel_relaxed(alarm_value & table->data_mask, regs + TSADCV2_COMP_INT(chn));
764
765 int_en = readl_relaxed(regs + TSADCV2_INT_EN);
766 int_en |= TSADCV2_INT_SRC_EN(chn);
767 writel_relaxed(int_en, regs + TSADCV2_INT_EN);
768
769 return 0;
770 }
771
rk_tsadcv2_tshut_temp(const struct chip_tsadc_table *table, int chn, void __iomem *regs, int temp)772 static int rk_tsadcv2_tshut_temp(const struct chip_tsadc_table *table, int chn, void __iomem *regs, int temp)
773 {
774 u32 tshut_value, val;
775
776 /* Make sure the value is valid */
777 tshut_value = rk_tsadcv2_temp_to_code(table, temp);
778 if (tshut_value == table->data_mask) {
779 return -ERANGE;
780 }
781
782 writel_relaxed(tshut_value, regs + TSADCV2_COMP_SHUT(chn));
783
784 /* TSHUT will be valid */
785 val = readl_relaxed(regs + TSADCV2_AUTO_CON);
786 writel_relaxed(val | TSADCV2_AUTO_SRC_EN(chn), regs + TSADCV2_AUTO_CON);
787
788 return 0;
789 }
790
rk_tsadcv2_tshut_mode(struct regmap *grf, int chn, void __iomem *regs, enum tshut_mode mode)791 static void rk_tsadcv2_tshut_mode(struct regmap *grf, int chn, void __iomem *regs, enum tshut_mode mode)
792 {
793 u32 val;
794
795 val = readl_relaxed(regs + TSADCV2_INT_EN);
796 if (mode == TSHUT_MODE_OTP) {
797 val &= ~TSADCV2_SHUT_2CRU_SRC_EN(chn);
798 val |= TSADCV2_SHUT_2GPIO_SRC_EN(chn);
799 } else {
800 val &= ~TSADCV2_SHUT_2GPIO_SRC_EN(chn);
801 val |= TSADCV2_SHUT_2CRU_SRC_EN(chn);
802 }
803
804 writel_relaxed(val, regs + TSADCV2_INT_EN);
805 }
806
rk_tsadcv3_tshut_mode(struct regmap *grf, int chn, void __iomem *regs, enum tshut_mode mode)807 static void rk_tsadcv3_tshut_mode(struct regmap *grf, int chn, void __iomem *regs, enum tshut_mode mode)
808 {
809 u32 val;
810
811 val = readl_relaxed(regs + TSADCV2_INT_EN);
812 if (mode == TSHUT_MODE_OTP) {
813 val &= ~TSADCV2_SHUT_2CRU_SRC_EN(chn);
814 val |= TSADCV2_SHUT_2GPIO_SRC_EN(chn);
815 if (!IS_ERR(grf)) {
816 regmap_write(grf, RV1126_GRF0_TSADC_CON, RV1126_GRF0_TSADC_SHUT_2GPIO);
817 }
818 } else {
819 val &= ~TSADCV2_SHUT_2GPIO_SRC_EN(chn);
820 val |= TSADCV2_SHUT_2CRU_SRC_EN(chn);
821 if (!IS_ERR(grf)) {
822 regmap_write(grf, RV1126_GRF0_TSADC_CON, RV1126_GRF0_TSADC_SHUT_2CRU);
823 }
824 }
825
826 writel_relaxed(val, regs + TSADCV2_INT_EN);
827 }
828
rk_tsadcv1_get_trim_code(struct platform_device *pdev, int code, int trim_base)829 static int rk_tsadcv1_get_trim_code(struct platform_device *pdev, int code, int trim_base)
830 {
831 struct rockchip_thermal_data *thermal = platform_get_drvdata(pdev);
832 const struct chip_tsadc_table *table = &thermal->chip->table;
833 u32 base_code;
834 int trim_code;
835
836 base_code = trim_base * table->kNum / ROCKCHIP_THERMAL_ONETHOUSAND + table->bNum;
837 trim_code = code - base_code - ROCKCHIP_THERMAL_TEN;
838
839 return trim_code;
840 }
841
rk_tsadcv1_trim_temp(struct platform_device *pdev)842 static int rk_tsadcv1_trim_temp(struct platform_device *pdev)
843 {
844 struct rockchip_thermal_data *thermal = platform_get_drvdata(pdev);
845
846 return thermal->trim * ROCKCHIP_THERMAL_FIVEHUNDRED;
847 }
848
849 static const struct rockchip_tsadc_chip px30_tsadc_data = {
850 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
851 .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */
852 .chn_num = ROCKCHIP_THERMAL_TWO, /* 2 channels for tsadc */
853
854 .tshut_mode = TSHUT_MODE_CRU, /* default TSHUT via CRU */
855 .tshut_temp = ROCKCHIP_THERMAL_NINETYFIVETHOUSAND,
856
857 .initialize = rk_tsadcv4_initialize,
858 .irq_ack = rk_tsadcv3_irq_ack,
859 .control = rk_tsadcv3_control,
860 .get_temp = rk_tsadcv2_get_temp,
861 .set_alarm_temp = rk_tsadcv2_alarm_temp,
862 .set_tshut_temp = rk_tsadcv2_tshut_temp,
863 .set_tshut_mode = rk_tsadcv2_tshut_mode,
864
865 .table =
866 {
867 .id = rk3328_code_table,
868 .length = ARRAY_SIZE(rk3328_code_table),
869 .data_mask = TSADCV2_DATA_MASK,
870 .mode = ADC_INCREMENT,
871 },
872 };
873
874 static const struct rockchip_tsadc_chip rv1108_tsadc_data = {
875 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
876 .chn_num = 1, /* one channel for tsadc */
877
878 .tshut_mode = TSHUT_MODE_OTP, /* default TSHUT via GPIO give PMIC */
879 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
880 .tshut_temp = ROCKCHIP_THERMAL_NINETYFIVETHOUSAND,
881
882 .initialize = rk_tsadcv2_initialize,
883 .irq_ack = rk_tsadcv3_irq_ack,
884 .control = rk_tsadcv3_control,
885 .get_temp = rk_tsadcv2_get_temp,
886 .set_alarm_temp = rk_tsadcv2_alarm_temp,
887 .set_tshut_temp = rk_tsadcv2_tshut_temp,
888 .set_tshut_mode = rk_tsadcv2_tshut_mode,
889
890 .table =
891 {
892 .id = rv1108_table,
893 .length = ARRAY_SIZE(rv1108_table),
894 .data_mask = TSADCV2_DATA_MASK,
895 .mode = ADC_INCREMENT,
896 },
897 };
898
899 static const struct rockchip_tsadc_chip rv1126_tsadc_data = {
900 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
901 .chn_num = 1, /* one channel for tsadc */
902
903 .tshut_mode = TSHUT_MODE_CRU, /* default TSHUT via CRU */
904 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
905 .tshut_temp = ROCKCHIP_THERMAL_NINETYFIVETHOUSAND,
906
907 .initialize = rk_tsadcv6_initialize,
908 .irq_ack = rk_tsadcv3_irq_ack,
909 .control = rk_tsadcv2_control,
910 .get_temp = rk_tsadcv2_get_temp,
911 .set_alarm_temp = rk_tsadcv2_alarm_temp,
912 .set_tshut_temp = rk_tsadcv2_tshut_temp,
913 .set_tshut_mode = rk_tsadcv3_tshut_mode,
914 .get_trim_code = rk_tsadcv1_get_trim_code,
915 .trim_temp = rk_tsadcv1_trim_temp,
916
917 .table =
918 {
919 .kNum = 2263,
920 .bNum = 2704,
921 .data_mask = TSADCV2_DATA_MASK,
922 .mode = ADC_INCREMENT,
923 },
924 };
925
926 static const struct rockchip_tsadc_chip rk1808_tsadc_data = {
927 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
928 .chn_num = 1, /* one channel for tsadc */
929
930 .tshut_mode = TSHUT_MODE_OTP, /* default TSHUT via GPIO give PMIC */
931 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
932 .tshut_temp = ROCKCHIP_THERMAL_NINETYFIVETHOUSAND,
933
934 .initialize = rk_tsadcv5_initialize,
935 .irq_ack = rk_tsadcv3_irq_ack,
936 .control = rk_tsadcv3_control,
937 .get_temp = rk_tsadcv2_get_temp,
938 .set_alarm_temp = rk_tsadcv2_alarm_temp,
939 .set_tshut_temp = rk_tsadcv2_tshut_temp,
940 .set_tshut_mode = rk_tsadcv2_tshut_mode,
941
942 .table =
943 {
944 .id = rk1808_code_table,
945 .length = ARRAY_SIZE(rk1808_code_table),
946 .data_mask = TSADCV2_DATA_MASK,
947 .mode = ADC_INCREMENT,
948 },
949 };
950
951 static const struct rockchip_tsadc_chip rk3228_tsadc_data = {
952 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
953 .chn_num = 1, /* one channel for tsadc */
954
955 .tshut_mode = TSHUT_MODE_OTP, /* default TSHUT via GPIO give PMIC */
956 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
957 .tshut_temp = ROCKCHIP_THERMAL_NINETYFIVETHOUSAND,
958
959 .initialize = rk_tsadcv2_initialize,
960 .irq_ack = rk_tsadcv3_irq_ack,
961 .control = rk_tsadcv3_control,
962 .get_temp = rk_tsadcv2_get_temp,
963 .set_alarm_temp = rk_tsadcv2_alarm_temp,
964 .set_tshut_temp = rk_tsadcv2_tshut_temp,
965 .set_tshut_mode = rk_tsadcv2_tshut_mode,
966
967 .table =
968 {
969 .id = rk3228_code_table,
970 .length = ARRAY_SIZE(rk3228_code_table),
971 .data_mask = TSADCV3_DATA_MASK,
972 .mode = ADC_INCREMENT,
973 },
974 };
975
976 static const struct rockchip_tsadc_chip rk3288_tsadc_data = {
977 .chn_id[SENSOR_CPU] = 1, /* cpu sensor is channel 1 */
978 .chn_id[SENSOR_GPU] = ROCKCHIP_THERMAL_TWO, /* gpu sensor is channel 2 */
979 .chn_num = ROCKCHIP_THERMAL_TWO, /* two channels for tsadc */
980
981 .tshut_mode = TSHUT_MODE_OTP, /* default TSHUT via GPIO give PMIC */
982 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
983 .tshut_temp = ROCKCHIP_THERMAL_NINETYFIVETHOUSAND,
984
985 .initialize = rk_tsadcv2_initialize,
986 .irq_ack = rk_tsadcv2_irq_ack,
987 .control = rk_tsadcv2_control,
988 .get_temp = rk_tsadcv2_get_temp,
989 .set_alarm_temp = rk_tsadcv2_alarm_temp,
990 .set_tshut_temp = rk_tsadcv2_tshut_temp,
991 .set_tshut_mode = rk_tsadcv2_tshut_mode,
992
993 .table =
994 {
995 .id = rk3288_code_table,
996 .length = ARRAY_SIZE(rk3288_code_table),
997 .data_mask = TSADCV2_DATA_MASK,
998 .mode = ADC_DECREMENT,
999 },
1000 };
1001
1002 static const struct rockchip_tsadc_chip rk3328_tsadc_data = {
1003 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
1004 .chn_num = 1, /* one channels for tsadc */
1005
1006 .tshut_mode = TSHUT_MODE_CRU, /* default TSHUT via CRU */
1007 .tshut_temp = ROCKCHIP_THERMAL_NINETYFIVETHOUSAND,
1008
1009 .initialize = rk_tsadcv2_initialize,
1010 .irq_ack = rk_tsadcv3_irq_ack,
1011 .control = rk_tsadcv3_control,
1012 .get_temp = rk_tsadcv2_get_temp,
1013 .set_alarm_temp = rk_tsadcv2_alarm_temp,
1014 .set_tshut_temp = rk_tsadcv2_tshut_temp,
1015 .set_tshut_mode = rk_tsadcv2_tshut_mode,
1016
1017 .table =
1018 {
1019 .id = rk3328_code_table,
1020 .length = ARRAY_SIZE(rk3328_code_table),
1021 .data_mask = TSADCV2_DATA_MASK,
1022 .mode = ADC_INCREMENT,
1023 },
1024 };
1025
1026 static const struct rockchip_tsadc_chip rk3366_tsadc_data = {
1027 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
1028 .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */
1029 .chn_num = ROCKCHIP_THERMAL_TWO, /* two channels for tsadc */
1030
1031 .tshut_mode = TSHUT_MODE_OTP, /* default TSHUT via GPIO give PMIC */
1032 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
1033 .tshut_temp = ROCKCHIP_THERMAL_NINETYFIVETHOUSAND,
1034
1035 .initialize = rk_tsadcv3_initialize,
1036 .irq_ack = rk_tsadcv3_irq_ack,
1037 .control = rk_tsadcv3_control,
1038 .get_temp = rk_tsadcv2_get_temp,
1039 .set_alarm_temp = rk_tsadcv2_alarm_temp,
1040 .set_tshut_temp = rk_tsadcv2_tshut_temp,
1041 .set_tshut_mode = rk_tsadcv2_tshut_mode,
1042
1043 .table =
1044 {
1045 .id = rk3228_code_table,
1046 .length = ARRAY_SIZE(rk3228_code_table),
1047 .data_mask = TSADCV3_DATA_MASK,
1048 .mode = ADC_INCREMENT,
1049 },
1050 };
1051
1052 static const struct rockchip_tsadc_chip rk3368_tsadc_data = {
1053 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
1054 .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */
1055 .chn_num = ROCKCHIP_THERMAL_TWO, /* two channels for tsadc */
1056
1057 .tshut_mode = TSHUT_MODE_OTP, /* default TSHUT via GPIO give PMIC */
1058 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
1059 .tshut_temp = ROCKCHIP_THERMAL_NINETYFIVETHOUSAND,
1060
1061 .initialize = rk_tsadcv2_initialize,
1062 .irq_ack = rk_tsadcv2_irq_ack,
1063 .control = rk_tsadcv2_control,
1064 .get_temp = rk_tsadcv2_get_temp,
1065 .set_alarm_temp = rk_tsadcv2_alarm_temp,
1066 .set_tshut_temp = rk_tsadcv2_tshut_temp,
1067 .set_tshut_mode = rk_tsadcv2_tshut_mode,
1068
1069 .table =
1070 {
1071 .id = rk3368_code_table,
1072 .length = ARRAY_SIZE(rk3368_code_table),
1073 .data_mask = TSADCV3_DATA_MASK,
1074 .mode = ADC_INCREMENT,
1075 },
1076 };
1077
1078 static const struct rockchip_tsadc_chip rk3399_tsadc_data = {
1079 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
1080 .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */
1081 .chn_num = ROCKCHIP_THERMAL_TWO, /* two channels for tsadc */
1082
1083 .tshut_mode = TSHUT_MODE_OTP, /* default TSHUT via GPIO give PMIC */
1084 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
1085 .tshut_temp = ROCKCHIP_THERMAL_NINETYFIVETHOUSAND,
1086
1087 .initialize = rk_tsadcv3_initialize,
1088 .irq_ack = rk_tsadcv3_irq_ack,
1089 .control = rk_tsadcv3_control,
1090 .get_temp = rk_tsadcv2_get_temp,
1091 .set_alarm_temp = rk_tsadcv2_alarm_temp,
1092 .set_tshut_temp = rk_tsadcv2_tshut_temp,
1093 .set_tshut_mode = rk_tsadcv2_tshut_mode,
1094
1095 .table =
1096 {
1097 .id = rk3399_code_table,
1098 .length = ARRAY_SIZE(rk3399_code_table),
1099 .data_mask = TSADCV3_DATA_MASK,
1100 .mode = ADC_INCREMENT,
1101 },
1102 };
1103
1104 static const struct rockchip_tsadc_chip rk3568_tsadc_data = {
1105 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
1106 .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */
1107 .chn_num = ROCKCHIP_THERMAL_TWO, /* two channels for tsadc */
1108
1109 .tshut_mode = TSHUT_MODE_OTP, /* default TSHUT via GPIO give PMIC */
1110 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
1111 .tshut_temp = ROCKCHIP_THERMAL_NINETYFIVETHOUSAND,
1112
1113 .initialize = rk_tsadcv7_initialize,
1114 .irq_ack = rk_tsadcv3_irq_ack,
1115 .control = rk_tsadcv3_control,
1116 .get_temp = rk_tsadcv2_get_temp,
1117 .set_alarm_temp = rk_tsadcv2_alarm_temp,
1118 .set_tshut_temp = rk_tsadcv2_tshut_temp,
1119 .set_tshut_mode = rk_tsadcv2_tshut_mode,
1120
1121 .table =
1122 {
1123 .id = rk3568_code_table,
1124 .length = ARRAY_SIZE(rk3568_code_table),
1125 .data_mask = TSADCV2_DATA_MASK,
1126 .mode = ADC_INCREMENT,
1127 },
1128 };
1129
1130 static const struct of_device_id of_rockchip_thermal_match[] = {
1131 {
1132 .compatible = "rockchip,px30-tsadc",
1133 .data = (void *)&px30_tsadc_data,
1134 },
1135 {
1136 .compatible = "rockchip,rv1108-tsadc",
1137 .data = (void *)&rv1108_tsadc_data,
1138 },
1139 {
1140 .compatible = "rockchip,rv1126-tsadc",
1141 .data = (void *)&rv1126_tsadc_data,
1142 },
1143 {
1144 .compatible = "rockchip,rk1808-tsadc",
1145 .data = (void *)&rk1808_tsadc_data,
1146 },
1147 {
1148 .compatible = "rockchip,rk3228-tsadc",
1149 .data = (void *)&rk3228_tsadc_data,
1150 },
1151 {
1152 .compatible = "rockchip,rk3288-tsadc",
1153 .data = (void *)&rk3288_tsadc_data,
1154 },
1155 {
1156 .compatible = "rockchip,rk3328-tsadc",
1157 .data = (void *)&rk3328_tsadc_data,
1158 },
1159 {
1160 .compatible = "rockchip,rk3366-tsadc",
1161 .data = (void *)&rk3366_tsadc_data,
1162 },
1163 {
1164 .compatible = "rockchip,rk3368-tsadc",
1165 .data = (void *)&rk3368_tsadc_data,
1166 },
1167 {
1168 .compatible = "rockchip,rk3399-tsadc",
1169 .data = (void *)&rk3399_tsadc_data,
1170 },
1171 {
1172 .compatible = "rockchip,rk3568-tsadc",
1173 .data = (void *)&rk3568_tsadc_data,
1174 },
1175 {},
1176 };
1177 MODULE_DEVICE_TABLE(of, of_rockchip_thermal_match);
1178
rockchip_thermal_toggle_sensor(struct rockchip_thermal_sensor *sensor, bool on)1179 static void rockchip_thermal_toggle_sensor(struct rockchip_thermal_sensor *sensor, bool on)
1180 {
1181 struct thermal_zone_device *tzd = sensor->tzd;
1182
1183 if (on) {
1184 thermal_zone_device_enable(tzd);
1185 } else {
1186 thermal_zone_device_disable(tzd);
1187 }
1188 }
1189
rockchip_thermal_alarm_irq_thread(int irq, void *dev)1190 static irqreturn_t rockchip_thermal_alarm_irq_thread(int irq, void *dev)
1191 {
1192 struct rockchip_thermal_data *thermal = dev;
1193 int i;
1194
1195 dev_dbg(&thermal->pdev->dev, "thermal alarm\n");
1196
1197 thermal->chip->irq_ack(thermal->regs);
1198
1199 for (i = 0; i < thermal->chip->chn_num; i++) {
1200 thermal_zone_device_update(thermal->sensors[i].tzd, THERMAL_EVENT_UNSPECIFIED);
1201 }
1202
1203 return IRQ_HANDLED;
1204 }
1205
rockchip_thermal_set_trips(void *_sensor, int low, int high)1206 static int rockchip_thermal_set_trips(void *_sensor, int low, int high)
1207 {
1208 struct rockchip_thermal_sensor *sensor = _sensor;
1209 struct rockchip_thermal_data *thermal = sensor->thermal;
1210 const struct rockchip_tsadc_chip *tsadc = thermal->chip;
1211
1212 dev_dbg(&thermal->pdev->dev, "%s: sensor %d: low: %d, high %d\n", __func__, sensor->id, low, high);
1213
1214 if (tsadc->trim_temp) {
1215 high += tsadc->trim_temp(thermal->pdev);
1216 }
1217
1218 return tsadc->set_alarm_temp(&tsadc->table, sensor->id, thermal->regs, high);
1219 }
1220
rockchip_thermal_get_temp(void *_sensor, int *out_temp)1221 static int rockchip_thermal_get_temp(void *_sensor, int *out_temp)
1222 {
1223 struct rockchip_thermal_sensor *sensor = _sensor;
1224 struct rockchip_thermal_data *thermal = sensor->thermal;
1225 const struct rockchip_tsadc_chip *tsadc = sensor->thermal->chip;
1226 int retval;
1227
1228 retval = tsadc->get_temp(&tsadc->table, sensor->id, thermal->regs, out_temp);
1229 if (tsadc->trim_temp) {
1230 *out_temp -= tsadc->trim_temp(thermal->pdev);
1231 }
1232 dev_dbg(&thermal->pdev->dev, "sensor %d - temp: %d, retval: %d\n", sensor->id, *out_temp, retval);
1233
1234 return retval;
1235 }
1236
1237 static const struct thermal_zone_of_device_ops rockchip_of_thermal_ops = {
1238 .get_temp = rockchip_thermal_get_temp,
1239 .set_trips = rockchip_thermal_set_trips,
1240 };
1241
thermal_pinctrl_select_otp(struct rockchip_thermal_data *thermal)1242 static void thermal_pinctrl_select_otp(struct rockchip_thermal_data *thermal)
1243 {
1244 if (!IS_ERR(thermal->pinctrl) && !IS_ERR_OR_NULL(thermal->otp_state)) {
1245 pinctrl_select_state(thermal->pinctrl, thermal->otp_state);
1246 }
1247 }
1248
thermal_pinctrl_select_gpio(struct rockchip_thermal_data *thermal)1249 static void thermal_pinctrl_select_gpio(struct rockchip_thermal_data *thermal)
1250 {
1251 if (!IS_ERR(thermal->pinctrl) && !IS_ERR_OR_NULL(thermal->gpio_state)) {
1252 pinctrl_select_state(thermal->pinctrl, thermal->gpio_state);
1253 }
1254 }
1255
rockchip_get_efuse_value(struct device_node *np, char *porp_name, int *value)1256 static int rockchip_get_efuse_value(struct device_node *np, char *porp_name, int *value)
1257 {
1258 struct nvmem_cell *cell;
1259 unsigned char *buf;
1260 size_t len;
1261
1262 cell = of_nvmem_cell_get(np, porp_name);
1263 if (IS_ERR(cell)) {
1264 return PTR_ERR(cell);
1265 }
1266
1267 buf = (unsigned char *)nvmem_cell_read(cell, &len);
1268
1269 nvmem_cell_put(cell);
1270
1271 if (IS_ERR(buf)) {
1272 return PTR_ERR(buf);
1273 }
1274
1275 *value = buf[0];
1276
1277 kfree(buf);
1278
1279 return 0;
1280 }
1281
rockchip_configure_from_dt(struct device *dev, struct device_node *np, struct rockchip_thermal_data *thermal)1282 static int rockchip_configure_from_dt(struct device *dev, struct device_node *np, struct rockchip_thermal_data *thermal)
1283 {
1284 const struct rockchip_tsadc_chip *tsadc = thermal->chip;
1285 u32 shut_temp, tshut_mode, tshut_polarity;
1286 int trim_l = 0, trim_h = 0, trim_bsae = 0;
1287
1288 if (of_property_read_u32(np, "rockchip,hw-tshut-temp", &shut_temp)) {
1289 dev_warn(dev, "Missing tshut temp property, using default %d\n", thermal->chip->tshut_temp);
1290 thermal->tshut_temp = thermal->chip->tshut_temp;
1291 } else {
1292 if (shut_temp > INT_MAX) {
1293 dev_err(dev, "Invalid tshut temperature specified: %d\n", shut_temp);
1294 return -ERANGE;
1295 }
1296 thermal->tshut_temp = shut_temp;
1297 }
1298
1299 if (of_property_read_u32(np, "rockchip,hw-tshut-mode", &tshut_mode)) {
1300 dev_warn(dev, "Missing tshut mode property, using default (%s)\n",
1301 thermal->chip->tshut_mode == TSHUT_MODE_OTP ? "gpio" : "cru");
1302 thermal->tshut_mode = thermal->chip->tshut_mode;
1303 } else {
1304 thermal->tshut_mode = tshut_mode;
1305 }
1306
1307 if (thermal->tshut_mode > 1) {
1308 dev_err(dev, "Invalid tshut mode specified: %d\n", thermal->tshut_mode);
1309 return -EINVAL;
1310 }
1311
1312 if (of_property_read_u32(np, "rockchip,hw-tshut-polarity", &tshut_polarity)) {
1313 dev_warn(dev, "Missing tshut-polarity property, using default (%s)\n",
1314 thermal->chip->tshut_polarity == TSHUT_LOW_ACTIVE ? "low" : "high");
1315 thermal->tshut_polarity = thermal->chip->tshut_polarity;
1316 } else {
1317 thermal->tshut_polarity = tshut_polarity;
1318 }
1319
1320 if (thermal->tshut_polarity > 1) {
1321 dev_err(dev, "Invalid tshut-polarity specified: %d\n", thermal->tshut_polarity);
1322 return -EINVAL;
1323 }
1324
1325 /* The tsadc wont to handle the error in here since some SoCs didn't
1326 * need this property.
1327 */
1328 thermal->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
1329 if (IS_ERR(thermal->grf)) {
1330 dev_warn(dev, "Missing rockchip,grf property\n");
1331 }
1332
1333 if (tsadc->trim_temp && tsadc->get_trim_code) {
1334 /* The tsadc won't to handle the error in here
1335 * since some SoCs didn't need this property.
1336 * rv1126 need trim tsadc.
1337 */
1338 if (rockchip_get_efuse_value(np, "trim_l", &trim_l)) {
1339 dev_warn(dev, "Missing trim_l property\n");
1340 }
1341 if (rockchip_get_efuse_value(np, "trim_h", &trim_h)) {
1342 dev_warn(dev, "Missing trim_h property\n");
1343 }
1344 if (rockchip_get_efuse_value(np, "trim_base", &trim_bsae)) {
1345 dev_warn(dev, "Missing trim_base property\n");
1346 }
1347
1348 if (trim_l && trim_h && trim_bsae) {
1349 thermal->trim = tsadc->get_trim_code(thermal->pdev, (trim_h << ROCKCHIP_THERMAL_EIGHT) | trim_l, trim_bsae);
1350 dev_info(dev, "tsadc trimmed value = %d\n", thermal->trim);
1351 thermal->tshut_temp += tsadc->trim_temp(thermal->pdev);
1352 }
1353 }
1354
1355 return 0;
1356 }
1357
rockchip_thermal_register_sensor(struct platform_device *pdev, struct rockchip_thermal_data *thermal, struct rockchip_thermal_sensor *sensor, int id)1358 static int rockchip_thermal_register_sensor(struct platform_device *pdev, struct rockchip_thermal_data *thermal,
1359 struct rockchip_thermal_sensor *sensor, int id)
1360 {
1361 const struct rockchip_tsadc_chip *tsadc = thermal->chip;
1362 int error;
1363
1364 tsadc->set_tshut_mode(thermal->grf, id, thermal->regs, thermal->tshut_mode);
1365
1366 error = tsadc->set_tshut_temp(&tsadc->table, id, thermal->regs, thermal->tshut_temp);
1367 if (error) {
1368 dev_err(&pdev->dev, "%s: invalid tshut=%d, error=%d\n", __func__, thermal->tshut_temp, error);
1369 }
1370
1371 sensor->thermal = thermal;
1372 sensor->id = id;
1373 sensor->tzd = devm_thermal_zone_of_sensor_register(&pdev->dev, id, sensor, &rockchip_of_thermal_ops);
1374 if (IS_ERR(sensor->tzd)) {
1375 error = PTR_ERR(sensor->tzd);
1376 dev_err(&pdev->dev, "failed to register sensor %d: %d\n", id, error);
1377 return error;
1378 }
1379
1380 return 0;
1381 }
1382
1383 /**
1384 * Reset TSADC Controller, reset all tsadc registers.
1385 * @reset: the reset controller of tsadc
1386 */
rockchip_thermal_reset_controller(struct reset_control *reset)1387 static void rockchip_thermal_reset_controller(struct reset_control *reset)
1388 {
1389 reset_control_assert(reset);
1390 usleep_range(ROCKCHIP_THERMAL_TEN, ROCKCHIP_THERMAL_TWENTY);
1391 reset_control_deassert(reset);
1392 }
1393
rockchip_dump_temperature(struct rockchip_thermal_data *thermal)1394 static void rockchip_dump_temperature(struct rockchip_thermal_data *thermal)
1395 {
1396 struct platform_device *pdev;
1397 int i;
1398
1399 if (!thermal) {
1400 return;
1401 }
1402
1403 pdev = thermal->pdev;
1404
1405 for (i = 0; i < thermal->chip->chn_num; i++) {
1406 struct rockchip_thermal_sensor *sensor = &thermal->sensors[i];
1407 struct thermal_zone_device *tz = sensor->tzd;
1408
1409 if (tz->temperature != THERMAL_TEMP_INVALID) {
1410 dev_warn(&pdev->dev, "channal %d: temperature(%d C)\n", i, tz->temperature / ROCKCHIP_THERMAL_ONETHOUSAND);
1411 }
1412 }
1413
1414 if (thermal->regs) {
1415 pr_warn("THERMAL REGS:\n");
1416 print_hex_dump(KERN_WARNING, "", DUMP_PREFIX_OFFSET, ROCKCHIP_THERMAL_THIRTYTWO, 0x4, thermal->regs, 0x88,
1417 false);
1418 }
1419 }
1420
rockchip_thermal_panic(struct notifier_block *this, unsigned long ev, void *ptr)1421 static int rockchip_thermal_panic(struct notifier_block *this, unsigned long ev, void *ptr)
1422 {
1423 struct rockchip_thermal_data *thermal;
1424
1425 thermal = container_of(this, struct rockchip_thermal_data, panic_nb);
1426 rockchip_dump_temperature(thermal);
1427
1428 return NOTIFY_DONE;
1429 }
1430
rockchip_thermal_probe(struct platform_device *pdev)1431 static int rockchip_thermal_probe(struct platform_device *pdev)
1432 {
1433 struct device_node *np = pdev->dev.of_node;
1434 struct rockchip_thermal_data *thermal;
1435 const struct of_device_id *match;
1436 struct resource *res;
1437 int irq;
1438 int i;
1439 int error;
1440
1441 match = of_match_node(of_rockchip_thermal_match, np);
1442 if (!match) {
1443 return -ENXIO;
1444 }
1445
1446 irq = platform_get_irq(pdev, 0);
1447 if (irq < 0) {
1448 return -EINVAL;
1449 }
1450
1451 thermal = devm_kzalloc(&pdev->dev, sizeof(struct rockchip_thermal_data), GFP_KERNEL);
1452 if (!thermal) {
1453 return -ENOMEM;
1454 }
1455
1456 thermal->pdev = pdev;
1457
1458 thermal->chip = (const struct rockchip_tsadc_chip *)match->data;
1459 if (!thermal->chip) {
1460 return -EINVAL;
1461 }
1462
1463 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1464 thermal->regs = devm_ioremap_resource(&pdev->dev, res);
1465 if (IS_ERR(thermal->regs)) {
1466 return PTR_ERR(thermal->regs);
1467 }
1468
1469 thermal->reset = devm_reset_control_array_get(&pdev->dev, false, false);
1470 if (IS_ERR(thermal->reset)) {
1471 if (PTR_ERR(thermal->reset) != -EPROBE_DEFER) {
1472 dev_err(&pdev->dev, "failed to get tsadc reset lines\n");
1473 }
1474 return PTR_ERR(thermal->reset);
1475 }
1476
1477 thermal->num_clks = devm_clk_bulk_get_all(&pdev->dev, &thermal->clks);
1478 if (thermal->num_clks < 1) {
1479 return -ENODEV;
1480 }
1481
1482 error = clk_bulk_prepare_enable(thermal->num_clks, thermal->clks);
1483 if (error) {
1484 dev_err(&pdev->dev, "failed to prepare enable tsadc bulk clks: %d\n", error);
1485 return error;
1486 }
1487 platform_set_drvdata(pdev, thermal);
1488
1489 thermal->chip->control(thermal->regs, false);
1490
1491 rockchip_thermal_reset_controller(thermal->reset);
1492
1493 error = rockchip_configure_from_dt(&pdev->dev, np, thermal);
1494 if (error) {
1495 dev_err(&pdev->dev, "failed to parse device tree data: %d\n", error);
1496 goto err_disable_clocks;
1497 }
1498
1499 thermal->chip->initialize(thermal->grf, thermal->regs, thermal->tshut_polarity);
1500
1501 if (thermal->tshut_mode == TSHUT_MODE_OTP) {
1502 thermal->pinctrl = devm_pinctrl_get(&pdev->dev);
1503 if (IS_ERR(thermal->pinctrl)) {
1504 dev_err(&pdev->dev, "failed to find thermal pinctrl\n");
1505 }
1506
1507 thermal->gpio_state = pinctrl_lookup_state(thermal->pinctrl, "gpio");
1508 if (IS_ERR_OR_NULL(thermal->gpio_state)) {
1509 dev_err(&pdev->dev, "failed to find thermal gpio state\n");
1510 }
1511
1512 thermal->otp_state = pinctrl_lookup_state(thermal->pinctrl, "otpout");
1513 if (IS_ERR_OR_NULL(thermal->otp_state)) {
1514 dev_err(&pdev->dev, "failed to find thermal otpout state\n");
1515 }
1516
1517 thermal_pinctrl_select_otp(thermal);
1518 }
1519
1520 for (i = 0; i < thermal->chip->chn_num; i++) {
1521 error = rockchip_thermal_register_sensor(pdev, thermal, &thermal->sensors[i], thermal->chip->chn_id[i]);
1522 if (error) {
1523 dev_err(&pdev->dev, "failed to register sensor[%d] : error = %d\n", i, error);
1524 goto err_disable_clocks;
1525 }
1526 }
1527
1528 error = devm_request_threaded_irq(&pdev->dev, irq, NULL, &rockchip_thermal_alarm_irq_thread, IRQF_ONESHOT,
1529 "rockchip_thermal", thermal);
1530 if (error) {
1531 dev_err(&pdev->dev, "failed to request tsadc irq: %d\n", error);
1532 goto err_disable_clocks;
1533 }
1534
1535 thermal->chip->control(thermal->regs, true);
1536
1537 for (i = 0; i < thermal->chip->chn_num; i++) {
1538 rockchip_thermal_toggle_sensor(&thermal->sensors[i], true);
1539 thermal->sensors[i].tzd->tzp->no_hwmon = false;
1540 error = thermal_add_hwmon_sysfs(thermal->sensors[i].tzd);
1541 if (error) {
1542 dev_warn(&pdev->dev, "failed to register sensor %d with hwmon: %d\n", i, error);
1543 }
1544 }
1545
1546 thermal->panic_nb.notifier_call = rockchip_thermal_panic;
1547 atomic_notifier_chain_register(&panic_notifier_list, &thermal->panic_nb);
1548
1549 dev_info(&pdev->dev, "tsadc is probed successfully!\n");
1550
1551 return 0;
1552
1553 err_disable_clocks:
1554 clk_bulk_disable_unprepare(thermal->num_clks, thermal->clks);
1555
1556 return error;
1557 }
1558
rockchip_thermal_remove(struct platform_device *pdev)1559 static int rockchip_thermal_remove(struct platform_device *pdev)
1560 {
1561 struct rockchip_thermal_data *thermal = platform_get_drvdata(pdev);
1562 int i;
1563
1564 for (i = 0; i < thermal->chip->chn_num; i++) {
1565 struct rockchip_thermal_sensor *sensor = &thermal->sensors[i];
1566
1567 thermal_remove_hwmon_sysfs(sensor->tzd);
1568 rockchip_thermal_toggle_sensor(sensor, false);
1569 }
1570
1571 thermal->chip->control(thermal->regs, false);
1572
1573 clk_bulk_disable_unprepare(thermal->num_clks, thermal->clks);
1574
1575 return 0;
1576 }
1577
rockchip_thermal_shutdown(struct platform_device *pdev)1578 static void rockchip_thermal_shutdown(struct platform_device *pdev)
1579 {
1580 struct rockchip_thermal_data *thermal = platform_get_drvdata(pdev);
1581 int i;
1582
1583 for (i = 0; i < thermal->chip->chn_num; i++) {
1584 int id = thermal->sensors[i].id;
1585
1586 if (thermal->tshut_mode != TSHUT_MODE_CRU) {
1587 thermal->chip->set_tshut_mode(thermal->grf, id, thermal->regs, TSHUT_MODE_CRU);
1588 }
1589 }
1590 if (thermal->tshut_mode == TSHUT_MODE_OTP) {
1591 thermal_pinctrl_select_gpio(thermal);
1592 }
1593 }
1594
rockchip_thermal_suspend(struct device *dev)1595 static int __maybe_unused rockchip_thermal_suspend(struct device *dev)
1596 {
1597 struct rockchip_thermal_data *thermal = dev_get_drvdata(dev);
1598 int i;
1599
1600 for (i = 0; i < thermal->chip->chn_num; i++) {
1601 rockchip_thermal_toggle_sensor(&thermal->sensors[i], false);
1602 }
1603
1604 thermal->chip->control(thermal->regs, false);
1605
1606 clk_bulk_disable(thermal->num_clks, thermal->clks);
1607
1608 if (thermal->tshut_mode == TSHUT_MODE_OTP) {
1609 thermal_pinctrl_select_gpio(thermal);
1610 }
1611
1612 return 0;
1613 }
1614
rockchip_thermal_resume(struct device *dev)1615 static int __maybe_unused rockchip_thermal_resume(struct device *dev)
1616 {
1617 struct rockchip_thermal_data *thermal = dev_get_drvdata(dev);
1618 int i;
1619 int error;
1620
1621 error = clk_bulk_enable(thermal->num_clks, thermal->clks);
1622 if (error) {
1623 dev_err(dev, "failed to enable tsadc bulk clks: %d\n", error);
1624 return error;
1625 }
1626
1627 rockchip_thermal_reset_controller(thermal->reset);
1628
1629 thermal->chip->initialize(thermal->grf, thermal->regs, thermal->tshut_polarity);
1630
1631 for (i = 0; i < thermal->chip->chn_num; i++) {
1632 int id = thermal->sensors[i].id;
1633
1634 thermal->chip->set_tshut_mode(thermal->grf, id, thermal->regs, thermal->tshut_mode);
1635
1636 error = thermal->chip->set_tshut_temp(&thermal->chip->table, id, thermal->regs, thermal->tshut_temp);
1637 if (error) {
1638 dev_err(dev, "%s: invalid tshut=%d, error=%d\n", __func__, thermal->tshut_temp, error);
1639 }
1640 }
1641
1642 thermal->chip->control(thermal->regs, true);
1643
1644 for (i = 0; i < thermal->chip->chn_num; i++) {
1645 rockchip_thermal_toggle_sensor(&thermal->sensors[i], true);
1646 }
1647
1648 if (thermal->tshut_mode == TSHUT_MODE_OTP) {
1649 thermal_pinctrl_select_otp(thermal);
1650 }
1651
1652 return 0;
1653 }
1654
1655 static SIMPLE_DEV_PM_OPS(rockchip_thermal_pm_ops, rockchip_thermal_suspend, rockchip_thermal_resume);
1656
1657 static struct platform_driver rockchip_thermal_driver = {
1658 .driver =
1659 {
1660 .name = "rockchip-thermal",
1661 .pm = &rockchip_thermal_pm_ops,
1662 .of_match_table = of_rockchip_thermal_match,
1663 },
1664 .probe = rockchip_thermal_probe,
1665 .remove = rockchip_thermal_remove,
1666 .shutdown = rockchip_thermal_shutdown,
1667 };
1668
1669 module_platform_driver(rockchip_thermal_driver);
1670
1671 MODULE_DESCRIPTION("ROCKCHIP THERMAL Driver");
1672 MODULE_AUTHOR("Rockchip, Inc.");
1673 MODULE_LICENSE("GPL v2");
1674 MODULE_ALIAS("platform:rockchip-thermal");
1675