| /device/soc/rockchip/common/sdk_linux/include/dt-bindings/clock/ |
| H A D | rk3036-cru.h | 23 #define SCLK_UART0 77 macro
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| H A D | rk3128-cru.h | 25 #define SCLK_UART0 77 macro
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| H A D | rk3188-cru-common.h | 20 #define SCLK_UART0 64 macro
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| H A D | rk3288-cru.h | 32 #define SCLK_UART0 77 macro
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| H A D | rk3368-cru.h | 30 #define SCLK_UART0 77 macro
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| H A D | rk3568-cru.h | 24 #define SCLK_UART0 11 macro
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| H A D | rk3399-cru.h | 39 #define SCLK_UART0 81 macro
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| /device/soc/rockchip/rk3588/kernel/include/dt-bindings/clock/ |
| H A D | rv1126-cru.h | 83 #define SCLK_UART0 16 macro
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| H A D | rk3568-cru.h | 24 #define SCLK_UART0 11 macro
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| H A D | rk3588-cru.h | 682 #define SCLK_UART0 686 macro
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| /device/soc/rockchip/common/sdk_linux/drivers/clk/rockchip/ |
| H A D | clk-rk3036.c | 153 MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT, RK2928_CLKSEL_CON(13), 8, 2, MFLAGS);
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| H A D | clk-rk3128.c | 176 MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT, RK2928_CLKSEL_CON(13), 8, 2, MFLAGS);
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| H A D | clk-rk3368.c | 257 MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT, RK3368_CLKSEL_CON(33), 8, 2, MFLAGS);
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| H A D | clk-rk3188.c | 246 MUX(SCLK_UART0, "sclk_uart0", mux_sclk_uart0_p, 0, RK2928_CLKSEL_CON(13), 8, 2, MFLAGS);
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| H A D | clk-rk3328.c | 202 MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT, RK3328_CLKSEL_CON(14), 8, 2, MFLAGS);
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| H A D | clk-rv1108.c | 158 MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT, RV1108_CLKSEL_CON(13), 8, 2, MFLAGS);
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| H A D | clk-rk3228.c | 187 MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT, RK2928_CLKSEL_CON(13), 8, 2, MFLAGS);
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| H A D | clk-rk3308.c | 282 GATE(SCLK_UART0, "clk_uart0", "clk_uart0_mux", 0, RK3308_CLKGATE_CON(1), 12, GFLAGS),
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| H A D | clk-rk3288.c | 208 MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT, RK3288_CLKSEL_CON(13), 8, 2, MFLAGS);
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| H A D | clk-rk3399.c | 257 SCLK_UART0, "clk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT, RK3399_CLKSEL_CON(33), 8, 2, MFLAGS, uart_mux_idx);
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| /device/soc/rockchip/rk3566/vendor/drivers/clk/ |
| H A D | clk-rk3568.c | 1071 GATE(SCLK_UART0, "sclk_uart0", "sclk_uart0_mux", 0, RK3568_PMU_CLKGATE_CON(1), 5, GFLAGS),
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| /device/soc/rockchip/rk3588/kernel/drivers/clk/rockchip/ |
| H A D | clk-rk3588.c | 2234 GATE(SCLK_UART0, "sclk_uart0", "clk_uart0", 0,
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