1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (c) 2019 Rockchip Electronics Co. Ltd. 4 * Author: Finley Xiao <finley.xiao@rock-chips.com> 5 */ 6 7 #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RV1126_H 8 #define _DT_BINDINGS_CLK_ROCKCHIP_RV1126_H 9 10 /* pmucru-clocks indices */ 11 12 /* pll clocks */ 13 #define PLL_GPLL 1 14 15 /* sclk (special clocks) */ 16 #define CLK_OSC0_DIV32K 2 17 #define CLK_RTC32K 3 18 #define CLK_WIFI_DIV 4 19 #define CLK_WIFI_OSC0 5 20 #define CLK_WIFI 6 21 #define CLK_PMU 7 22 #define SCLK_UART1_DIV 8 23 #define SCLK_UART1_FRACDIV 9 24 #define SCLK_UART1_MUX 10 25 #define SCLK_UART1 11 26 #define CLK_I2C0 12 27 #define CLK_I2C2 13 28 #define CLK_CAPTURE_PWM0 14 29 #define CLK_PWM0 15 30 #define CLK_CAPTURE_PWM1 16 31 #define CLK_PWM1 17 32 #define CLK_SPI0 18 33 #define DBCLK_GPIO0 19 34 #define CLK_PMUPVTM 20 35 #define CLK_CORE_PMUPVTM 21 36 #define CLK_REF12M 22 37 #define CLK_USBPHY_OTG_REF 23 38 #define CLK_USBPHY_HOST_REF 24 39 #define CLK_REF24M 25 40 #define CLK_MIPIDSIPHY_REF 26 41 #define CLK_32K_IOE 27 42 43 /* pclk */ 44 #define PCLK_PDPMU 30 45 #define PCLK_PMU 31 46 #define PCLK_UART1 32 47 #define PCLK_I2C0 33 48 #define PCLK_I2C2 34 49 #define PCLK_PWM0 35 50 #define PCLK_PWM1 36 51 #define PCLK_SPI0 37 52 #define PCLK_GPIO0 38 53 #define PCLK_PMUSGRF 39 54 #define PCLK_PMUGRF 40 55 #define PCLK_PMUCRU 41 56 #define PCLK_CHIPVEROTP 42 57 #define PCLK_PDPMU_NIU 43 58 #define PCLK_PMUPVTM 44 59 #define PCLK_SCRKEYGEN 45 60 61 #define CLKPMU_NR_CLKS (PCLK_SCRKEYGEN + 1) 62 63 /* cru-clocks indices */ 64 65 /* pll clocks */ 66 #define PLL_APLL 1 67 #define PLL_DPLL 2 68 #define PLL_CPLL 3 69 #define PLL_HPLL 4 70 71 /* sclk (special clocks) */ 72 #define ARMCLK 5 73 #define USB480M 6 74 #define CLK_CORE_CPUPVTM 7 75 #define CLK_CPUPVTM 8 76 #define CLK_SCR1 9 77 #define CLK_SCR1_CORE 10 78 #define CLK_SCR1_RTC 11 79 #define CLK_SCR1_JTAG 12 80 #define SCLK_UART0_DIV 13 81 #define SCLK_UART0_FRAC 14 82 #define SCLK_UART0_MUX 15 83 #define SCLK_UART0 16 84 #define SCLK_UART2_DIV 17 85 #define SCLK_UART2_FRAC 18 86 #define SCLK_UART2_MUX 19 87 #define SCLK_UART2 20 88 #define SCLK_UART3_DIV 21 89 #define SCLK_UART3_FRAC 22 90 #define SCLK_UART3_MUX 23 91 #define SCLK_UART3 24 92 #define SCLK_UART4_DIV 25 93 #define SCLK_UART4_FRAC 26 94 #define SCLK_UART4_MUX 27 95 #define SCLK_UART4 28 96 #define SCLK_UART5_DIV 29 97 #define SCLK_UART5_FRAC 30 98 #define SCLK_UART5_MUX 31 99 #define SCLK_UART5 32 100 #define CLK_I2C1 33 101 #define CLK_I2C3 34 102 #define CLK_I2C4 35 103 #define CLK_I2C5 36 104 #define CLK_SPI1 37 105 #define CLK_CAPTURE_PWM2 38 106 #define CLK_PWM2 39 107 #define DBCLK_GPIO1 40 108 #define DBCLK_GPIO2 41 109 #define DBCLK_GPIO3 42 110 #define DBCLK_GPIO4 43 111 #define CLK_SARADC 44 112 #define CLK_TIMER0 45 113 #define CLK_TIMER1 46 114 #define CLK_TIMER2 47 115 #define CLK_TIMER3 48 116 #define CLK_TIMER4 49 117 #define CLK_TIMER5 50 118 #define CLK_CAN 51 119 #define CLK_NPU_TSADC 52 120 #define CLK_NPU_TSADCPHY 53 121 #define CLK_CPU_TSADC 54 122 #define CLK_CPU_TSADCPHY 55 123 #define CLK_CRYPTO_CORE 56 124 #define CLK_CRYPTO_PKA 57 125 #define MCLK_I2S0_TX_DIV 58 126 #define MCLK_I2S0_TX_FRACDIV 59 127 #define MCLK_I2S0_TX_MUX 60 128 #define MCLK_I2S0_TX 61 129 #define MCLK_I2S0_RX_DIV 62 130 #define MCLK_I2S0_RX_FRACDIV 63 131 #define MCLK_I2S0_RX_MUX 64 132 #define MCLK_I2S0_RX 65 133 #define MCLK_I2S0_TX_OUT2IO 66 134 #define MCLK_I2S0_RX_OUT2IO 67 135 #define MCLK_I2S1_DIV 68 136 #define MCLK_I2S1_FRACDIV 69 137 #define MCLK_I2S1_MUX 70 138 #define MCLK_I2S1 71 139 #define MCLK_I2S1_OUT2IO 72 140 #define MCLK_I2S2_DIV 73 141 #define MCLK_I2S2_FRACDIV 74 142 #define MCLK_I2S2_MUX 75 143 #define MCLK_I2S2 76 144 #define MCLK_I2S2_OUT2IO 77 145 #define MCLK_PDM 78 146 #define SCLK_ADUPWM_DIV 79 147 #define SCLK_AUDPWM_FRACDIV 80 148 #define SCLK_AUDPWM_MUX 81 149 #define SCLK_AUDPWM 82 150 #define CLK_ACDCDIG_ADC 83 151 #define CLK_ACDCDIG_DAC 84 152 #define CLK_ACDCDIG_I2C 85 153 #define CLK_VENC_CORE 86 154 #define CLK_VDEC_CORE 87 155 #define CLK_VDEC_CA 88 156 #define CLK_VDEC_HEVC_CA 89 157 #define CLK_RGA_CORE 90 158 #define CLK_IEP_CORE 91 159 #define CLK_ISP_DIV 92 160 #define CLK_ISP_NP5 93 161 #define CLK_ISP_NUX 94 162 #define CLK_ISP 95 163 #define CLK_CIF_OUT_DIV 96 164 #define CLK_CIF_OUT_FRACDIV 97 165 #define CLK_CIF_OUT_MUX 98 166 #define CLK_CIF_OUT 99 167 #define CLK_MIPICSI_OUT_DIV 100 168 #define CLK_MIPICSI_OUT_FRACDIV 101 169 #define CLK_MIPICSI_OUT_MUX 102 170 #define CLK_MIPICSI_OUT 103 171 #define CLK_ISPP_DIV 104 172 #define CLK_ISPP_NP5 105 173 #define CLK_ISPP_NUX 106 174 #define CLK_ISPP 107 175 #define CLK_SDMMC 108 176 #define SCLK_SDMMC_DRV 109 177 #define SCLK_SDMMC_SAMPLE 110 178 #define CLK_SDIO 111 179 #define SCLK_SDIO_DRV 112 180 #define SCLK_SDIO_SAMPLE 113 181 #define CLK_EMMC 114 182 #define SCLK_EMMC_DRV 115 183 #define SCLK_EMMC_SAMPLE 116 184 #define CLK_NANDC 117 185 #define SCLK_SFC 118 186 #define CLK_USBHOST_UTMI_OHCI 119 187 #define CLK_USBOTG_REF 120 188 #define CLK_GMAC_DIV 121 189 #define CLK_GMAC_RGMII_M0 122 190 #define CLK_GMAC_SRC_M0 123 191 #define CLK_GMAC_RGMII_M1 124 192 #define CLK_GMAC_SRC_M1 125 193 #define CLK_GMAC_SRC 126 194 #define CLK_GMAC_REF 127 195 #define CLK_GMAC_TX_SRC 128 196 #define CLK_GMAC_TX_DIV5 129 197 #define CLK_GMAC_TX_DIV50 130 198 #define RGMII_MODE_CLK 131 199 #define CLK_GMAC_RX_SRC 132 200 #define CLK_GMAC_RX_DIV2 133 201 #define CLK_GMAC_RX_DIV20 134 202 #define RMII_MODE_CLK 135 203 #define CLK_GMAC_TX_RX 136 204 #define CLK_GMAC_PTPREF 137 205 #define CLK_GMAC_ETHERNET_OUT 138 206 #define CLK_DDRPHY 139 207 #define CLK_DDR_MON 140 208 #define TMCLK_DDR_MON 141 209 #define CLK_NPU_DIV 142 210 #define CLK_NPU_NP5 143 211 #define CLK_CORE_NPU 144 212 #define CLK_CORE_NPUPVTM 145 213 #define CLK_NPUPVTM 146 214 #define SCLK_DDRCLK 147 215 #define CLK_OTP 148 216 217 /* dclk */ 218 #define DCLK_DECOM 150 219 #define DCLK_VOP_DIV 151 220 #define DCLK_VOP_FRACDIV 152 221 #define DCLK_VOP_MUX 153 222 #define DCLK_VOP 154 223 #define DCLK_CIF 155 224 #define DCLK_CIFLITE 156 225 226 /* aclk */ 227 #define ACLK_PDBUS 160 228 #define ACLK_DMAC 161 229 #define ACLK_DCF 162 230 #define ACLK_SPINLOCK 163 231 #define ACLK_DECOM 164 232 #define ACLK_PDCRYPTO 165 233 #define ACLK_CRYPTO 166 234 #define ACLK_PDVEPU 167 235 #define ACLK_VENC 168 236 #define ACLK_PDVDEC 169 237 #define ACLK_PDJPEG 170 238 #define ACLK_VDEC 171 239 #define ACLK_JPEG 172 240 #define ACLK_PDVO 173 241 #define ACLK_RGA 174 242 #define ACLK_VOP 175 243 #define ACLK_IEP 176 244 #define ACLK_PDVI_DIV 177 245 #define ACLK_PDVI_NP5 178 246 #define ACLK_PDVI 179 247 #define ACLK_ISP 180 248 #define ACLK_CIF 181 249 #define ACLK_CIFLITE 182 250 #define ACLK_PDISPP_DIV 183 251 #define ACLK_PDISPP_NP5 184 252 #define ACLK_PDISPP 185 253 #define ACLK_ISPP 186 254 #define ACLK_PDPHP 187 255 #define ACLK_PDUSB 188 256 #define ACLK_USBOTG 189 257 #define ACLK_PDGMAC 190 258 #define ACLK_GMAC 191 259 #define ACLK_PDNPU_DIV 192 260 #define ACLK_PDNPU_NP5 193 261 #define ACLK_PDNPU 194 262 #define ACLK_NPU 195 263 264 /* hclk */ 265 #define HCLK_PDCORE_NIU 200 266 #define HCLK_PDUSB 201 267 #define HCLK_PDCRYPTO 202 268 #define HCLK_CRYPTO 203 269 #define HCLK_PDAUDIO 204 270 #define HCLK_I2S0 205 271 #define HCLK_I2S1 206 272 #define HCLK_I2S2 207 273 #define HCLK_PDM 208 274 #define HCLK_AUDPWM 209 275 #define HCLK_PDVEPU 210 276 #define HCLK_VENC 211 277 #define HCLK_PDVDEC 212 278 #define HCLK_PDJPEG 213 279 #define HCLK_VDEC 214 280 #define HCLK_JPEG 215 281 #define HCLK_PDVO 216 282 #define HCLK_RGA 217 283 #define HCLK_VOP 218 284 #define HCLK_IEP 219 285 #define HCLK_PDVI 220 286 #define HCLK_ISP 221 287 #define HCLK_CIF 222 288 #define HCLK_CIFLITE 223 289 #define HCLK_PDISPP 224 290 #define HCLK_ISPP 225 291 #define HCLK_PDPHP 226 292 #define HCLK_PDSDMMC 227 293 #define HCLK_SDMMC 228 294 #define HCLK_PDSDIO 229 295 #define HCLK_SDIO 230 296 #define HCLK_PDNVM 231 297 #define HCLK_EMMC 232 298 #define HCLK_NANDC 233 299 #define HCLK_SFC 234 300 #define HCLK_SFCXIP 235 301 #define HCLK_PDBUS 236 302 #define HCLK_USBHOST 237 303 #define HCLK_USBHOST_ARB 238 304 #define HCLK_PDNPU 239 305 #define HCLK_NPU 240 306 307 /* pclk */ 308 #define PCLK_CPUPVTM 245 309 #define PCLK_PDBUS 246 310 #define PCLK_DCF 247 311 #define PCLK_WDT 248 312 #define PCLK_MAILBOX 249 313 #define PCLK_UART0 250 314 #define PCLK_UART2 251 315 #define PCLK_UART3 252 316 #define PCLK_UART4 253 317 #define PCLK_UART5 254 318 #define PCLK_I2C1 255 319 #define PCLK_I2C3 256 320 #define PCLK_I2C4 257 321 #define PCLK_I2C5 258 322 #define PCLK_SPI1 259 323 #define PCLK_PWM2 261 324 #define PCLK_GPIO1 262 325 #define PCLK_GPIO2 263 326 #define PCLK_GPIO3 264 327 #define PCLK_GPIO4 265 328 #define PCLK_SARADC 266 329 #define PCLK_TIMER 267 330 #define PCLK_DECOM 268 331 #define PCLK_CAN 269 332 #define PCLK_NPU_TSADC 270 333 #define PCLK_CPU_TSADC 271 334 #define PCLK_ACDCDIG 272 335 #define PCLK_PDVO 273 336 #define PCLK_DSIHOST 274 337 #define PCLK_PDVI 275 338 #define PCLK_CSIHOST 276 339 #define PCLK_PDGMAC 277 340 #define PCLK_GMAC 278 341 #define PCLK_PDDDR 279 342 #define PCLK_DDR_MON 280 343 #define PCLK_PDNPU 281 344 #define PCLK_NPUPVTM 282 345 #define PCLK_PDTOP 283 346 #define PCLK_TOPCRU 284 347 #define PCLK_TOPGRF 285 348 #define PCLK_CPUEMADET 286 349 #define PCLK_DDRPHY 287 350 #define PCLK_DSIPHY 289 351 #define PCLK_CSIPHY0 290 352 #define PCLK_CSIPHY1 291 353 #define PCLK_USBPHY_HOST 292 354 #define PCLK_USBPHY_OTG 293 355 #define PCLK_OTP 294 356 357 #define CLK_NR_CLKS (PCLK_OTP + 1) 358 359 /* pmu soft-reset indices */ 360 361 /* pmu_cru_softrst_con0 */ 362 #define SRST_PDPMU_NIU_P 0 363 #define SRST_PMU_SGRF_P 1 364 #define SRST_PMU_SGRF_REMAP_P 2 365 #define SRST_I2C0_P 3 366 #define SRST_I2C0 4 367 #define SRST_I2C2_P 7 368 #define SRST_I2C2 8 369 #define SRST_UART1_P 9 370 #define SRST_UART1 10 371 #define SRST_PWM0_P 11 372 #define SRST_PWM0 12 373 #define SRST_PWM1_P 13 374 #define SRST_PWM1 14 375 #define SRST_DDR_FAIL_SAFE 15 376 377 /* pmu_cru_softrst_con1 */ 378 #define SRST_GPIO0_P 17 379 #define SRST_GPIO0_DB 18 380 #define SRST_SPI0_P 19 381 #define SRST_SPI0 20 382 #define SRST_PMUGRF_P 21 383 #define SRST_CHIPVEROTP_P 22 384 #define SRST_PMUPVTM 24 385 #define SRST_PMUPVTM_P 25 386 #define SRST_PMUCRU_P 30 387 388 /* soft-reset indices */ 389 390 /* cru_softrst_con0 */ 391 #define SRST_CORE0_PO 0 392 #define SRST_CORE1_PO 1 393 #define SRST_CORE2_PO 2 394 #define SRST_CORE3_PO 3 395 #define SRST_CORE0 4 396 #define SRST_CORE1 5 397 #define SRST_CORE2 6 398 #define SRST_CORE3 7 399 #define SRST_CORE0_DBG 8 400 #define SRST_CORE1_DBG 9 401 #define SRST_CORE2_DBG 10 402 #define SRST_CORE3_DBG 11 403 #define SRST_NL2 12 404 #define SRST_CORE_NIU_A 13 405 #define SRST_DBG_DAPLITE_P 14 406 #define SRST_DAPLITE_P 15 407 408 /* cru_softrst_con1 */ 409 #define SRST_PDBUS_NIU1_A 16 410 #define SRST_PDBUS_NIU1_H 17 411 #define SRST_PDBUS_NIU1_P 18 412 #define SRST_PDBUS_NIU2_A 19 413 #define SRST_PDBUS_NIU2_H 20 414 #define SRST_PDBUS_NIU3_A 21 415 #define SRST_PDBUS_NIU3_H 22 416 #define SRST_PDBUS_HOLD_NIU1_A 23 417 #define SRST_DBG_NIU_P 24 418 #define SRST_PDCORE_NIIU_H 25 419 #define SRST_MUC_NIU 26 420 #define SRST_DCF_A 29 421 #define SRST_DCF_P 30 422 #define SRST_SYSTEM_SRAM_A 31 423 424 /* cru_softrst_con2 */ 425 #define SRST_I2C1_P 32 426 #define SRST_I2C1 33 427 #define SRST_I2C3_P 34 428 #define SRST_I2C3 35 429 #define SRST_I2C4_P 36 430 #define SRST_I2C4 37 431 #define SRST_I2C5_P 38 432 #define SRST_I2C5 39 433 #define SRST_SPI1_P 40 434 #define SRST_SPI1 41 435 #define SRST_MCU_CORE 42 436 #define SRST_PWM2_P 44 437 #define SRST_PWM2 45 438 #define SRST_SPINLOCK_A 46 439 440 /* cru_softrst_con3 */ 441 #define SRST_UART0_P 48 442 #define SRST_UART0 49 443 #define SRST_UART2_P 50 444 #define SRST_UART2 51 445 #define SRST_UART3_P 52 446 #define SRST_UART3 53 447 #define SRST_UART4_P 54 448 #define SRST_UART4 55 449 #define SRST_UART5_P 56 450 #define SRST_UART5 57 451 #define SRST_WDT_P 58 452 #define SRST_SARADC_P 59 453 #define SRST_GRF_P 61 454 #define SRST_TIMER_P 62 455 #define SRST_MAILBOX_P 63 456 457 /* cru_softrst_con4 */ 458 #define SRST_TIMER0 64 459 #define SRST_TIMER1 65 460 #define SRST_TIMER2 66 461 #define SRST_TIMER3 67 462 #define SRST_TIMER4 68 463 #define SRST_TIMER5 69 464 #define SRST_INTMUX_P 70 465 #define SRST_GPIO1_P 72 466 #define SRST_GPIO1_DB 73 467 #define SRST_GPIO2_P 74 468 #define SRST_GPIO2_DB 75 469 #define SRST_GPIO3_P 76 470 #define SRST_GPIO3_DB 77 471 #define SRST_GPIO4_P 78 472 #define SRST_GPIO4_DB 79 473 474 /* cru_softrst_con5 */ 475 #define SRST_CAN_P 80 476 #define SRST_CAN 81 477 #define SRST_DECOM_A 85 478 #define SRST_DECOM_P 86 479 #define SRST_DECOM_D 87 480 #define SRST_PDCRYPTO_NIU_A 88 481 #define SRST_PDCRYPTO_NIU_H 89 482 #define SRST_CRYPTO_A 90 483 #define SRST_CRYPTO_H 91 484 #define SRST_CRYPTO_CORE 92 485 #define SRST_CRYPTO_PKA 93 486 #define SRST_SGRF_P 95 487 488 /* cru_softrst_con6 */ 489 #define SRST_PDAUDIO_NIU_H 96 490 #define SRST_PDAUDIO_NIU_P 97 491 #define SRST_I2S0_H 98 492 #define SRST_I2S0_TX_M 99 493 #define SRST_I2S0_RX_M 100 494 #define SRST_I2S1_H 101 495 #define SRST_I2S1_M 102 496 #define SRST_I2S2_H 103 497 #define SRST_I2S2_M 104 498 #define SRST_PDM_H 105 499 #define SRST_PDM_M 106 500 #define SRST_AUDPWM_H 107 501 #define SRST_AUDPWM 108 502 #define SRST_ACDCDIG_P 109 503 #define SRST_ACDCDIG 110 504 505 /* cru_softrst_con7 */ 506 #define SRST_PDVEPU_NIU_A 112 507 #define SRST_PDVEPU_NIU_H 113 508 #define SRST_VENC_A 114 509 #define SRST_VENC_H 115 510 #define SRST_VENC_CORE 116 511 #define SRST_PDVDEC_NIU_A 117 512 #define SRST_PDVDEC_NIU_H 118 513 #define SRST_VDEC_A 119 514 #define SRST_VDEC_H 120 515 #define SRST_VDEC_CORE 121 516 #define SRST_VDEC_CA 122 517 #define SRST_VDEC_HEVC_CA 123 518 #define SRST_PDJPEG_NIU_A 124 519 #define SRST_PDJPEG_NIU_H 125 520 #define SRST_JPEG_A 126 521 #define SRST_JPEG_H 127 522 523 /* cru_softrst_con8 */ 524 #define SRST_PDVO_NIU_A 128 525 #define SRST_PDVO_NIU_H 129 526 #define SRST_PDVO_NIU_P 130 527 #define SRST_RGA_A 131 528 #define SRST_RGA_H 132 529 #define SRST_RGA_CORE 133 530 #define SRST_VOP_A 134 531 #define SRST_VOP_H 135 532 #define SRST_VOP_D 136 533 #define SRST_TXBYTEHS_DSIHOST 137 534 #define SRST_DSIHOST_P 138 535 #define SRST_IEP_A 139 536 #define SRST_IEP_H 140 537 #define SRST_IEP_CORE 141 538 #define SRST_ISP_RX_P 142 539 540 /* cru_softrst_con9 */ 541 #define SRST_PDVI_NIU_A 144 542 #define SRST_PDVI_NIU_H 145 543 #define SRST_PDVI_NIU_P 146 544 #define SRST_ISP 147 545 #define SRST_CIF_A 148 546 #define SRST_CIF_H 149 547 #define SRST_CIF_D 150 548 #define SRST_CIF_P 151 549 #define SRST_CIF_I 152 550 #define SRST_CIF_RX_P 153 551 #define SRST_PDISPP_NIU_A 154 552 #define SRST_PDISPP_NIU_H 155 553 #define SRST_ISPP_A 156 554 #define SRST_ISPP_H 157 555 #define SRST_ISPP 158 556 #define SRST_CSIHOST_P 159 557 558 /* cru_softrst_con10 */ 559 #define SRST_PDPHPMID_NIU_A 160 560 #define SRST_PDPHPMID_NIU_H 161 561 #define SRST_PDNVM_NIU_H 163 562 #define SRST_SDMMC_H 164 563 #define SRST_SDIO_H 165 564 #define SRST_EMMC_H 166 565 #define SRST_SFC_H 167 566 #define SRST_SFCXIP_H 168 567 #define SRST_SFC 169 568 #define SRST_NANDC_H 170 569 #define SRST_NANDC 171 570 #define SRST_PDSDMMC_H 173 571 #define SRST_PDSDIO_H 174 572 573 /* cru_softrst_con11 */ 574 #define SRST_PDUSB_NIU_A 176 575 #define SRST_PDUSB_NIU_H 177 576 #define SRST_USBHOST_H 178 577 #define SRST_USBHOST_ARB_H 179 578 #define SRST_USBHOST_UTMI 180 579 #define SRST_USBOTG_A 181 580 #define SRST_USBPHY_OTG_P 182 581 #define SRST_USBPHY_HOST_P 183 582 #define SRST_USBPHYPOR_OTG 184 583 #define SRST_USBPHYPOR_HOST 185 584 #define SRST_PDGMAC_NIU_A 188 585 #define SRST_PDGMAC_NIU_P 189 586 #define SRST_GMAC_A 190 587 588 /* cru_softrst_con12 */ 589 #define SRST_DDR_DFICTL_P 193 590 #define SRST_DDR_MON_P 194 591 #define SRST_DDR_STANDBY_P 195 592 #define SRST_DDR_GRF_P 196 593 #define SRST_DDR_MSCH_P 197 594 #define SRST_DDR_SPLIT_A 198 595 #define SRST_DDR_MSCH 199 596 #define SRST_DDR_DFICTL 202 597 #define SRST_DDR_STANDBY 203 598 #define SRST_NPUMCU_NIU 205 599 #define SRST_DDRPHY_P 206 600 #define SRST_DDRPHY 207 601 602 /* cru_softrst_con13 */ 603 #define SRST_PDNPU_NIU_A 208 604 #define SRST_PDNPU_NIU_H 209 605 #define SRST_PDNPU_NIU_P 210 606 #define SRST_NPU_A 211 607 #define SRST_NPU_H 212 608 #define SRST_NPU 213 609 #define SRST_NPUPVTM_P 214 610 #define SRST_NPUPVTM 215 611 #define SRST_NPU_TSADC_P 216 612 #define SRST_NPU_TSADC 217 613 #define SRST_NPU_TSADCPHY 218 614 #define SRST_CIFLITE_A 220 615 #define SRST_CIFLITE_H 221 616 #define SRST_CIFLITE_D 222 617 #define SRST_CIFLITE_RX_P 223 618 619 /* cru_softrst_con14 */ 620 #define SRST_TOPNIU_P 224 621 #define SRST_TOPCRU_P 225 622 #define SRST_TOPGRF_P 226 623 #define SRST_CPUEMADET_P 227 624 #define SRST_CSIPHY0_P 228 625 #define SRST_CSIPHY1_P 229 626 #define SRST_DSIPHY_P 230 627 #define SRST_CPU_TSADC_P 232 628 #define SRST_CPU_TSADC 233 629 #define SRST_CPU_TSADCPHY 234 630 #define SRST_CPUPVTM_P 235 631 #define SRST_CPUPVTM 236 632 633 #endif 634