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Searched refs:PNAME (Results 1 - 19 of 19) sorted by relevance

/device/soc/rockchip/rk3566/vendor/drivers/clk/
H A Dclk-rk3568.c196 PNAME(mux_pll_p) = {"xin24m"};
197 PNAME(mux_usb480m_p) = {"xin24m", "usb480m_phy", "clk_rtc_32k"};
198 PNAME(clk_i2s0_8ch_tx_p) = {"clk_i2s0_8ch_tx_src", "clk_i2s0_8ch_tx_frac", "i2s0_mclkin", "xin_osc0_half"};
199 PNAME(clk_i2s0_8ch_rx_p) = {"clk_i2s0_8ch_rx_src", "clk_i2s0_8ch_rx_frac", "i2s0_mclkin", "xin_osc0_half"};
200 PNAME(clk_i2s1_8ch_tx_p) = {"clk_i2s1_8ch_tx_src", "clk_i2s1_8ch_tx_frac", "i2s1_mclkin", "xin_osc0_half"};
201 PNAME(clk_i2s1_8ch_rx_p) = {"clk_i2s1_8ch_rx_src", "clk_i2s1_8ch_rx_frac", "i2s1_mclkin", "xin_osc0_half"};
202 PNAME(clk_i2s2_2ch_p) = {"clk_i2s2_2ch_src", "clk_i2s2_2ch_frac", "i2s2_mclkin", "xin_osc0_half "};
203 PNAME(clk_i2s3_2ch_tx_p) = {"clk_i2s3_2ch_tx_src", "clk_i2s3_2ch_tx_frac", "i2s3_mclkin", "xin_osc0_half"};
204 PNAME(clk_i2s3_2ch_rx_p) = {"clk_i2s3_2ch_rx_src", "clk_i2s3_2ch_rx_frac", "i2s3_mclkin", "xin_osc0_half"};
205 PNAME(mclk_spdif_8ch_
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/device/soc/rockchip/common/sdk_linux/drivers/clk/rockchip/
H A Dclk-rk3308.c99 PNAME(mux_pll_p) = {"xin24m"};
100 PNAME(mux_usb480m_p) = {"xin24m", "usb480m_phy", "clk_rtc32k"};
101 PNAME(mux_dpll_vpll0_p) = {"dpll", "vpll0"};
102 PNAME(mux_dpll_vpll0_xin24m_p) = {"dpll", "vpll0", "xin24m"};
103 PNAME(mux_dpll_vpll0_vpll1_p) = {"dpll", "vpll0", "vpll1"};
104 PNAME(mux_dpll_vpll0_vpll1_xin24m_p) = {"dpll", "vpll0", "vpll1", "xin24m"};
105 PNAME(mux_dpll_vpll0_vpll1_usb480m_xin24m_p) = {"dpll", "vpll0", "vpll1", "usb480m", "xin24m"};
106 PNAME(mux_vpll0_vpll1_p) = {"vpll0", "vpll1"};
107 PNAME(mux_vpll0_vpll1_xin24m_p) = {"vpll0", "vpll1", "xin24m"};
108 PNAME(mux_uart0_
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H A Dclk-rk3399.c101 PNAME(mux_pll_p) = {"xin24m", "xin32k"};
103 PNAME(mux_ddrclk_p) = {"clk_ddrc_lpll_src", "clk_ddrc_bpll_src", "clk_ddrc_dpll_src", "clk_ddrc_gpll_src"};
105 PNAME(mux_pll_src_vpll_cpll_gpll_p) = {"vpll", "cpll", "gpll"};
106 PNAME(mux_pll_src_dmyvpll_cpll_gpll_p) = {"dummy_vpll", "cpll", "gpll"};
109 PNAME(mux_aclk_cci_p) = {"dummy_cpll", "gpll_aclk_cci_src", "npll_aclk_cci_src", "dummy_vpll"};
110 PNAME(mux_cci_trace_p) = {"dummy_cpll", "gpll_cci_trace"};
111 PNAME(mux_cs_p) = {"dummy_cpll", "gpll_cs", "npll_cs"};
112 PNAME(mux_aclk_perihp_p) = {"dummy_cpll", "gpll_aclk_perihp_src"};
114 PNAME(mux_pll_src_cpll_gpll_p) = {"dummy_cpll", "gpll"};
115 PNAME(mux_pll_src_cpll_gpll_npll_
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H A Dclk-px30.c104 PNAME(mux_pll_p) = {"xin24m"};
105 PNAME(mux_usb480m_p) = {"xin24m", "usb480m_phy", "clk_rtc32k_pmu"};
106 PNAME(mux_ddrphy_p) = {"dpll_ddr", "gpll_ddr"};
107 PNAME(mux_ddrstdby_p) = {"clk_ddrphy1x", "clk_stdby_2wrap"};
108 PNAME(mux_gpll_dmycpll_usb480m_npll_p) = {"gpll", "dummy_cpll", "usb480m", "npll"};
109 PNAME(mux_gpll_dmycpll_usb480m_dmynpll_p) = {"gpll", "dummy_cpll", "usb480m", "dummy_npll"};
110 PNAME(mux_cpll_npll_p) = {"cpll", "npll"};
111 PNAME(mux_npll_cpll_p) = {"npll", "cpll"};
112 PNAME(mux_gpll_cpll_p) = {"gpll", "dummy_cpll"};
113 PNAME(mux_gpll_npll_
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H A Dclk-rv1108.c111 PNAME(mux_pll_p) = {"xin24m", "xin24m"};
112 PNAME(mux_ddrphy_p) = {"dpll_ddr", "gpll_ddr", "apll_ddr"};
113 PNAME(mux_usb480m_pre_p) = {"usbphy", "xin24m"};
114 PNAME(mux_hdmiphy_phy_p) = {"hdmiphy", "xin24m"};
115 PNAME(mux_dclk_hdmiphy_pre_p) = {"dclk_hdmiphy_src_gpll", "dclk_hdmiphy_src_dpll"};
116 PNAME(mux_pll_src_4plls_p) = {"dpll", "gpll", "hdmiphy", "usb480m"};
117 PNAME(mux_pll_src_2plls_p) = {"dpll", "gpll"};
118 PNAME(mux_pll_src_apll_gpll_p) = {"apll", "gpll"};
119 PNAME(mux_aclk_peri_src_p) = {"aclk_peri_src_gpll", "aclk_peri_src_dpll"};
120 PNAME(mux_aclk_bus_src_
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H A Dclk-rk3328.c138 PNAME(mux_pll_p) = {"xin24m"};
140 PNAME(mux_2plls_p) = {"cpll", "gpll"};
141 PNAME(mux_gpll_cpll_p) = {"gpll", "cpll"};
142 PNAME(mux_cpll_gpll_apll_p) = {"cpll", "gpll", "apll"};
143 PNAME(mux_2plls_xin24m_p) = {"cpll", "gpll", "xin24m"};
144 PNAME(mux_2plls_hdmiphy_p) = {"cpll", "gpll", "dummy_hdmiphy"};
145 PNAME(mux_4plls_p) = {"cpll", "gpll", "dummy_hdmiphy", "usb480m"};
146 PNAME(mux_2plls_u480m_p) = {"cpll", "gpll", "usb480m"};
147 PNAME(mux_2plls_24m_u480m_p) = {"cpll", "gpll", "xin24m", "usb480m"};
149 PNAME(mux_ddrphy_
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H A Dclk-rk3368.c112 PNAME(mux_pll_p) = {"xin24m", "xin32k"};
113 PNAME(mux_ddrphy_p) = {"dpll_ddr", "gpll_ddr"};
114 PNAME(mux_cs_src_p) = {"apllb_cs", "aplll_cs", "gpll_cs"};
115 PNAME(mux_aclk_bus_src_p) = {"cpll_aclk_bus", "gpll_aclk_bus"};
117 PNAME(mux_pll_src_cpll_gpll_p) = {"cpll", "gpll"};
118 PNAME(mux_pll_src_cpll_gpll_npll_p) = {"cpll", "gpll", "dummy_npll"};
119 PNAME(mux_pll_src_dmycpll_dmygpll_npll_p) = {"dummy_cpll", "dummy_gpll", "npll"};
120 PNAME(mux_pll_src_npll_cpll_gpll_p) = {"dummy_npll", "cpll", "gpll"};
121 PNAME(mux_pll_src_cpll_gpll_usb_p) = {"cpll", "gpll", "usbphy_480m"};
122 PNAME(mux_pll_src_cpll_gpll_usb_usb_
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H A Dclk-rk3228.c126 PNAME(mux_pll_p) = {"clk_24m", "xin24m"};
128 PNAME(mux_ddrphy_p) = {"dpll_ddr", "gpll_ddr", "apll_ddr"};
129 PNAME(mux_usb480m_phy_p) = {"usb480m_phy0", "usb480m_phy1"};
130 PNAME(mux_usb480m_p) = {"usb480m_phy", "xin24m"};
131 PNAME(mux_hdmiphy_p) = {"hdmiphy_phy", "xin24m"};
132 PNAME(mux_aclk_cpu_src_p) = {"cpll_aclk_cpu", "gpll_aclk_cpu", "hdmiphy_aclk_cpu"};
134 PNAME(mux_pll_src_4plls_p) = {"cpll", "gpll", "hdmiphy", "usb480m"};
135 PNAME(mux_pll_src_3plls_p) = {"cpll", "gpll", "hdmiphy"};
136 PNAME(mux_pll_src_2plls_p) = {"cpll", "gpll"};
137 PNAME(mux_sclk_hdmi_cec_
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H A Dclk-rk3036.c120 PNAME(mux_pll_p) = {"xin24m", "xin24m"};
122 PNAME(mux_busclk_p) = {"apll", "dpll_cpu", "gpll_cpu"};
123 PNAME(mux_ddrphy_p) = {"dpll_ddr", "gpll_ddr"};
124 PNAME(mux_pll_src_3plls_p) = {"apll", "dpll", "gpll"};
125 PNAME(mux_timer_p) = {"xin24m", "pclk_peri_src"};
127 PNAME(mux_pll_src_apll_dpll_gpll_usb480m_p) = {"apll", "dpll", "gpll", "usb480m"};
128 PNAME(mux_pll_src_dmyapll_dpll_gpll_xin24_p) = {"dummy_apll", "dpll", "gpll", "xin24m"};
130 PNAME(mux_mmc_src_p) = {"apll", "dpll", "gpll", "xin24m"};
131 PNAME(mux_i2s_pre_p) = {"i2s_src", "i2s_frac", "ext_i2s", "xin12m"};
132 PNAME(mux_i2s_clkout_
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H A Dclk-rk3128.c125 PNAME(mux_pll_p) = {"clk_24m", "xin24m"};
127 PNAME(mux_ddrphy_p) = {"dpll_ddr", "gpll_div2_ddr"};
128 PNAME(mux_usb480m_p) = {"usb480m_phy", "xin24m"};
129 PNAME(mux_aclk_cpu_src_p) = {"cpll", "gpll", "gpll_div2", "gpll_div3"};
131 PNAME(mux_pll_src_5plls_p) = {"cpll", "gpll", "gpll_div2", "gpll_div3", "usb480m"};
132 PNAME(mux_pll_src_4plls_p) = {"cpll", "gpll", "gpll_div2", "usb480m"};
133 PNAME(mux_pll_src_3plls_p) = {"cpll", "gpll", "gpll_div2"};
135 PNAME(mux_aclk_peri_src_p) = {"gpll_peri", "cpll_peri", "gpll_div2_peri", "gpll_div3_peri"};
136 PNAME(mux_mmc_src_p) = {"cpll", "gpll", "gpll_div2", "xin24m"};
137 PNAME(mux_clk_cif_out_src_
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H A Dclk-rk3188.c193 PNAME(mux_pll_p) = {"xin24m", "xin32k"};
194 PNAME(mux_ddrphy_p) = {"dpll", "gpll_ddr"};
195 PNAME(mux_pll_src_gpll_cpll_p) = {"gpll", "cpll"};
196 PNAME(mux_pll_src_cpll_gpll_p) = {"cpll", "gpll"};
197 PNAME(mux_aclk_cpu_p) = {"apll", "gpll"};
198 PNAME(mux_sclk_cif0_p) = {"cif0_pre", "xin24m"};
199 PNAME(mux_sclk_i2s0_p) = {"i2s0_pre", "i2s0_frac", "xin12m"};
200 PNAME(mux_sclk_spdif_p) = {"spdif_pre", "spdif_frac", "xin12m"};
201 PNAME(mux_sclk_uart0_p) = {"uart0_pre", "uart0_frac", "xin24m"};
202 PNAME(mux_sclk_uart1_
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H A Dclk-rk3288.c143 PNAME(mux_pll_p) = {"xin24m", "xin32k"};
144 PNAME(mux_ddrphy_p) = {"dpll_ddr", "gpll_ddr"};
145 PNAME(mux_aclk_cpu_src_p) = {"cpll_aclk_cpu", "gpll_aclk_cpu"};
147 PNAME(mux_pll_src_cpll_gpll_p) = {"cpll", "gpll"};
148 PNAME(mux_pll_src_npll_cpll_gpll_p) = {"npll", "cpll", "gpll"};
149 PNAME(mux_pll_src_cpll_gpll_npll_p) = {"cpll", "gpll", "npll"};
150 PNAME(mux_pll_src_cpll_gpll_usb480m_p) = {"cpll", "gpll", "unstable:usbphy480m_src"};
151 PNAME(mux_pll_src_cpll_gll_usb_npll_p) = {"cpll", "gpll", "unstable:usbphy480m_src", "npll"};
153 PNAME(mux_mmc_src_p) = {"cpll", "gpll", "xin24m", "xin24m"};
154 PNAME(mux_i2s_pre_
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H A Dclk.h467 #define PNAME(x) static const char *const x[] __initconst macro
/device/soc/rockchip/common/vendor/drivers/clk/
H A Dclk-rk1808.c123 PNAME(mux_pll_p) = {"xin24m", "xin32k"};
124 PNAME(mux_usb480m_p) = {"xin24m", "usb480m_phy", "xin32k"};
125 PNAME(mux_gpll_cpll_p) = {"gpll", "cpll"};
126 PNAME(mux_gpll_cpll_apll_p) = {"gpll", "cpll", "apll"};
127 PNAME(mux_npu_p) = {"clk_npu_div", "clk_npu_np5"};
128 PNAME(mux_ddr_p) = {"dpll_ddr", "gpll_ddr"};
129 PNAME(mux_cpll_gpll_npll_p) = {"cpll", "gpll", "npll"};
130 PNAME(mux_gpll_cpll_npll_p) = {"gpll", "cpll", "npll"};
131 PNAME(mux_dclk_vopraw_p) = {"dclk_vopraw_src", "dclk_vopraw_frac", "xin24m"};
132 PNAME(mux_dclk_voplite_
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/device/soc/rockchip/rk3588/kernel/drivers/clk/rockchip/
H A Dclk-rk3588.c420 PNAME(mux_pll_p) = { "xin24m", "xin32k" };
421 PNAME(mux_armclkl_p) = { "xin24m", "gpll", "lpll" };
422 PNAME(mux_armclkb01_p) = { "xin24m", "gpll", "b0pll",};
423 PNAME(mux_armclkb23_p) = { "xin24m", "gpll", "b1pll",};
424 PNAME(b0pll_b1pll_lpll_gpll_p) = { "b0pll", "b1pll", "lpll", "gpll" };
425 PNAME(gpll_24m_p) = { "gpll", "xin24m" };
426 PNAME(gpll_aupll_p) = { "gpll", "aupll" };
427 PNAME(gpll_lpll_p) = { "gpll", "lpll" };
428 PNAME(gpll_cpll_p) = { "gpll", "cpll" };
429 PNAME(gpll_spll_
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H A Dclk.h563 #define PNAME(x) static const char *const x[] __initconst macro
/device/soc/rockchip/common/sdk_linux/drivers/gpu/drm/rockchip/
H A Drockchip_vop2_clk.c20 #define PNAME(x) static const char *const x[] macro
63 PNAME(mux_port0_dclk_src_p) = {"dclk0", "dclk1"};
64 PNAME(mux_port2_dclk_src_p) = {"dclk2", "dclk1"};
65 PNAME(mux_dp_pixclk_p) = {"dclk_out0", "dclk_out1", "dclk_out2"};
66 PNAME(mux_hdmi_edp_clk_src_p) = {"dclk0", "dclk1", "dclk2"};
67 PNAME(mux_mipi_clk_src_p) = {"dclk_out1", "dclk_out2", "dclk_out3"};
68 PNAME(mux_dsc_8k_clk_src_p) = {"dclk0", "dclk1", "dclk2", "dclk3"};
69 PNAME(mux_dsc_4k_clk_src_p) = {"dclk0", "dclk1", "dclk2", "dclk3"};
/device/soc/rockchip/rk3588/kernel/drivers/gpu/drm/rockchip/
H A Drockchip_vop2_clk.c19 #define PNAME(x) static const char *const x[] macro
74 PNAME(mux_port0_dclk_src_p) = { "dclk0", "dclk1" };
75 PNAME(mux_port2_dclk_src_p) = { "dclk2", "dclk1" };
76 PNAME(mux_dp_pixclk_p) = { "dclk_out0", "dclk_out1", "dclk_out2" };
77 PNAME(mux_hdmi_edp_clk_src_p) = { "dclk0", "dclk1", "dclk2" };
78 PNAME(mux_mipi_clk_src_p) = { "dclk_out1", "dclk_out2", "dclk_out3" };
79 PNAME(mux_dsc_8k_clk_src_p) = { "dclk0", "dclk1", "dclk2", "dclk3" };
80 PNAME(mux_dsc_4k_clk_src_p) = { "dclk0", "dclk1", "dclk2", "dclk3" };
/device/soc/rockchip/rk3588/kernel/drivers/soc/rockchip/
H A Dclk.h563 #define PNAME(x) static const char *const x[] __initconst macro

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