clk-rk1808.c - OpenGrok cross reference for /device/soc/rockchip/common/vendor/drivers/clk/clk-rk1808.c

Lines Matching refs:PNAME
123 PNAME(mux_pll_p) = {"xin24m", "xin32k"};
124 PNAME(mux_usb480m_p) = {"xin24m", "usb480m_phy", "xin32k"};
125 PNAME(mux_gpll_cpll_p) = {"gpll", "cpll"};
126 PNAME(mux_gpll_cpll_apll_p) = {"gpll", "cpll", "apll"};
127 PNAME(mux_npu_p) = {"clk_npu_div", "clk_npu_np5"};
128 PNAME(mux_ddr_p) = {"dpll_ddr", "gpll_ddr"};
129 PNAME(mux_cpll_gpll_npll_p) = {"cpll", "gpll", "npll"};
130 PNAME(mux_gpll_cpll_npll_p) = {"gpll", "cpll", "npll"};
131 PNAME(mux_dclk_vopraw_p) = {"dclk_vopraw_src", "dclk_vopraw_frac", "xin24m"};
132 PNAME(mux_dclk_voplite_p) = {"dclk_voplite_src", "dclk_voplite_frac", "xin24m"};
133 PNAME(mux_24m_npll_gpll_usb480m_p) = {"xin24m", "npll", "gpll", "usb480m"};
134 PNAME(mux_usb3_otg0_suspend_p) = {"xin32k", "xin24m"};
135 PNAME(mux_pcie_aux_p) = {"xin24m", "clk_pcie_src"};
136 PNAME(mux_gpll_cpll_npll_24m_p) = {"gpll", "cpll", "npll", "xin24m"};
137 PNAME(mux_sdio_p) = {"clk_sdio_div", "clk_sdio_div50"};
138 PNAME(mux_sdmmc_p) = {"clk_sdmmc_div", "clk_sdmmc_div50"};
139 PNAME(mux_emmc_p) = {"clk_emmc_div", "clk_emmc_div50"};
140 PNAME(mux_cpll_npll_ppll_p) = {"cpll", "npll", "ppll"};
141 PNAME(mux_gmac_p) = {"clk_gmac_src", "gmac_clkin"};
142 PNAME(mux_gmac_rgmii_speed_p) = {"clk_gmac_tx_src", "clk_gmac_tx_src", "clk_gmac_tx_div50", "clk_gmac_tx_div5"};
143 PNAME(mux_gmac_rmii_speed_p) = {"clk_gmac_rx_div20", "clk_gmac_rx_div2"};
144 PNAME(mux_gmac_rx_tx_p) = {"clk_gmac_rgmii_speed", "clk_gmac_rmii_speed"};
145 PNAME(mux_gpll_usb480m_cpll_npll_p) = {"gpll", "usb480m", "cpll", "npll"};
146 PNAME(mux_uart1_p) = {"clk_uart1_src", "clk_uart1_np5", "clk_uart1_frac", "xin24m"};
147 PNAME(mux_uart2_p) = {"clk_uart2_src", "clk_uart2_np5", "clk_uart2_frac", "xin24m"};
148 PNAME(mux_uart3_p) = {"clk_uart3_src", "clk_uart3_np5", "clk_uart3_frac", "xin24m"};
149 PNAME(mux_uart4_p) = {"clk_uart4_src", "clk_uart4_np5", "clk_uart4_frac", "xin24m"};
150 PNAME(mux_uart5_p) = {"clk_uart5_src", "clk_uart5_np5", "clk_uart5_frac", "xin24m"};
151 PNAME(mux_uart6_p) = {"clk_uart6_src", "clk_uart6_np5", "clk_uart6_frac", "xin24m"};
152 PNAME(mux_uart7_p) = {"clk_uart7_src", "clk_uart7_np5", "clk_uart7_frac", "xin24m"};
153 PNAME(mux_gpll_xin24m_p) = {"gpll", "xin24m"};
154 PNAME(mux_gpll_cpll_xin24m_p) = {"gpll", "cpll", "xin24m"};
155 PNAME(mux_gpll_xin24m_cpll_npll_p) = {"gpll", "xin24m", "cpll", "npll"};
156 PNAME(mux_pdm_p) = {"clk_pdm_src", "clk_pdm_frac"};
157 PNAME(mux_i2s0_8ch_tx_p) = {"clk_i2s0_8ch_tx_src", "clk_i2s0_8ch_tx_frac", "mclk_i2s0_8ch_in", "xin12m"};
158 PNAME(mux_i2s0_8ch_tx_rx_p) = {"clk_i2s0_8ch_tx_mux", "clk_i2s0_8ch_rx_mux"};
159 PNAME(mux_i2s0_8ch_tx_out_p) = {"clk_i2s0_8ch_tx", "xin12m", "clk_i2s0_8ch_rx"};
160 PNAME(mux_i2s0_8ch_rx_p) = {"clk_i2s0_8ch_rx_src", "clk_i2s0_8ch_rx_frac", "mclk_i2s0_8ch_in", "xin12m"};
161 PNAME(mux_i2s0_8ch_rx_tx_p) = {"clk_i2s0_8ch_rx_mux", "clk_i2s0_8ch_tx_mux"};
162 PNAME(mux_i2s0_8ch_rx_out_p) = {"clk_i2s0_8ch_rx", "xin12m", "clk_i2s0_8ch_tx"};
163 PNAME(mux_i2s1_2ch_p) = {"clk_i2s1_2ch_src", "clk_i2s1_2ch_frac", "mclk_i2s1_2ch_in", "xin12m"};
164 PNAME(mux_i2s1_2ch_out_p) = {"clk_i2s1_2ch", "xin12m"};
165 PNAME(mux_rtc32k_pmu_p) = {"xin32k", "pmu_pvtm_32k", "clk_rtc32k_frac"};
166 PNAME(mux_wifi_pmu_p) = {"xin24m", "clk_wifi_pmu_src"};
167 PNAME(mux_gpll_usb480m_cpll_ppll_p) = {"gpll", "usb480m", "cpll", "ppll"};
168 PNAME(mux_uart0_pmu_p) = {"clk_uart0_pmu_src", "clk_uart0_np5", "clk_uart0_frac", "xin24m"};
169 PNAME(mux_usbphy_ref_p) = {"xin24m", "clk_ref24m_pmu"};
170 PNAME(mux_mipidsiphy_ref_p) = {"xin24m", "clk_ref24m_pmu"};
171 PNAME(mux_pciephy_ref_p) = {"xin24m", "clk_pciephy_src"};
172 PNAME(mux_ppll_xin24m_p) = {"ppll", "xin24m"};
173 PNAME(mux_xin24m_32k_p) = {"xin24m", "xin32k"};
174 PNAME(mux_clk_32k_ioe_p) = {"clk_rtc32k_pmu", "xin32k"};