| /device/soc/rockchip/common/kernel/drivers/net/wireless/rockchip_wlan/rkwifi/bcmdhd_wifi6/include/ |
| H A D | sbsdpcmdev.h | 241 #define SDA_F1_REG_SPACE 0x300 /* sdioAccess F1 core-specific register space */
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| H A D | sbconfig.h | 232 #define SBTMCH_EM_MASK 0x300 /**< sb error mode */
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| H A D | pcicfg.h | 261 #define PCIE_BARCOHERENTACCEN_MASK 0x300
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| H A D | pcie_core.h | 265 pcie_devdmaregs_t h2d2_dmaregs; /* 0x300 - 0x33c */
520 #define PCIEADDR_PROT_MASK 0x300
1082 #define LTR_FINAL_MASK 0x300
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| H A D | sbchipc.h | 328 uint8 uart0data; /* 0x300 */
1346 #define NFLASH 0x300
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| /device/soc/hisilicon/hi3861v100/sdk_liteos/platform/drivers/cipher/ |
| H A D | drv_pke_common.h | 49 #define PKE_PRAM 0x300
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| /device/soc/rockchip/common/vendor/drivers/gpu/arm/bifrost/gpu/ |
| H A D | mali_kbase_gpu_regmap.h | 156 #define COHERENCY_FEATURES 0x300 /* (RO) Coherency features present */
|
| /device/soc/hisilicon/hi3516dv300/sdk_linux/drv/interdrv/common/cipher/include/ |
| H A D | drv_cipher_kapi.h | 76 #define HI_BASE_ERR_BASE_RSA (HI_BASE_ERR_BASE + 0x300)
|
| /device/soc/rockchip/common/vendor/drivers/video/rockchip/mpp/ |
| H A D | mpp_common.h | 140 MPP_CMD_POLL_BASE = 0x300,
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| /device/soc/rockchip/common/vendor/drivers/gpu/arm/midgard/ |
| H A D | mali_midg_regmap.h | 184 #define COHERENCY_FEATURES 0x300 /* (RO) Coherency features present */
|
| /device/soc/rockchip/common/sdk_linux/drivers/gpu/drm/bridge/analogix/ |
| H A D | analogix_dp_reg.h | 57 #define ANALOGIX_DP_SPD_HB2 0x300
|
| /device/soc/rockchip/common/kernel/drivers/gpu/arm/midgard/ |
| H A D | mali_midg_regmap.h | 191 #define COHERENCY_FEATURES 0x300 /* (RO) Coherency features present */
|
| /device/soc/rockchip/rk3588/kernel/include/uapi/gpu/arm/bifrost/gpu/ |
| H A D | mali_kbase_gpu_regmap.h | 175 #define COHERENCY_FEATURES 0x300 /* (RO) Coherency features present */
|
| /device/soc/rockchip/rk3588/kernel/drivers/video/rockchip/mpp/ |
| H A D | mpp_common.h | 112 MPP_CMD_POLL_BASE = 0x300,
|
| /device/soc/hisilicon/common/platform/i2c/ |
| H A D | i2c_hi35xx.c | 254 addr = ((msg->addr & 0x300) << 1) | 0xf000; in Hi35xxI2cSetAddr()
|
| /device/soc/rockchip/common/kernel/drivers/gpu/arm/bifrost/backend/gpu/ |
| H A D | mali_kbase_model_dummy.c | 272 .thread_max_threads = 0x300,
285 .thread_max_threads = 0x300,
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| /device/soc/rockchip/rk3588/kernel/drivers/pci/controller/dwc/ |
| H A D | pcie-dw-rockchip.c | 76 #define PCIE_DMA_RD_CTRL_LO 0x300
111 #define PCIE_CLIENT_LTSSM_STATUS 0x300
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| /device/soc/rockchip/common/sdk_linux/drivers/gpu/drm/ |
| H A D | drm_edid.c | 2476 vsize = 0x300; in drm_mode_std()
2489 if (hsize == 0x556 && vsize == 0x300 && vrefresh_rate == 0x3c) { in drm_mode_std()
2490 mode = drm_cvt_mode(dev, 0x556, 0x300, vrefresh_rate, 0, 0, false); in drm_mode_std()
2815 if (mode->hdisplay == 0x558 && mode->vdisplay == 0x300) { in drm_mode_fixup_1366x768()
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| /device/soc/rockchip/rk3588/kernel/drivers/clk/rockchip/ |
| H A D | clk-rk3588.c | 2392 0x300, false); in rk3588_dump_cru()
2396 0x300, false); in rk3588_dump_cru()
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| /device/soc/rockchip/common/vendor/drivers/phy/ |
| H A D | phy-rockchip-csi2-dphy-hw.c | 74 #define CSI2_DCPHY_DATA_LANE2_ENABLE (0x300)
|
| H A D | phy-rockchip-mipi-rx.c | 177 #define RV1126_CSI_DPHY_LVDS_MODE 0x300
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| /device/soc/rockchip/rk3588/kernel/drivers/phy/rockchip/ |
| H A D | phy-rockchip-csi2-dphy-hw.c | 75 #define CSI2_DCPHY_DATA_LANE2_ENABLE (0x300)
|
| H A D | phy-rockchip-mipi-rx.c | 201 #define RV1126_CSI_DPHY_LVDS_MODE 0x300
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| /device/soc/hisilicon/hi3861v100/sdk_liteos/platform/os/Huawei_LiteOS/components/lib/libc/musl/include/ |
| H A D | elf.h | 665 #define NT_S390_HIGH_GPRS 0x300
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| /device/soc/rockchip/common/vendor/drivers/pci/ |
| H A D | pcie-dw-rockchip.c | 94 #define PCIE_CLIENT_LTSSM_STATUS 0x300
|