1 /* 2 * 3 * (C) COPYRIGHT 2010-2017 ARM Limited. All rights reserved. 4 * 5 * This program is free software and is provided to you under the terms of the 6 * GNU General Public License version 2 as published by the Free Software 7 * Foundation, and any use by you of this program is subject to the terms 8 * of such GNU licence. 9 * 10 * A copy of the licence is included with the program, and can also be obtained 11 * from Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, 12 * Boston, MA 02110-1301, USA. 13 * 14 */ 15 16 17 18 #ifndef _MIDGARD_REGMAP_H_ 19 #define _MIDGARD_REGMAP_H_ 20 21 #include "mali_midg_coherency.h" 22 #include "mali_kbase_gpu_id.h" 23 24 /* 25 * Begin Register Offsets 26 */ 27 28 #define GPU_CONTROL_BASE 0x0000 29 #define GPU_CONTROL_REG(r) (GPU_CONTROL_BASE + (r)) 30 #define GPU_ID 0x000 /* (RO) GPU and revision identifier */ 31 #define L2_FEATURES 0x004 /* (RO) Level 2 cache features */ 32 #define SUSPEND_SIZE 0x008 /* (RO) Fixed-function suspend buffer 33 size */ 34 #define TILER_FEATURES 0x00C /* (RO) Tiler Features */ 35 #define MEM_FEATURES 0x010 /* (RO) Memory system features */ 36 #define MMU_FEATURES 0x014 /* (RO) MMU features */ 37 #define AS_PRESENT 0x018 /* (RO) Address space slots present */ 38 #define JS_PRESENT 0x01C /* (RO) Job slots present */ 39 #define GPU_IRQ_RAWSTAT 0x020 /* (RW) */ 40 #define GPU_IRQ_CLEAR 0x024 /* (WO) */ 41 #define GPU_IRQ_MASK 0x028 /* (RW) */ 42 #define GPU_IRQ_STATUS 0x02C /* (RO) */ 43 44 /* IRQ flags */ 45 #define GPU_FAULT (1 << 0) /* A GPU Fault has occurred */ 46 #define MULTIPLE_GPU_FAULTS (1 << 7) /* More than one GPU Fault occurred. */ 47 #define RESET_COMPLETED (1 << 8) /* Set when a reset has completed. Intended to use with SOFT_RESET 48 commands which may take time. */ 49 #define POWER_CHANGED_SINGLE (1 << 9) /* Set when a single core has finished powering up or down. */ 50 #define POWER_CHANGED_ALL (1 << 10) /* Set when all cores have finished powering up or down 51 and the power manager is idle. */ 52 53 #define PRFCNT_SAMPLE_COMPLETED (1 << 16) /* Set when a performance count sample has completed. */ 54 #define CLEAN_CACHES_COMPLETED (1 << 17) /* Set when a cache clean operation has completed. */ 55 56 #define GPU_IRQ_REG_ALL (GPU_FAULT | MULTIPLE_GPU_FAULTS | RESET_COMPLETED \ 57 | POWER_CHANGED_ALL | PRFCNT_SAMPLE_COMPLETED) 58 59 #define GPU_COMMAND 0x030 /* (WO) */ 60 #define GPU_STATUS 0x034 /* (RO) */ 61 #define LATEST_FLUSH 0x038 /* (RO) */ 62 63 #define GROUPS_L2_COHERENT (1 << 0) /* Cores groups are l2 coherent */ 64 #define GPU_DBGEN (1 << 8) /* DBGEN wire status */ 65 66 #define GPU_FAULTSTATUS 0x03C /* (RO) GPU exception type and fault status */ 67 #define GPU_FAULTADDRESS_LO 0x040 /* (RO) GPU exception fault address, low word */ 68 #define GPU_FAULTADDRESS_HI 0x044 /* (RO) GPU exception fault address, high word */ 69 70 #define PWR_KEY 0x050 /* (WO) Power manager key register */ 71 #define PWR_OVERRIDE0 0x054 /* (RW) Power manager override settings */ 72 #define PWR_OVERRIDE1 0x058 /* (RW) Power manager override settings */ 73 74 #define PRFCNT_BASE_LO 0x060 /* (RW) Performance counter memory region base address, low word */ 75 #define PRFCNT_BASE_HI 0x064 /* (RW) Performance counter memory region base address, high word */ 76 #define PRFCNT_CONFIG 0x068 /* (RW) Performance counter configuration */ 77 #define PRFCNT_JM_EN 0x06C /* (RW) Performance counter enable flags for Job Manager */ 78 #define PRFCNT_SHADER_EN 0x070 /* (RW) Performance counter enable flags for shader cores */ 79 #define PRFCNT_TILER_EN 0x074 /* (RW) Performance counter enable flags for tiler */ 80 #define PRFCNT_MMU_L2_EN 0x07C /* (RW) Performance counter enable flags for MMU/L2 cache */ 81 82 #define CYCLE_COUNT_LO 0x090 /* (RO) Cycle counter, low word */ 83 #define CYCLE_COUNT_HI 0x094 /* (RO) Cycle counter, high word */ 84 #define TIMESTAMP_LO 0x098 /* (RO) Global time stamp counter, low word */ 85 #define TIMESTAMP_HI 0x09C /* (RO) Global time stamp counter, high word */ 86 87 #define THREAD_MAX_THREADS 0x0A0 /* (RO) Maximum number of threads per core */ 88 #define THREAD_MAX_WORKGROUP_SIZE 0x0A4 /* (RO) Maximum workgroup size */ 89 #define THREAD_MAX_BARRIER_SIZE 0x0A8 /* (RO) Maximum threads waiting at a barrier */ 90 #define THREAD_FEATURES 0x0AC /* (RO) Thread features */ 91 92 #define TEXTURE_FEATURES_0 0x0B0 /* (RO) Support flags for indexed texture formats 0..31 */ 93 #define TEXTURE_FEATURES_1 0x0B4 /* (RO) Support flags for indexed texture formats 32..63 */ 94 #define TEXTURE_FEATURES_2 0x0B8 /* (RO) Support flags for indexed texture formats 64..95 */ 95 96 #define TEXTURE_FEATURES_REG(n) GPU_CONTROL_REG(TEXTURE_FEATURES_0 + ((n) << 2)) 97 98 #define JS0_FEATURES 0x0C0 /* (RO) Features of job slot 0 */ 99 #define JS1_FEATURES 0x0C4 /* (RO) Features of job slot 1 */ 100 #define JS2_FEATURES 0x0C8 /* (RO) Features of job slot 2 */ 101 #define JS3_FEATURES 0x0CC /* (RO) Features of job slot 3 */ 102 #define JS4_FEATURES 0x0D0 /* (RO) Features of job slot 4 */ 103 #define JS5_FEATURES 0x0D4 /* (RO) Features of job slot 5 */ 104 #define JS6_FEATURES 0x0D8 /* (RO) Features of job slot 6 */ 105 #define JS7_FEATURES 0x0DC /* (RO) Features of job slot 7 */ 106 #define JS8_FEATURES 0x0E0 /* (RO) Features of job slot 8 */ 107 #define JS9_FEATURES 0x0E4 /* (RO) Features of job slot 9 */ 108 #define JS10_FEATURES 0x0E8 /* (RO) Features of job slot 10 */ 109 #define JS11_FEATURES 0x0EC /* (RO) Features of job slot 11 */ 110 #define JS12_FEATURES 0x0F0 /* (RO) Features of job slot 12 */ 111 #define JS13_FEATURES 0x0F4 /* (RO) Features of job slot 13 */ 112 #define JS14_FEATURES 0x0F8 /* (RO) Features of job slot 14 */ 113 #define JS15_FEATURES 0x0FC /* (RO) Features of job slot 15 */ 114 115 #define JS_FEATURES_REG(n) GPU_CONTROL_REG(JS0_FEATURES + ((n) << 2)) 116 117 #define SHADER_PRESENT_LO 0x100 /* (RO) Shader core present bitmap, low word */ 118 #define SHADER_PRESENT_HI 0x104 /* (RO) Shader core present bitmap, high word */ 119 120 #define TILER_PRESENT_LO 0x110 /* (RO) Tiler core present bitmap, low word */ 121 #define TILER_PRESENT_HI 0x114 /* (RO) Tiler core present bitmap, high word */ 122 123 #define L2_PRESENT_LO 0x120 /* (RO) Level 2 cache present bitmap, low word */ 124 #define L2_PRESENT_HI 0x124 /* (RO) Level 2 cache present bitmap, high word */ 125 126 #define STACK_PRESENT_LO 0xE00 /* (RO) Core stack present bitmap, low word */ 127 #define STACK_PRESENT_HI 0xE04 /* (RO) Core stack present bitmap, high word */ 128 129 130 #define SHADER_READY_LO 0x140 /* (RO) Shader core ready bitmap, low word */ 131 #define SHADER_READY_HI 0x144 /* (RO) Shader core ready bitmap, high word */ 132 133 #define TILER_READY_LO 0x150 /* (RO) Tiler core ready bitmap, low word */ 134 #define TILER_READY_HI 0x154 /* (RO) Tiler core ready bitmap, high word */ 135 136 #define L2_READY_LO 0x160 /* (RO) Level 2 cache ready bitmap, low word */ 137 #define L2_READY_HI 0x164 /* (RO) Level 2 cache ready bitmap, high word */ 138 139 #define STACK_READY_LO 0xE10 /* (RO) Core stack ready bitmap, low word */ 140 #define STACK_READY_HI 0xE14 /* (RO) Core stack ready bitmap, high word */ 141 142 143 #define SHADER_PWRON_LO 0x180 /* (WO) Shader core power on bitmap, low word */ 144 #define SHADER_PWRON_HI 0x184 /* (WO) Shader core power on bitmap, high word */ 145 146 #define TILER_PWRON_LO 0x190 /* (WO) Tiler core power on bitmap, low word */ 147 #define TILER_PWRON_HI 0x194 /* (WO) Tiler core power on bitmap, high word */ 148 149 #define L2_PWRON_LO 0x1A0 /* (WO) Level 2 cache power on bitmap, low word */ 150 #define L2_PWRON_HI 0x1A4 /* (WO) Level 2 cache power on bitmap, high word */ 151 152 #define STACK_PWRON_LO 0xE20 /* (RO) Core stack power on bitmap, low word */ 153 #define STACK_PWRON_HI 0xE24 /* (RO) Core stack power on bitmap, high word */ 154 155 156 #define SHADER_PWROFF_LO 0x1C0 /* (WO) Shader core power off bitmap, low word */ 157 #define SHADER_PWROFF_HI 0x1C4 /* (WO) Shader core power off bitmap, high word */ 158 159 #define TILER_PWROFF_LO 0x1D0 /* (WO) Tiler core power off bitmap, low word */ 160 #define TILER_PWROFF_HI 0x1D4 /* (WO) Tiler core power off bitmap, high word */ 161 162 #define L2_PWROFF_LO 0x1E0 /* (WO) Level 2 cache power off bitmap, low word */ 163 #define L2_PWROFF_HI 0x1E4 /* (WO) Level 2 cache power off bitmap, high word */ 164 165 #define STACK_PWROFF_LO 0xE30 /* (RO) Core stack power off bitmap, low word */ 166 #define STACK_PRWOFF_HI 0xE34 /* (RO) Core stack power off bitmap, high word */ 167 168 169 #define SHADER_PWRTRANS_LO 0x200 /* (RO) Shader core power transition bitmap, low word */ 170 #define SHADER_PWRTRANS_HI 0x204 /* (RO) Shader core power transition bitmap, high word */ 171 172 #define TILER_PWRTRANS_LO 0x210 /* (RO) Tiler core power transition bitmap, low word */ 173 #define TILER_PWRTRANS_HI 0x214 /* (RO) Tiler core power transition bitmap, high word */ 174 175 #define L2_PWRTRANS_LO 0x220 /* (RO) Level 2 cache power transition bitmap, low word */ 176 #define L2_PWRTRANS_HI 0x224 /* (RO) Level 2 cache power transition bitmap, high word */ 177 178 #define STACK_PWRTRANS_LO 0xE40 /* (RO) Core stack power transition bitmap, low word */ 179 #define STACK_PRWTRANS_HI 0xE44 /* (RO) Core stack power transition bitmap, high word */ 180 181 182 #define SHADER_PWRACTIVE_LO 0x240 /* (RO) Shader core active bitmap, low word */ 183 #define SHADER_PWRACTIVE_HI 0x244 /* (RO) Shader core active bitmap, high word */ 184 185 #define TILER_PWRACTIVE_LO 0x250 /* (RO) Tiler core active bitmap, low word */ 186 #define TILER_PWRACTIVE_HI 0x254 /* (RO) Tiler core active bitmap, high word */ 187 188 #define L2_PWRACTIVE_LO 0x260 /* (RO) Level 2 cache active bitmap, low word */ 189 #define L2_PWRACTIVE_HI 0x264 /* (RO) Level 2 cache active bitmap, high word */ 190 191 #define COHERENCY_FEATURES 0x300 /* (RO) Coherency features present */ 192 #define COHERENCY_ENABLE 0x304 /* (RW) Coherency enable */ 193 194 #define JM_CONFIG 0xF00 /* (RW) Job Manager configuration register (Implementation specific register) */ 195 #define SHADER_CONFIG 0xF04 /* (RW) Shader core configuration settings (Implementation specific register) */ 196 #define TILER_CONFIG 0xF08 /* (RW) Tiler core configuration settings (Implementation specific register) */ 197 #define L2_MMU_CONFIG 0xF0C /* (RW) Configuration of the L2 cache and MMU (Implementation specific register) */ 198 199 #define JOB_CONTROL_BASE 0x1000 200 201 #define JOB_CONTROL_REG(r) (JOB_CONTROL_BASE + (r)) 202 203 #define JOB_IRQ_RAWSTAT 0x000 /* Raw interrupt status register */ 204 #define JOB_IRQ_CLEAR 0x004 /* Interrupt clear register */ 205 #define JOB_IRQ_MASK 0x008 /* Interrupt mask register */ 206 #define JOB_IRQ_STATUS 0x00C /* Interrupt status register */ 207 #define JOB_IRQ_JS_STATE 0x010 /* status==active and _next == busy snapshot from last JOB_IRQ_CLEAR */ 208 #define JOB_IRQ_THROTTLE 0x014 /* cycles to delay delivering an interrupt externally. The JOB_IRQ_STATUS is NOT affected by this, just the delivery of the interrupt. */ 209 210 #define JOB_SLOT0 0x800 /* Configuration registers for job slot 0 */ 211 #define JOB_SLOT1 0x880 /* Configuration registers for job slot 1 */ 212 #define JOB_SLOT2 0x900 /* Configuration registers for job slot 2 */ 213 #define JOB_SLOT3 0x980 /* Configuration registers for job slot 3 */ 214 #define JOB_SLOT4 0xA00 /* Configuration registers for job slot 4 */ 215 #define JOB_SLOT5 0xA80 /* Configuration registers for job slot 5 */ 216 #define JOB_SLOT6 0xB00 /* Configuration registers for job slot 6 */ 217 #define JOB_SLOT7 0xB80 /* Configuration registers for job slot 7 */ 218 #define JOB_SLOT8 0xC00 /* Configuration registers for job slot 8 */ 219 #define JOB_SLOT9 0xC80 /* Configuration registers for job slot 9 */ 220 #define JOB_SLOT10 0xD00 /* Configuration registers for job slot 10 */ 221 #define JOB_SLOT11 0xD80 /* Configuration registers for job slot 11 */ 222 #define JOB_SLOT12 0xE00 /* Configuration registers for job slot 12 */ 223 #define JOB_SLOT13 0xE80 /* Configuration registers for job slot 13 */ 224 #define JOB_SLOT14 0xF00 /* Configuration registers for job slot 14 */ 225 #define JOB_SLOT15 0xF80 /* Configuration registers for job slot 15 */ 226 227 #define JOB_SLOT_REG(n, r) (JOB_CONTROL_REG(JOB_SLOT0 + ((n) << 7)) + (r)) 228 229 #define JS_HEAD_LO 0x00 /* (RO) Job queue head pointer for job slot n, low word */ 230 #define JS_HEAD_HI 0x04 /* (RO) Job queue head pointer for job slot n, high word */ 231 #define JS_TAIL_LO 0x08 /* (RO) Job queue tail pointer for job slot n, low word */ 232 #define JS_TAIL_HI 0x0C /* (RO) Job queue tail pointer for job slot n, high word */ 233 #define JS_AFFINITY_LO 0x10 /* (RO) Core affinity mask for job slot n, low word */ 234 #define JS_AFFINITY_HI 0x14 /* (RO) Core affinity mask for job slot n, high word */ 235 #define JS_CONFIG 0x18 /* (RO) Configuration settings for job slot n */ 236 #define JS_XAFFINITY 0x1C /* (RO) Extended affinity mask for job 237 slot n */ 238 239 #define JS_COMMAND 0x20 /* (WO) Command register for job slot n */ 240 #define JS_STATUS 0x24 /* (RO) Status register for job slot n */ 241 242 #define JS_HEAD_NEXT_LO 0x40 /* (RW) Next job queue head pointer for job slot n, low word */ 243 #define JS_HEAD_NEXT_HI 0x44 /* (RW) Next job queue head pointer for job slot n, high word */ 244 245 #define JS_AFFINITY_NEXT_LO 0x50 /* (RW) Next core affinity mask for job slot n, low word */ 246 #define JS_AFFINITY_NEXT_HI 0x54 /* (RW) Next core affinity mask for job slot n, high word */ 247 #define JS_CONFIG_NEXT 0x58 /* (RW) Next configuration settings for job slot n */ 248 #define JS_XAFFINITY_NEXT 0x5C /* (RW) Next extended affinity mask for 249 job slot n */ 250 251 #define JS_COMMAND_NEXT 0x60 /* (RW) Next command register for job slot n */ 252 253 #define JS_FLUSH_ID_NEXT 0x70 /* (RW) Next job slot n cache flush ID */ 254 255 #define MEMORY_MANAGEMENT_BASE 0x2000 256 #define MMU_REG(r) (MEMORY_MANAGEMENT_BASE + (r)) 257 258 #define MMU_IRQ_RAWSTAT 0x000 /* (RW) Raw interrupt status register */ 259 #define MMU_IRQ_CLEAR 0x004 /* (WO) Interrupt clear register */ 260 #define MMU_IRQ_MASK 0x008 /* (RW) Interrupt mask register */ 261 #define MMU_IRQ_STATUS 0x00C /* (RO) Interrupt status register */ 262 263 #define MMU_AS0 0x400 /* Configuration registers for address space 0 */ 264 #define MMU_AS1 0x440 /* Configuration registers for address space 1 */ 265 #define MMU_AS2 0x480 /* Configuration registers for address space 2 */ 266 #define MMU_AS3 0x4C0 /* Configuration registers for address space 3 */ 267 #define MMU_AS4 0x500 /* Configuration registers for address space 4 */ 268 #define MMU_AS5 0x540 /* Configuration registers for address space 5 */ 269 #define MMU_AS6 0x580 /* Configuration registers for address space 6 */ 270 #define MMU_AS7 0x5C0 /* Configuration registers for address space 7 */ 271 #define MMU_AS8 0x600 /* Configuration registers for address space 8 */ 272 #define MMU_AS9 0x640 /* Configuration registers for address space 9 */ 273 #define MMU_AS10 0x680 /* Configuration registers for address space 10 */ 274 #define MMU_AS11 0x6C0 /* Configuration registers for address space 11 */ 275 #define MMU_AS12 0x700 /* Configuration registers for address space 12 */ 276 #define MMU_AS13 0x740 /* Configuration registers for address space 13 */ 277 #define MMU_AS14 0x780 /* Configuration registers for address space 14 */ 278 #define MMU_AS15 0x7C0 /* Configuration registers for address space 15 */ 279 280 #define MMU_AS_REG(n, r) (MMU_REG(MMU_AS0 + ((n) << 6)) + (r)) 281 282 #define AS_TRANSTAB_LO 0x00 /* (RW) Translation Table Base Address for address space n, low word */ 283 #define AS_TRANSTAB_HI 0x04 /* (RW) Translation Table Base Address for address space n, high word */ 284 #define AS_MEMATTR_LO 0x08 /* (RW) Memory attributes for address space n, low word. */ 285 #define AS_MEMATTR_HI 0x0C /* (RW) Memory attributes for address space n, high word. */ 286 #define AS_LOCKADDR_LO 0x10 /* (RW) Lock region address for address space n, low word */ 287 #define AS_LOCKADDR_HI 0x14 /* (RW) Lock region address for address space n, high word */ 288 #define AS_COMMAND 0x18 /* (WO) MMU command register for address space n */ 289 #define AS_FAULTSTATUS 0x1C /* (RO) MMU fault status register for address space n */ 290 #define AS_FAULTADDRESS_LO 0x20 /* (RO) Fault Address for address space n, low word */ 291 #define AS_FAULTADDRESS_HI 0x24 /* (RO) Fault Address for address space n, high word */ 292 #define AS_STATUS 0x28 /* (RO) Status flags for address space n */ 293 294 295 /* (RW) Translation table configuration for address space n, low word */ 296 #define AS_TRANSCFG_LO 0x30 297 /* (RW) Translation table configuration for address space n, high word */ 298 #define AS_TRANSCFG_HI 0x34 299 /* (RO) Secondary fault address for address space n, low word */ 300 #define AS_FAULTEXTRA_LO 0x38 301 /* (RO) Secondary fault address for address space n, high word */ 302 #define AS_FAULTEXTRA_HI 0x3C 303 304 /* End Register Offsets */ 305 306 /* 307 * MMU_IRQ_RAWSTAT register values. Values are valid also for 308 MMU_IRQ_CLEAR, MMU_IRQ_MASK, MMU_IRQ_STATUS registers. 309 */ 310 311 #define MMU_PAGE_FAULT_FLAGS 16 312 313 /* Macros returning a bitmask to retrieve page fault or bus error flags from 314 * MMU registers */ 315 #define MMU_PAGE_FAULT(n) (1UL << (n)) 316 #define MMU_BUS_ERROR(n) (1UL << ((n) + MMU_PAGE_FAULT_FLAGS)) 317 318 /* 319 * Begin LPAE MMU TRANSTAB register values 320 */ 321 #define AS_TRANSTAB_LPAE_ADDR_SPACE_MASK 0xfffff000 322 #define AS_TRANSTAB_LPAE_ADRMODE_UNMAPPED (0u << 0) 323 #define AS_TRANSTAB_LPAE_ADRMODE_IDENTITY (1u << 1) 324 #define AS_TRANSTAB_LPAE_ADRMODE_TABLE (3u << 0) 325 #define AS_TRANSTAB_LPAE_READ_INNER (1u << 2) 326 #define AS_TRANSTAB_LPAE_SHARE_OUTER (1u << 4) 327 328 #define AS_TRANSTAB_LPAE_ADRMODE_MASK 0x00000003 329 330 /* 331 * Begin AARCH64 MMU TRANSTAB register values 332 */ 333 #define MMU_HW_OUTA_BITS 40 334 #define AS_TRANSTAB_BASE_MASK ((1ULL << MMU_HW_OUTA_BITS) - (1ULL << 4)) 335 336 /* 337 * Begin MMU STATUS register values 338 */ 339 #define AS_STATUS_AS_ACTIVE 0x01 340 341 #define AS_FAULTSTATUS_EXCEPTION_CODE_MASK (0x7<<3) 342 #define AS_FAULTSTATUS_EXCEPTION_CODE_TRANSLATION_FAULT (0x0<<3) 343 #define AS_FAULTSTATUS_EXCEPTION_CODE_PERMISSION_FAULT (0x1<<3) 344 #define AS_FAULTSTATUS_EXCEPTION_CODE_TRANSTAB_BUS_FAULT (0x2<<3) 345 #define AS_FAULTSTATUS_EXCEPTION_CODE_ACCESS_FLAG (0x3<<3) 346 347 #define AS_FAULTSTATUS_EXCEPTION_CODE_ADDRESS_SIZE_FAULT (0x4<<3) 348 #define AS_FAULTSTATUS_EXCEPTION_CODE_MEMORY_ATTRIBUTES_FAULT (0x5<<3) 349 350 #define AS_FAULTSTATUS_ACCESS_TYPE_MASK (0x3<<8) 351 #define AS_FAULTSTATUS_ACCESS_TYPE_ATOMIC (0x0<<8) 352 #define AS_FAULTSTATUS_ACCESS_TYPE_EX (0x1<<8) 353 #define AS_FAULTSTATUS_ACCESS_TYPE_READ (0x2<<8) 354 #define AS_FAULTSTATUS_ACCESS_TYPE_WRITE (0x3<<8) 355 356 /* 357 * Begin MMU TRANSCFG register values 358 */ 359 360 #define AS_TRANSCFG_ADRMODE_LEGACY 0 361 #define AS_TRANSCFG_ADRMODE_UNMAPPED 1 362 #define AS_TRANSCFG_ADRMODE_IDENTITY 2 363 #define AS_TRANSCFG_ADRMODE_AARCH64_4K 6 364 #define AS_TRANSCFG_ADRMODE_AARCH64_64K 8 365 366 #define AS_TRANSCFG_ADRMODE_MASK 0xF 367 368 369 /* 370 * Begin TRANSCFG register values 371 */ 372 #define AS_TRANSCFG_PTW_MEMATTR_MASK (3 << 24) 373 #define AS_TRANSCFG_PTW_MEMATTR_NON_CACHEABLE (1 << 24) 374 #define AS_TRANSCFG_PTW_MEMATTR_WRITE_BACK (2 << 24) 375 376 #define AS_TRANSCFG_PTW_SH_MASK ((3 << 28)) 377 #define AS_TRANSCFG_PTW_SH_OS (2 << 28) 378 #define AS_TRANSCFG_PTW_SH_IS (3 << 28) 379 380 /* 381 * Begin Command Values 382 */ 383 384 /* JS_COMMAND register commands */ 385 #define JS_COMMAND_NOP 0x00 /* NOP Operation. Writing this value is ignored */ 386 #define JS_COMMAND_START 0x01 /* Start processing a job chain. Writing this value is ignored */ 387 #define JS_COMMAND_SOFT_STOP 0x02 /* Gently stop processing a job chain */ 388 #define JS_COMMAND_HARD_STOP 0x03 /* Rudely stop processing a job chain */ 389 #define JS_COMMAND_SOFT_STOP_0 0x04 /* Execute SOFT_STOP if JOB_CHAIN_FLAG is 0 */ 390 #define JS_COMMAND_HARD_STOP_0 0x05 /* Execute HARD_STOP if JOB_CHAIN_FLAG is 0 */ 391 #define JS_COMMAND_SOFT_STOP_1 0x06 /* Execute SOFT_STOP if JOB_CHAIN_FLAG is 1 */ 392 #define JS_COMMAND_HARD_STOP_1 0x07 /* Execute HARD_STOP if JOB_CHAIN_FLAG is 1 */ 393 394 #define JS_COMMAND_MASK 0x07 /* Mask of bits currently in use by the HW */ 395 396 /* AS_COMMAND register commands */ 397 #define AS_COMMAND_NOP 0x00 /* NOP Operation */ 398 #define AS_COMMAND_UPDATE 0x01 /* Broadcasts the values in AS_TRANSTAB and ASn_MEMATTR to all MMUs */ 399 #define AS_COMMAND_LOCK 0x02 /* Issue a lock region command to all MMUs */ 400 #define AS_COMMAND_UNLOCK 0x03 /* Issue a flush region command to all MMUs */ 401 #define AS_COMMAND_FLUSH 0x04 /* Flush all L2 caches then issue a flush region command to all MMUs 402 (deprecated - only for use with T60x) */ 403 #define AS_COMMAND_FLUSH_PT 0x04 /* Flush all L2 caches then issue a flush region command to all MMUs */ 404 #define AS_COMMAND_FLUSH_MEM 0x05 /* Wait for memory accesses to complete, flush all the L1s cache then 405 flush all L2 caches then issue a flush region command to all MMUs */ 406 407 /* Possible values of JS_CONFIG and JS_CONFIG_NEXT registers */ 408 #define JS_CONFIG_START_FLUSH_NO_ACTION (0u << 0) 409 #define JS_CONFIG_START_FLUSH_CLEAN (1u << 8) 410 #define JS_CONFIG_START_FLUSH_CLEAN_INVALIDATE (3u << 8) 411 #define JS_CONFIG_START_MMU (1u << 10) 412 #define JS_CONFIG_JOB_CHAIN_FLAG (1u << 11) 413 #define JS_CONFIG_END_FLUSH_NO_ACTION JS_CONFIG_START_FLUSH_NO_ACTION 414 #define JS_CONFIG_END_FLUSH_CLEAN (1u << 12) 415 #define JS_CONFIG_END_FLUSH_CLEAN_INVALIDATE (3u << 12) 416 #define JS_CONFIG_ENABLE_FLUSH_REDUCTION (1u << 14) 417 #define JS_CONFIG_DISABLE_DESCRIPTOR_WR_BK (1u << 15) 418 #define JS_CONFIG_THREAD_PRI(n) ((n) << 16) 419 420 /* JS_XAFFINITY register values */ 421 #define JS_XAFFINITY_XAFFINITY_ENABLE (1u << 0) 422 #define JS_XAFFINITY_TILER_ENABLE (1u << 8) 423 #define JS_XAFFINITY_CACHE_ENABLE (1u << 16) 424 425 /* JS_STATUS register values */ 426 427 /* NOTE: Please keep this values in sync with enum base_jd_event_code in mali_base_kernel.h. 428 * The values are separated to avoid dependency of userspace and kernel code. 429 */ 430 431 /* Group of values representing the job status insead a particular fault */ 432 #define JS_STATUS_NO_EXCEPTION_BASE 0x00 433 #define JS_STATUS_INTERRUPTED (JS_STATUS_NO_EXCEPTION_BASE + 0x02) /* 0x02 means INTERRUPTED */ 434 #define JS_STATUS_STOPPED (JS_STATUS_NO_EXCEPTION_BASE + 0x03) /* 0x03 means STOPPED */ 435 #define JS_STATUS_TERMINATED (JS_STATUS_NO_EXCEPTION_BASE + 0x04) /* 0x04 means TERMINATED */ 436 437 /* General fault values */ 438 #define JS_STATUS_FAULT_BASE 0x40 439 #define JS_STATUS_CONFIG_FAULT (JS_STATUS_FAULT_BASE) /* 0x40 means CONFIG FAULT */ 440 #define JS_STATUS_POWER_FAULT (JS_STATUS_FAULT_BASE + 0x01) /* 0x41 means POWER FAULT */ 441 #define JS_STATUS_READ_FAULT (JS_STATUS_FAULT_BASE + 0x02) /* 0x42 means READ FAULT */ 442 #define JS_STATUS_WRITE_FAULT (JS_STATUS_FAULT_BASE + 0x03) /* 0x43 means WRITE FAULT */ 443 #define JS_STATUS_AFFINITY_FAULT (JS_STATUS_FAULT_BASE + 0x04) /* 0x44 means AFFINITY FAULT */ 444 #define JS_STATUS_BUS_FAULT (JS_STATUS_FAULT_BASE + 0x08) /* 0x48 means BUS FAULT */ 445 446 /* Instruction or data faults */ 447 #define JS_STATUS_INSTRUCTION_FAULT_BASE 0x50 448 #define JS_STATUS_INSTR_INVALID_PC (JS_STATUS_INSTRUCTION_FAULT_BASE) /* 0x50 means INSTR INVALID PC */ 449 #define JS_STATUS_INSTR_INVALID_ENC (JS_STATUS_INSTRUCTION_FAULT_BASE + 0x01) /* 0x51 means INSTR INVALID ENC */ 450 #define JS_STATUS_INSTR_TYPE_MISMATCH (JS_STATUS_INSTRUCTION_FAULT_BASE + 0x02) /* 0x52 means INSTR TYPE MISMATCH */ 451 #define JS_STATUS_INSTR_OPERAND_FAULT (JS_STATUS_INSTRUCTION_FAULT_BASE + 0x03) /* 0x53 means INSTR OPERAND FAULT */ 452 #define JS_STATUS_INSTR_TLS_FAULT (JS_STATUS_INSTRUCTION_FAULT_BASE + 0x04) /* 0x54 means INSTR TLS FAULT */ 453 #define JS_STATUS_INSTR_BARRIER_FAULT (JS_STATUS_INSTRUCTION_FAULT_BASE + 0x05) /* 0x55 means INSTR BARRIER FAULT */ 454 #define JS_STATUS_INSTR_ALIGN_FAULT (JS_STATUS_INSTRUCTION_FAULT_BASE + 0x06) /* 0x56 means INSTR ALIGN FAULT */ 455 /* NOTE: No fault with 0x57 code defined in spec. */ 456 #define JS_STATUS_DATA_INVALID_FAULT (JS_STATUS_INSTRUCTION_FAULT_BASE + 0x08) /* 0x58 means DATA INVALID FAULT */ 457 #define JS_STATUS_TILE_RANGE_FAULT (JS_STATUS_INSTRUCTION_FAULT_BASE + 0x09) /* 0x59 means TILE RANGE FAULT */ 458 #define JS_STATUS_ADDRESS_RANGE_FAULT (JS_STATUS_INSTRUCTION_FAULT_BASE + 0x0A) /* 0x5A means ADDRESS RANGE FAULT */ 459 460 /* Other faults */ 461 #define JS_STATUS_MEMORY_FAULT_BASE 0x60 462 #define JS_STATUS_OUT_OF_MEMORY (JS_STATUS_MEMORY_FAULT_BASE) /* 0x60 means OUT OF MEMORY */ 463 #define JS_STATUS_UNKNOWN 0x7F /* 0x7F means UNKNOWN */ 464 465 /* GPU_COMMAND values */ 466 #define GPU_COMMAND_NOP 0x00 /* No operation, nothing happens */ 467 #define GPU_COMMAND_SOFT_RESET 0x01 /* Stop all external bus interfaces, and then reset the entire GPU. */ 468 #define GPU_COMMAND_HARD_RESET 0x02 /* Immediately reset the entire GPU. */ 469 #define GPU_COMMAND_PRFCNT_CLEAR 0x03 /* Clear all performance counters, setting them all to zero. */ 470 #define GPU_COMMAND_PRFCNT_SAMPLE 0x04 /* Sample all performance counters, writing them out to memory */ 471 #define GPU_COMMAND_CYCLE_COUNT_START 0x05 /* Starts the cycle counter, and system timestamp propagation */ 472 #define GPU_COMMAND_CYCLE_COUNT_STOP 0x06 /* Stops the cycle counter, and system timestamp propagation */ 473 #define GPU_COMMAND_CLEAN_CACHES 0x07 /* Clean all caches */ 474 #define GPU_COMMAND_CLEAN_INV_CACHES 0x08 /* Clean and invalidate all caches */ 475 #define GPU_COMMAND_SET_PROTECTED_MODE 0x09 /* Places the GPU in protected mode */ 476 477 /* End Command Values */ 478 479 /* GPU_STATUS values */ 480 #define GPU_STATUS_PRFCNT_ACTIVE (1 << 2) /* Set if the performance counters are active. */ 481 #define GPU_STATUS_PROTECTED_MODE_ACTIVE (1 << 7) /* Set if protected mode is active */ 482 483 /* PRFCNT_CONFIG register values */ 484 #define PRFCNT_CONFIG_MODE_SHIFT 0 /* Counter mode position. */ 485 #define PRFCNT_CONFIG_AS_SHIFT 4 /* Address space bitmap position. */ 486 #define PRFCNT_CONFIG_SETSELECT_SHIFT 8 /* Set select position. */ 487 488 #define PRFCNT_CONFIG_MODE_OFF 0 /* The performance counters are disabled. */ 489 #define PRFCNT_CONFIG_MODE_MANUAL 1 /* The performance counters are enabled, but are only written out when a PRFCNT_SAMPLE command is issued using the GPU_COMMAND register. */ 490 #define PRFCNT_CONFIG_MODE_TILE 2 /* The performance counters are enabled, and are written out each time a tile finishes rendering. */ 491 492 /* AS<n>_MEMATTR values: */ 493 /* Use GPU implementation-defined caching policy. */ 494 #define AS_MEMATTR_IMPL_DEF_CACHE_POLICY 0x88ull 495 /* The attribute set to force all resources to be cached. */ 496 #define AS_MEMATTR_FORCE_TO_CACHE_ALL 0x8Full 497 /* Inner write-alloc cache setup, no outer caching */ 498 #define AS_MEMATTR_WRITE_ALLOC 0x8Dull 499 500 /* Set to implementation defined, outer caching */ 501 #define AS_MEMATTR_AARCH64_OUTER_IMPL_DEF 0x88ull 502 /* Set to write back memory, outer caching */ 503 #define AS_MEMATTR_AARCH64_OUTER_WA 0x8Dull 504 505 /* Use GPU implementation-defined caching policy. */ 506 #define AS_MEMATTR_LPAE_IMPL_DEF_CACHE_POLICY 0x48ull 507 /* The attribute set to force all resources to be cached. */ 508 #define AS_MEMATTR_LPAE_FORCE_TO_CACHE_ALL 0x4Full 509 /* Inner write-alloc cache setup, no outer caching */ 510 #define AS_MEMATTR_LPAE_WRITE_ALLOC 0x4Dull 511 /* Set to implementation defined, outer caching */ 512 #define AS_MEMATTR_LPAE_OUTER_IMPL_DEF 0x88ull 513 /* Set to write back memory, outer caching */ 514 #define AS_MEMATTR_LPAE_OUTER_WA 0x8Dull 515 516 /* Symbol for default MEMATTR to use */ 517 518 /* Default is - HW implementation defined caching */ 519 #define AS_MEMATTR_INDEX_DEFAULT 0 520 #define AS_MEMATTR_INDEX_DEFAULT_ACE 3 521 522 /* HW implementation defined caching */ 523 #define AS_MEMATTR_INDEX_IMPL_DEF_CACHE_POLICY 0 524 /* Force cache on */ 525 #define AS_MEMATTR_INDEX_FORCE_TO_CACHE_ALL 1 526 /* Write-alloc */ 527 #define AS_MEMATTR_INDEX_WRITE_ALLOC 2 528 /* Outer coherent, inner implementation defined policy */ 529 #define AS_MEMATTR_INDEX_OUTER_IMPL_DEF 3 530 /* Outer coherent, write alloc inner */ 531 #define AS_MEMATTR_INDEX_OUTER_WA 4 532 533 /* JS<n>_FEATURES register */ 534 535 #define JS_FEATURE_NULL_JOB (1u << 1) 536 #define JS_FEATURE_SET_VALUE_JOB (1u << 2) 537 #define JS_FEATURE_CACHE_FLUSH_JOB (1u << 3) 538 #define JS_FEATURE_COMPUTE_JOB (1u << 4) 539 #define JS_FEATURE_VERTEX_JOB (1u << 5) 540 #define JS_FEATURE_GEOMETRY_JOB (1u << 6) 541 #define JS_FEATURE_TILER_JOB (1u << 7) 542 #define JS_FEATURE_FUSED_JOB (1u << 8) 543 #define JS_FEATURE_FRAGMENT_JOB (1u << 9) 544 545 /* End JS<n>_FEATURES register */ 546 547 /* L2_MMU_CONFIG register */ 548 #define L2_MMU_CONFIG_ALLOW_SNOOP_DISPARITY_SHIFT (23) 549 #define L2_MMU_CONFIG_ALLOW_SNOOP_DISPARITY (0x1 << L2_MMU_CONFIG_ALLOW_SNOOP_DISPARITY_SHIFT) 550 #define L2_MMU_CONFIG_LIMIT_EXTERNAL_READS_SHIFT (24) 551 #define L2_MMU_CONFIG_LIMIT_EXTERNAL_READS (0x3 << L2_MMU_CONFIG_LIMIT_EXTERNAL_READS_SHIFT) 552 #define L2_MMU_CONFIG_LIMIT_EXTERNAL_READS_OCTANT (0x1 << L2_MMU_CONFIG_LIMIT_EXTERNAL_READS_SHIFT) 553 #define L2_MMU_CONFIG_LIMIT_EXTERNAL_READS_QUARTER (0x2 << L2_MMU_CONFIG_LIMIT_EXTERNAL_READS_SHIFT) 554 #define L2_MMU_CONFIG_LIMIT_EXTERNAL_READS_HALF (0x3 << L2_MMU_CONFIG_LIMIT_EXTERNAL_READS_SHIFT) 555 556 #define L2_MMU_CONFIG_LIMIT_EXTERNAL_WRITES_SHIFT (26) 557 #define L2_MMU_CONFIG_LIMIT_EXTERNAL_WRITES (0x3 << L2_MMU_CONFIG_LIMIT_EXTERNAL_WRITES_SHIFT) 558 #define L2_MMU_CONFIG_LIMIT_EXTERNAL_WRITES_OCTANT (0x1 << L2_MMU_CONFIG_LIMIT_EXTERNAL_WRITES_SHIFT) 559 #define L2_MMU_CONFIG_LIMIT_EXTERNAL_WRITES_QUARTER (0x2 << L2_MMU_CONFIG_LIMIT_EXTERNAL_WRITES_SHIFT) 560 #define L2_MMU_CONFIG_LIMIT_EXTERNAL_WRITES_HALF (0x3 << L2_MMU_CONFIG_LIMIT_EXTERNAL_WRITES_SHIFT) 561 /* End L2_MMU_CONFIG register */ 562 563 /* THREAD_* registers */ 564 565 /* THREAD_FEATURES IMPLEMENTATION_TECHNOLOGY values */ 566 #define IMPLEMENTATION_UNSPECIFIED 0 567 #define IMPLEMENTATION_SILICON 1 568 #define IMPLEMENTATION_FPGA 2 569 #define IMPLEMENTATION_MODEL 3 570 571 /* Default values when registers are not supported by the implemented hardware */ 572 #define THREAD_MT_DEFAULT 256 573 #define THREAD_MWS_DEFAULT 256 574 #define THREAD_MBS_DEFAULT 256 575 #define THREAD_MR_DEFAULT 1024 576 #define THREAD_MTQ_DEFAULT 4 577 #define THREAD_MTGS_DEFAULT 10 578 579 /* End THREAD_* registers */ 580 581 /* SHADER_CONFIG register */ 582 583 #define SC_ALT_COUNTERS (1ul << 3) 584 #define SC_OVERRIDE_FWD_PIXEL_KILL (1ul << 4) 585 #define SC_SDC_DISABLE_OQ_DISCARD (1ul << 6) 586 #define SC_LS_ALLOW_ATTR_TYPES (1ul << 16) 587 #define SC_LS_PAUSEBUFFER_DISABLE (1ul << 16) 588 #define SC_LS_ATTR_CHECK_DISABLE (1ul << 18) 589 #define SC_ENABLE_TEXGRD_FLAGS (1ul << 25) 590 /* End SHADER_CONFIG register */ 591 592 /* TILER_CONFIG register */ 593 594 #define TC_CLOCK_GATE_OVERRIDE (1ul << 0) 595 596 /* End TILER_CONFIG register */ 597 598 /* JM_CONFIG register */ 599 600 #define JM_TIMESTAMP_OVERRIDE (1ul << 0) 601 #define JM_CLOCK_GATE_OVERRIDE (1ul << 1) 602 #define JM_JOB_THROTTLE_ENABLE (1ul << 2) 603 #define JM_JOB_THROTTLE_LIMIT_SHIFT (3) 604 #define JM_MAX_JOB_THROTTLE_LIMIT (0x3F) 605 #define JM_FORCE_COHERENCY_FEATURES_SHIFT (2) 606 #define JM_IDVS_GROUP_SIZE_SHIFT (16) 607 #define JM_MAX_IDVS_GROUP_SIZE (0x3F) 608 /* End JM_CONFIG register */ 609 610 611 #endif /* _MIDGARD_REGMAP_H_ */ 612