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Searched refs:x200 (Results 176 - 200 of 3683) sorted by relevance

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/third_party/mesa3d/src/etnaviv/drm-shim/
H A D	etnaviv_noop.c	`89 [ETNAVIV_PARAM_GPU_VERTEX_OUTPUT_BUFFER_SIZE] = 0x200, 91 [ETNAVIV_PARAM_GPU_INSTRUCTION_COUNT] = 0x200, 145 [ETNAVIV_PARAM_GPU_INSTRUCTION_COUNT] = 0x200,`
/third_party/mesa3d/src/panfrost/bifrost/test/
H A D	test-pack-formats.cpp	`246 { 0x84008d0586100043, 0x200 }, in TEST_F() 249 { 0x1600dd878320400, 0x200 }, in TEST_F() 250 { 0x49709c1b08308900, 0x200 }, in TEST_F()`
/third_party/toybox/toys/pending/
H A D	tr.c	`45 TT.map[set1[k]] = TT.map[set1[k]]\|0x200; in map_translation() 47 TT.map[set2[k]] = TT.map[set2[k]]\|0x200; in map_translation() 223 if (FLAG(s) && ((ch & 0x200) && prev == ch)) continue; in print_map()`
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/include/asic_reg/dce/
H A D	dce_11_2_sh_mask.h	129 #define DCPG_INTERRUPT_STATUS__DCFE4_POWER_DOWN_INT_OCCURRED_MASK 0x200 165 #define DCPG_INTERRUPT_CONTROL__DCFE2_POWER_UP_INT_CLEAR_MASK 0x200 363 #define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_MASK 0x200 607 #define CRTC_TRIGA_CNTL__CRTC_TRIGA_INPUT_STATUS_MASK 0x200 631 #define CRTC_TRIGB_CNTL__CRTC_TRIGB_INPUT_STATUS_MASK 0x200 827 #define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_TYPE_MASK 0x200 1059 #define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE_MASK 0x200 1415 #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x200 1499 #define DCCG_DS_CNTL__DCCG_DS_ENABLED_STATUS_MASK 0x200 1615 #define DCCG_GATE_DISABLE_CNTL2__SYMCLKLPB_FE_GATE_DISABLE_MASK 0x200 [all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/include/asic_reg/dce/
H A D	dce_11_2_sh_mask.h	129 #define DCPG_INTERRUPT_STATUS__DCFE4_POWER_DOWN_INT_OCCURRED_MASK 0x200 165 #define DCPG_INTERRUPT_CONTROL__DCFE2_POWER_UP_INT_CLEAR_MASK 0x200 363 #define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_MASK 0x200 607 #define CRTC_TRIGA_CNTL__CRTC_TRIGA_INPUT_STATUS_MASK 0x200 631 #define CRTC_TRIGB_CNTL__CRTC_TRIGB_INPUT_STATUS_MASK 0x200 827 #define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_TYPE_MASK 0x200 1059 #define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE_MASK 0x200 1415 #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x200 1499 #define DCCG_DS_CNTL__DCCG_DS_ENABLED_STATUS_MASK 0x200 1615 #define DCCG_GATE_DISABLE_CNTL2__SYMCLKLPB_FE_GATE_DISABLE_MASK 0x200 [all...]
/kernel/linux/linux-5.10/drivers/misc/habanalabs/include/gaudi/asic_reg/
H A D	mme0_qm_masks.h	`150 #define MME0_QM_GLBL_STS1_CP_FENCE1_OVF_ERR_MASK 0x200 180 #define MME0_QM_GLBL_STS1_4_CP_FENCE1_OVF_ERR_MASK 0x200 212 #define MME0_QM_GLBL_MSG_EN_CP_FENCE1_OVF_ERR_MASK 0x200 242 #define MME0_QM_GLBL_MSG_EN_4_CP_FENCE1_OVF_ERR_MASK 0x200 714 #define MME0_QM_CGM_STS_AXI_IDLE_MASK 0x200`
H A D	dma0_qm_masks.h	`150 #define DMA0_QM_GLBL_STS1_CP_FENCE1_OVF_ERR_MASK 0x200 180 #define DMA0_QM_GLBL_STS1_4_CP_FENCE1_OVF_ERR_MASK 0x200 212 #define DMA0_QM_GLBL_MSG_EN_CP_FENCE1_OVF_ERR_MASK 0x200 242 #define DMA0_QM_GLBL_MSG_EN_4_CP_FENCE1_OVF_ERR_MASK 0x200 714 #define DMA0_QM_CGM_STS_AXI_IDLE_MASK 0x200`
H A D	tpc0_qm_masks.h	`150 #define TPC0_QM_GLBL_STS1_CP_FENCE1_OVF_ERR_MASK 0x200 180 #define TPC0_QM_GLBL_STS1_4_CP_FENCE1_OVF_ERR_MASK 0x200 212 #define TPC0_QM_GLBL_MSG_EN_CP_FENCE1_OVF_ERR_MASK 0x200 242 #define TPC0_QM_GLBL_MSG_EN_4_CP_FENCE1_OVF_ERR_MASK 0x200 714 #define TPC0_QM_CGM_STS_AXI_IDLE_MASK 0x200`
/kernel/linux/linux-5.10/drivers/net/ethernet/atheros/atl1e/
H A D	atl1e_hw.h	`66 #define REG_SPI_FLASH_CTRL 0x200 154 #define MASTER_CTRL_LED_MODE 0x200 179 #define GPHY_CTRL_PCLK_SEL_DIS 0x200 273 #define MAC_CTRL_HUGE_EN 0x200 /* 1: receive Jumbo frame enable */ 544 #define ISR_RX0_PAGE_FULL 0x200`
/kernel/linux/linux-5.10/drivers/reset/
H A D	reset-uniphier.c	`144 UNIPHIER_RESETX((id), 0x110 + 0x200 * (ch), 0) 147 UNIPHIER_RESETX((id), 0x110 + 0x200 * (ch), 26) 150 UNIPHIER_RESETX((id), 0x80 + 0x200 * (ch), 0) 153 UNIPHIER_RESETX((id), 0x114 + 0x200 * (ch), 0) 156 UNIPHIER_RESETX((id), 0x110 + 0x200 * (ch), 24)`
/kernel/linux/linux-6.6/drivers/net/ethernet/atheros/atl1e/
H A D	atl1e_hw.h	`66 #define REG_SPI_FLASH_CTRL 0x200 154 #define MASTER_CTRL_LED_MODE 0x200 179 #define GPHY_CTRL_PCLK_SEL_DIS 0x200 273 #define MAC_CTRL_HUGE_EN 0x200 /* 1: receive Jumbo frame enable */ 544 #define ISR_RX0_PAGE_FULL 0x200`
/kernel/linux/linux-6.6/drivers/reset/
H A D	reset-uniphier.c	`158 UNIPHIER_RESETX((id), 0x110 + 0x200 * (ch), 0) 161 UNIPHIER_RESETX((id), 0x110 + 0x200 * (ch), 26) 164 UNIPHIER_RESETX((id), 0x80 + 0x200 * (ch), 0) 167 UNIPHIER_RESETX((id), 0x114 + 0x200 * (ch), 0) 170 UNIPHIER_RESETX((id), 0x110 + 0x200 * (ch), 24)`
/kernel/linux/linux-6.6/drivers/accel/habanalabs/include/gaudi/asic_reg/
H A D	dma0_qm_masks.h	`150 #define DMA0_QM_GLBL_STS1_CP_FENCE1_OVF_ERR_MASK 0x200 180 #define DMA0_QM_GLBL_STS1_4_CP_FENCE1_OVF_ERR_MASK 0x200 212 #define DMA0_QM_GLBL_MSG_EN_CP_FENCE1_OVF_ERR_MASK 0x200 242 #define DMA0_QM_GLBL_MSG_EN_4_CP_FENCE1_OVF_ERR_MASK 0x200 714 #define DMA0_QM_CGM_STS_AXI_IDLE_MASK 0x200`
H A D	mme0_qm_masks.h	`150 #define MME0_QM_GLBL_STS1_CP_FENCE1_OVF_ERR_MASK 0x200 180 #define MME0_QM_GLBL_STS1_4_CP_FENCE1_OVF_ERR_MASK 0x200 212 #define MME0_QM_GLBL_MSG_EN_CP_FENCE1_OVF_ERR_MASK 0x200 242 #define MME0_QM_GLBL_MSG_EN_4_CP_FENCE1_OVF_ERR_MASK 0x200 714 #define MME0_QM_CGM_STS_AXI_IDLE_MASK 0x200`
H A D	tpc0_qm_masks.h	`150 #define TPC0_QM_GLBL_STS1_CP_FENCE1_OVF_ERR_MASK 0x200 180 #define TPC0_QM_GLBL_STS1_4_CP_FENCE1_OVF_ERR_MASK 0x200 212 #define TPC0_QM_GLBL_MSG_EN_CP_FENCE1_OVF_ERR_MASK 0x200 242 #define TPC0_QM_GLBL_MSG_EN_4_CP_FENCE1_OVF_ERR_MASK 0x200 714 #define TPC0_QM_CGM_STS_AXI_IDLE_MASK 0x200`
H A D	nic0_qm0_masks.h	`150 #define NIC0_QM0_GLBL_STS1_CP_FENCE1_OVF_ERR_MASK 0x200 180 #define NIC0_QM0_GLBL_STS1_4_CP_FENCE1_OVF_ERR_MASK 0x200 212 #define NIC0_QM0_GLBL_MSG_EN_CP_FENCE1_OVF_ERR_MASK 0x200 242 #define NIC0_QM0_GLBL_MSG_EN_4_CP_FENCE1_OVF_ERR_MASK 0x200 714 #define NIC0_QM0_CGM_STS_AXI_IDLE_MASK 0x200`
/kernel/linux/linux-5.10/sound/soc/amd/include/
H A D	acp_2_2_sh_mask.h	785 #define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBAdrWinViolChkEnb_MASK 0x200 843 #define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBAdrWinViolChkEnb_MASK 0x200 985 #define ACP_SOFT_RESET__SoftResetDMA_MASK 0x200 1029 #define ACP_DAGB_DEBUG_CNT_ENABLE__onion_wr_go_cnt_enable_MASK 0x200 1093 #define ACP_EXTERNAL_INTR_CNTL__DSP1TimeoutMask_MASK 0x200 1145 #define ACP_DSP_SW_INTR_TRIG__TrigSWIntDSPnDSP1_MASK 0x200 1163 #define ACP_DSP_SW_INTR_CNTL__EnbSWIntDSPnDSP1_MASK 0x200 1209 #define ACP_EXTERNAL_INTR_STAT__DSP1TimeoutStat_MASK 0x200 1211 #define ACP_EXTERNAL_INTR_STAT__DSP1TimeoutAck_MASK 0x200 1241 #define ACP_DSP_SW_INTR_STAT__SWIntDSPnDSP1Stat_MASK 0x200 [all...]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/include/asic_reg/oss/
H A D	oss_2_0_sh_mask.h	133 #define IH_STATUS__MC_WR_CLEAN_STALL_MASK 0x200 145 #define IH_PERFMON_CNTL__CLEAR1_MASK 0x200 219 #define SEM_STATUS__SDMA1_MAILBOX_PENDING_MASK 0x200 291 #define SRBM_STATUS2__CHUB_BUSY_MASK 0x200 309 #define SRBM_STATUS__MCB_BUSY_MASK 0x200 345 #define SRBM_SOFT_RESET__SOFT_RESET_HDP_MASK 0x200 439 #define SRBM_DEBUG__SAM_CLOCK_DOMAIN_OVERRIDE_MASK 0x200 459 #define SRBM_DEBUG_SNAPSHOT__UVD_RDY_MASK 0x200 763 #define XDMA_SLV_CNTL__XDMA_SLV_MEM_READY_MASK 0x200 927 #define SDMA0_STATUS_REG__INSIDE_IB_MASK 0x200 [all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/include/asic_reg/oss/
H A D	oss_2_0_sh_mask.h	133 #define IH_STATUS__MC_WR_CLEAN_STALL_MASK 0x200 145 #define IH_PERFMON_CNTL__CLEAR1_MASK 0x200 219 #define SEM_STATUS__SDMA1_MAILBOX_PENDING_MASK 0x200 291 #define SRBM_STATUS2__CHUB_BUSY_MASK 0x200 309 #define SRBM_STATUS__MCB_BUSY_MASK 0x200 345 #define SRBM_SOFT_RESET__SOFT_RESET_HDP_MASK 0x200 439 #define SRBM_DEBUG__SAM_CLOCK_DOMAIN_OVERRIDE_MASK 0x200 459 #define SRBM_DEBUG_SNAPSHOT__UVD_RDY_MASK 0x200 763 #define XDMA_SLV_CNTL__XDMA_SLV_MEM_READY_MASK 0x200 927 #define SDMA0_STATUS_REG__INSIDE_IB_MASK 0x200 [all...]
/kernel/linux/linux-6.6/sound/soc/amd/include/
H A D	acp_2_2_sh_mask.h	785 #define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBAdrWinViolChkEnb_MASK 0x200 843 #define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBAdrWinViolChkEnb_MASK 0x200 985 #define ACP_SOFT_RESET__SoftResetDMA_MASK 0x200 1029 #define ACP_DAGB_DEBUG_CNT_ENABLE__onion_wr_go_cnt_enable_MASK 0x200 1093 #define ACP_EXTERNAL_INTR_CNTL__DSP1TimeoutMask_MASK 0x200 1145 #define ACP_DSP_SW_INTR_TRIG__TrigSWIntDSPnDSP1_MASK 0x200 1163 #define ACP_DSP_SW_INTR_CNTL__EnbSWIntDSPnDSP1_MASK 0x200 1209 #define ACP_EXTERNAL_INTR_STAT__DSP1TimeoutStat_MASK 0x200 1211 #define ACP_EXTERNAL_INTR_STAT__DSP1TimeoutAck_MASK 0x200 1241 #define ACP_DSP_SW_INTR_STAT__SWIntDSPnDSP1Stat_MASK 0x200 [all...]
/kernel/linux/linux-5.10/drivers/pci/controller/
H A D	pcie-iproc-msi.c	`113 { 0x200, 0x2c0, 0x204, 0x2c4, 0x210, 0x250, 0x254, 0x208 }, 114 { 0x200, 0x2c0, 0x204, 0x2c4, 0x214, 0x258, 0x25c, 0x208 }, 115 { 0x200, 0x2c0, 0x204, 0x2c4, 0x218, 0x260, 0x264, 0x208 }, 116 { 0x200, 0x2c0, 0x204, 0x2c4, 0x21c, 0x268, 0x26c, 0x208 }, 117 { 0x200, 0x2c0, 0x204, 0x2c4, 0x220, 0x270, 0x274, 0x208 }, 118 { 0x200, 0x2c0, 0x204, 0x2c4, 0x224, 0x278, 0x27c, 0x208 },`
/kernel/linux/linux-6.6/drivers/pci/controller/
H A D	pcie-iproc-msi.c	`113 { 0x200, 0x2c0, 0x204, 0x2c4, 0x210, 0x250, 0x254, 0x208 }, 114 { 0x200, 0x2c0, 0x204, 0x2c4, 0x214, 0x258, 0x25c, 0x208 }, 115 { 0x200, 0x2c0, 0x204, 0x2c4, 0x218, 0x260, 0x264, 0x208 }, 116 { 0x200, 0x2c0, 0x204, 0x2c4, 0x21c, 0x268, 0x26c, 0x208 }, 117 { 0x200, 0x2c0, 0x204, 0x2c4, 0x220, 0x270, 0x274, 0x208 }, 118 { 0x200, 0x2c0, 0x204, 0x2c4, 0x224, 0x278, 0x27c, 0x208 },`
/kernel/linux/linux-6.6/drivers/gpu/drm/msm/adreno/
H A D	a6xx_gpu_state.h	`196 SHADER(A6XX_TP0_TMO_DATA, 0x200), 199 SHADER(A6XX_TP1_TMO_DATA, 0x200), 208 SHADER(A6XX_SP_LB_5_DATA, 0x200), 238 SHADER(A6XX_SP_LB_6_DATA, 0x200), 239 SHADER(A6XX_SP_LB_7_DATA, 0x200), 240 SHADER(A6XX_HLSQ_INST_RAM_1, 0x200),`
/kernel/linux/linux-5.10/arch/m68k/include/asm/
H A D	m5206sim.h	`100 #define MCFDMA_BASE0 (MCF_MBAR + 0x200) /* Base address DMA 0 / 133 #define MCFSIM_PAR_DREQ1 0x200 / Select DREQ1 input */`
/kernel/linux/linux-5.10/arch/sh/boards/
H A D	board-apsh4a3a.c	`83 .start = evt2irq(0x200), 84 .end = evt2irq(0x200),`

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