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Searched refs:reset (Results 2226 - 2250 of 7053) sorted by relevance

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/third_party/skia/gm/
H A Dgetpostextpath.cpp51 path.reset(); in DEF_SIMPLE_GM()
/third_party/skia/include/android/
H A DSkAnimatedImage.h49 void reset();
55 * animation. Gets reset to false if the animation is restarted.
/third_party/skia/bench/
H A DGlyphQuadFillBench.cpp60 fVertices.reset(new char[subRun->vertexStride(drawMatrix) * subRun->glyphCount() * 4]);
H A DGrMipmapBench.cpp67 fSurface.reset(nullptr);
/third_party/spirv-tools/source/opt/
H A Dpass_manager.cpp77 pass.reset(nullptr); in Run()
/third_party/skia/third_party/externals/angle2/scripts/
H A Droll_aosp.sh135 gclient sync --reset --force --delete_unversioned_trees
/kernel/linux/linux-5.10/drivers/mmc/host/
H A Dsdhci-msm.c19 #include <linux/reset.h>
893 * Retuning in HS400 (DDR mode) will fail, just reset the in sdhci_msm_cdclp533_calibration()
998 * configuration on reset. Currently reprogramming the power on in sdhci_msm_cm_dll_sdc4_calibration()
999 * reset (POR) value in case it might have been modified by in sdhci_msm_cm_dll_sdc4_calibration()
1073 * Retuning in HS400 (DDR mode) will fail, just reset the in sdhci_msm_hs400_dll_calibration()
1203 /* First of all reset the tuning block */ in sdhci_msm_execute_tuning()
1525 * SDHCI_HOST_CONTROL2 register. The reset state of that bit is 0 in sdhci_msm_check_power_status()
1594 * lost when actual reset and clear/read of status register is in sdhci_msm_handle_pwr_irq()
1900 /* Disable cqe reset due to cqe enable signal */ in sdhci_msm_cqe_add_host()
2195 .reset
2238 struct reset_control *reset; sdhci_msm_gcc_reset() local
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/kernel/linux/linux-5.10/drivers/media/usb/dvb-usb/
H A Ddw2102.c942 /* reset board */ in su3000_power_ctrl()
1863 u8 reset; in dw2102_load_firmware() local
1881 reset = 1; in dw2102_load_firmware()
1883 dw210x_op_rw(dev, 0xa0, 0x7f92, 0, &reset, 1, DW210X_WRITE_MSG); in dw2102_load_firmware()
1884 dw210x_op_rw(dev, 0xa0, 0xe600, 0, &reset, 1, DW210X_WRITE_MSG); in dw2102_load_firmware()
1898 reset = 0; in dw2102_load_firmware()
1899 if (ret || dw210x_op_rw(dev, 0xa0, 0x7f92, 0, &reset, 1, in dw2102_load_firmware()
1904 if (ret || dw210x_op_rw(dev, 0xa0, 0xe600, 0, &reset, 1, in dw2102_load_firmware()
1915 reset = 1; in dw2102_load_firmware()
1916 dw210x_op_rw(dev, 0xc4, 0x0000, 0, &reset, in dw2102_load_firmware()
[all...]
/kernel/linux/linux-6.6/drivers/mmc/host/
H A Dsdhci-msm.c19 #include <linux/reset.h>
913 * Retuning in HS400 (DDR mode) will fail, just reset the in sdhci_msm_cdclp533_calibration()
1018 * configuration on reset. Currently reprogramming the power on in sdhci_msm_cm_dll_sdc4_calibration()
1019 * reset (POR) value in case it might have been modified by in sdhci_msm_cm_dll_sdc4_calibration()
1093 * Retuning in HS400 (DDR mode) will fail, just reset the in sdhci_msm_hs400_dll_calibration()
1223 /* First of all reset the tuning block */ in sdhci_msm_execute_tuning()
1545 * SDHCI_HOST_CONTROL2 register. The reset state of that bit is 0 in sdhci_msm_check_power_status()
1614 * lost when actual reset and clear/read of status register is in sdhci_msm_handle_pwr_irq()
2039 /* Disable cqe reset due to cqe enable signal */ in sdhci_msm_cqe_add_host()
2322 .reset
2365 struct reset_control *reset; sdhci_msm_gcc_reset() local
[all...]
/kernel/linux/linux-6.6/drivers/media/usb/dvb-usb/
H A Ddw2102.c942 /* reset board */ in su3000_power_ctrl()
1855 u8 reset; in dw2102_load_firmware() local
1873 reset = 1; in dw2102_load_firmware()
1875 dw210x_op_rw(dev, 0xa0, 0x7f92, 0, &reset, 1, DW210X_WRITE_MSG); in dw2102_load_firmware()
1876 dw210x_op_rw(dev, 0xa0, 0xe600, 0, &reset, 1, DW210X_WRITE_MSG); in dw2102_load_firmware()
1890 reset = 0; in dw2102_load_firmware()
1891 if (ret || dw210x_op_rw(dev, 0xa0, 0x7f92, 0, &reset, 1, in dw2102_load_firmware()
1896 if (ret || dw210x_op_rw(dev, 0xa0, 0xe600, 0, &reset, 1, in dw2102_load_firmware()
1907 reset = 1; in dw2102_load_firmware()
1908 dw210x_op_rw(dev, 0xc4, 0x0000, 0, &reset, in dw2102_load_firmware()
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/third_party/icu/icu4j/main/classes/charset/src/com/ibm/icu/charset/
H A DCharsetISO2022.java331 void reset() { in reset() method in CharsetISO2022.ISO2022State
361 void reset() { in reset() method in CharsetISO2022.UConverterDataISO2022
362 toU2022State.reset(); in reset()
363 fromU2022State.reset(); in reset()
791 myConverterData.reset(); in implReset()
904 myConverterData.isEmptySegment = false; /* reset this, we have a different error */ in decodeLoop()
943 /* automatically reset to single-byte mode */ in decodeLoop()
1104 myConverterData.reset(); in implReset()
1149 myConverterData.isEmptySegment = false; /* we are handling it, reset to avoid future spurious errors */ in decodeLoop()
1164 myConverterData.isEmptySegment = false; /* Handling a different error, reset thi in decodeLoop()
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/third_party/skia/third_party/externals/spirv-cross/
H A Dspirv_cross_c.cpp286 comp->compiler.reset(new Compiler(move(parsed_ir->parsed))); in spvc_context_create_compiler()
288 comp->compiler.reset(new Compiler(parsed_ir->parsed)); in spvc_context_create_compiler()
294 comp->compiler.reset(new CompilerGLSL(move(parsed_ir->parsed))); in spvc_context_create_compiler()
296 comp->compiler.reset(new CompilerGLSL(parsed_ir->parsed)); in spvc_context_create_compiler()
303 comp->compiler.reset(new CompilerHLSL(move(parsed_ir->parsed))); in spvc_context_create_compiler()
305 comp->compiler.reset(new CompilerHLSL(parsed_ir->parsed)); in spvc_context_create_compiler()
312 comp->compiler.reset(new CompilerMSL(move(parsed_ir->parsed))); in spvc_context_create_compiler()
314 comp->compiler.reset(new CompilerMSL(parsed_ir->parsed)); in spvc_context_create_compiler()
321 comp->compiler.reset(new CompilerCPP(move(parsed_ir->parsed))); in spvc_context_create_compiler()
323 comp->compiler.reset(ne in spvc_context_create_compiler()
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/kernel/linux/linux-5.10/drivers/devfreq/
H A Ddevfreq-event.c66 * devfreq device can't use the devfreq-event device for get/set/reset
190 * Note that this function stop all operations of devfreq-event dev and reset
204 if (edev->desc->ops && edev->desc->ops->reset) in devfreq_event_reset_event()
205 ret = edev->desc->ops->reset(edev); in devfreq_event_reset_event()
/kernel/linux/linux-5.10/drivers/clk/meson/
H A Dg12a-aoclk.c13 #include <linux/reset-controller.h>
451 .reset = g12a_aoclk_reset,
/kernel/linux/linux-5.10/drivers/cpuidle/
H A Dcoupled.c142 * this function, will be reset to 0 before any cpu returns from this function.
494 reset: in cpuidle_enter_state_coupled()
582 * it, and it's too late to turn on interrupts here, so reset the in cpuidle_enter_state_coupled()
589 goto reset; in cpuidle_enter_state_coupled()
/kernel/linux/linux-5.10/drivers/clk/tegra/
H A Dclk.c13 #include <linux/reset-controller.h>
30 /* Handlers for SoC-specific reset lines */
102 * access after disabling clock. Since the reset driver has no in tegra_clk_rst_assert()
103 * knowledge of which reset IDs represent which devices, simply do in tegra_clk_rst_assert()
195 * All non-boot peripherals will be in reset state on resume. in tegra_clk_periph_resume()
196 * Wait for 5us of reset propagation delay before de-asserting in tegra_clk_periph_resume()
309 .reset = tegra_clk_rst_reset,
/kernel/linux/linux-5.10/arch/arm/mach-pxa/
H A Dpalm27x.c244 void __init palm27x_ac97_init(int minv, int maxv, int jack, int reset) in palm27x_ac97_init() argument
246 palm27x_ac97_pdata.reset_gpio = reset; in palm27x_ac97_init()
/kernel/linux/linux-5.10/arch/arm64/kvm/
H A Dreset.c6 * Derived from arch/arm/kvm/reset.c
246 * kvm_reset_vcpu - sets core registers and sys_regs to reset value
250 * the virtual CPU struct to their architecturally defined reset
251 * values, except for registers whose reset is deferred until
261 * disable preemption around the vcpu reset as we would otherwise race with
273 WRITE_ONCE(vcpu->arch.reset_state.reset, false); in kvm_reset_vcpu()
331 * Additional reset state handling that PSCI may have imposed on us. in kvm_reset_vcpu()
332 * Must be done after all the sys_reg reset. in kvm_reset_vcpu()
334 if (reset_state.reset) { in kvm_reset_vcpu()
/kernel/linux/linux-5.10/arch/mips/cavium-octeon/executive/
H A Dcvmx-helper-sgmii.c142 * Take PCS through a reset sequence. in __cvmx_helper_sgmii_hardware_init_link()
152 control_reg.s.reset = 1; in __cvmx_helper_sgmii_hardware_init_link()
157 union cvmx_pcsx_mrx_control_reg, reset, ==, 0, 10000)) { in __cvmx_helper_sgmii_hardware_init_link()
159 "to finish reset\n", in __cvmx_helper_sgmii_hardware_init_link()
/kernel/linux/linux-5.10/arch/alpha/kernel/
H A Dsys_sio.c130 static void __sio_fixup_irq_levels(unsigned int level_bits, bool reset) in __sio_fixup_irq_levels() argument
148 if (reset) in __sio_fixup_irq_levels()
/kernel/linux/linux-5.10/drivers/cpufreq/
H A Dcpufreq_stats.c25 /* Deferred reset */
48 /* Adjust for the time elapsed since reset was requested */ in cpufreq_stats_reset_table()
122 cpufreq_freq_attr_wo(reset); variable
178 &reset.attr,
/kernel/linux/linux-5.10/drivers/firmware/arm_scmi/
H A Dreset.c203 .reset = scmi_reset_domain_reset,
318 DEFINE_SCMI_PROTOCOL_REGISTER_UNREGISTER(SCMI_PROTOCOL_RESET, reset)
/kernel/linux/linux-5.10/drivers/net/ethernet/intel/igc/
H A Digc_base.c25 * on the last TLP read/write transaction when MAC is reset. in igc_reset_hw_base()
42 hw_dbg("Issuing a global reset to MAC\n"); in igc_reset_hw_base()
136 /* reset */ in igc_init_mac_params_base()
178 ret_val = hw->phy.ops.reset(hw); in igc_init_phy_params_base()
415 .reset = igc_phy_hw_reset,
/kernel/linux/linux-6.6/arch/mips/cavium-octeon/executive/
H A Dcvmx-helper-sgmii.c142 * Take PCS through a reset sequence. in __cvmx_helper_sgmii_hardware_init_link()
152 control_reg.s.reset = 1; in __cvmx_helper_sgmii_hardware_init_link()
157 union cvmx_pcsx_mrx_control_reg, reset, ==, 0, 10000)) { in __cvmx_helper_sgmii_hardware_init_link()
159 "to finish reset\n", in __cvmx_helper_sgmii_hardware_init_link()
/kernel/linux/linux-6.6/arch/alpha/kernel/
H A Dsys_sio.c130 static void __sio_fixup_irq_levels(unsigned int level_bits, bool reset) in __sio_fixup_irq_levels() argument
148 if (reset) in __sio_fixup_irq_levels()

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