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/kernel/linux/linux-5.10/drivers/i2c/busses/
H A Di2c-owl.c96 void __iomem *base; member
119 owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_CTL, in owl_i2c_reset()
122 owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_CTL, in owl_i2c_reset()
126 writel(0, i2c_dev->base + OWL_I2C_REG_STAT); in owl_i2c_reset()
134 owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_FIFOCTL, in owl_i2c_reset_fifo()
140 val = readl(i2c_dev->base + OWL_I2C_REG_FIFOCTL); in owl_i2c_reset_fifo()
161 writel(OWL_I2C_DIV_FACTOR(val), i2c_dev->base + OWL_I2C_REG_CLKDIV); in owl_i2c_set_freq()
175 fifostat = readl(i2c_dev->base + OWL_I2C_REG_FIFOSTAT); in owl_i2c_interrupt()
179 owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_FIFOSTAT, in owl_i2c_interrupt()
185 stat = readl(i2c_dev->base in owl_i2c_interrupt()
[all...]
/kernel/linux/linux-6.6/drivers/mfd/
H A Dintel-m10-bmc-pmci.c19 void __iomem *base; member
42 void __iomem *base; member
51 writel(INDIRECT_CMD_CLR, ctx->base + INDIRECT_CMD_OFF); in indirect_clear_cmd()
53 ret = readl_poll_timeout(ctx->base + INDIRECT_CMD_OFF, cmd, in indirect_clear_cmd()
68 cmd = readl(ctx->base + INDIRECT_CMD_OFF); in indirect_reg_read()
72 writel(reg, ctx->base + INDIRECT_ADDR_OFF); in indirect_reg_read()
73 writel(INDIRECT_CMD_RD, ctx->base + INDIRECT_CMD_OFF); in indirect_reg_read()
75 ret = readl_poll_timeout(ctx->base + INDIRECT_CMD_OFF, ack, in indirect_reg_read()
81 tmpval = readl(ctx->base + INDIRECT_RD_OFF); in indirect_reg_read()
100 cmd = readl(ctx->base in indirect_reg_write()
121 pmci_write_fifo(void __iomem *base, const u32 *buf, size_t count) pmci_write_fifo() argument
127 pmci_read_fifo(void __iomem *base, u32 *buf, size_t count) pmci_read_fifo() argument
[all...]
/kernel/linux/linux-6.6/drivers/watchdog/
H A Df71808e_wdt.c126 static inline int superio_inb(int base, int reg);
127 static inline int superio_inw(int base, int reg);
128 static inline void superio_outb(int base, int reg, u8 val);
129 static inline void superio_set_bit(int base, int reg, int bit);
130 static inline void superio_clear_bit(int base, int reg, int bit);
131 static inline int superio_enter(int base);
132 static inline void superio_select(int base, int ld);
133 static inline void superio_exit(int base);
152 static inline int superio_inb(int base, int reg) in superio_inb() argument
154 outb(reg, base); in superio_inb()
158 superio_inw(int base, int reg) superio_inw() argument
166 superio_outb(int base, int reg, u8 val) superio_outb() argument
172 superio_set_bit(int base, int reg, int bit) superio_set_bit() argument
179 superio_clear_bit(int base, int reg, int bit) superio_clear_bit() argument
186 superio_enter(int base) superio_enter() argument
201 superio_select(int base, int ld) superio_select() argument
207 superio_exit(int base) superio_exit() argument
[all...]
/kernel/linux/linux-6.6/drivers/spi/
H A Dspi-amlogic-spifc-a1.c109 void __iomem *base; member
120 spifc->base + SPIFC_A1_USER_CTRL0_REG); in amlogic_spifc_a1_request()
122 return readl_poll_timeout(spifc->base + SPIFC_A1_USER_CTRL0_REG, in amlogic_spifc_a1_request()
135 spifc->base + SPIFC_A1_DBUF_CTRL_REG); in amlogic_spifc_a1_drain_buffer()
136 ioread32_rep(spifc->base + SPIFC_A1_DBUF_DATA_REG, buf, count); in amlogic_spifc_a1_drain_buffer()
139 data = readl(spifc->base + SPIFC_A1_DBUF_DATA_REG); in amlogic_spifc_a1_drain_buffer()
152 spifc->base + SPIFC_A1_DBUF_CTRL_REG); in amlogic_spifc_a1_fill_buffer()
153 iowrite32_rep(spifc->base + SPIFC_A1_DBUF_DATA_REG, buf, count); in amlogic_spifc_a1_fill_buffer()
157 writel(data, spifc->base + SPIFC_A1_DBUF_DATA_REG); in amlogic_spifc_a1_fill_buffer()
163 writel(0, spifc->base in amlogic_spifc_a1_user_init()
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/kernel/linux/linux-6.6/drivers/perf/hisilicon/
H A Dhisi_uncore_hha_pmu.c67 val = readl(hha_pmu->base + HHA_SRCID_CTRL); in hisi_hha_pmu_enable_tracetag()
69 writel(val, hha_pmu->base + HHA_SRCID_CTRL); in hisi_hha_pmu_enable_tracetag()
78 val = readl(hha_pmu->base + HHA_SRCID_CTRL); in hisi_hha_pmu_clear_tracetag()
80 writel(val, hha_pmu->base + HHA_SRCID_CTRL); in hisi_hha_pmu_clear_tracetag()
91 val = readl(hha_pmu->base + HHA_DATSRC_CTRL); in hisi_hha_pmu_config_ds()
93 writel(val, hha_pmu->base + HHA_DATSRC_CTRL); in hisi_hha_pmu_config_ds()
105 val = readl(hha_pmu->base + HHA_DATSRC_CTRL); in hisi_hha_pmu_clear_ds()
107 writel(val, hha_pmu->base + HHA_DATSRC_CTRL); in hisi_hha_pmu_clear_ds()
120 val = readl(hha_pmu->base + HHA_SRCID_CTRL); in hisi_hha_pmu_config_srcid()
123 writel(val, hha_pmu->base in hisi_hha_pmu_config_srcid()
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/msm/disp/dpu1/
H A Ddpu_hw_dsc_1_2.c79 DPU_REG_WRITE(hw, sblk->ctl.base + DSC_CFG, 0); in dpu_hw_dsc_disable_1_2()
81 DPU_REG_WRITE(hw, sblk->enc.base + ENC_DF_CTRL, 0); in dpu_hw_dsc_disable_1_2()
82 DPU_REG_WRITE(hw, sblk->enc.base + DSC_MAIN_CONF, 0); in dpu_hw_dsc_disable_1_2()
125 DPU_REG_WRITE(hw, sblk->enc.base + ENC_DF_CTRL, data); in dpu_hw_dsc_config_1_2()
153 DPU_REG_WRITE(hw, sblk->enc.base + DSC_MAIN_CONF, data); in dpu_hw_dsc_config_1_2()
158 DPU_REG_WRITE(hw, sblk->enc.base + DSC_PICTURE_SIZE, data); in dpu_hw_dsc_config_1_2()
163 DPU_REG_WRITE(hw, sblk->enc.base + DSC_SLICE_SIZE, data); in dpu_hw_dsc_config_1_2()
165 DPU_REG_WRITE(hw, sblk->enc.base + DSC_MISC_SIZE, in dpu_hw_dsc_config_1_2()
171 DPU_REG_WRITE(hw, sblk->enc.base + DSC_HRD_DELAYS, data); in dpu_hw_dsc_config_1_2()
173 DPU_REG_WRITE(hw, sblk->enc.base in dpu_hw_dsc_config_1_2()
[all...]
/third_party/gn/src/gn/
H A Dcommand_args.cc12 #include "base/command_line.h"
13 #include "base/environment.h"
14 #include "base/files/file_util.h"
15 #include "base/json/json_writer.h"
16 #include "base/strings/string_number_conversions.h"
17 #include "base/strings/string_util.h"
46 while (i < line.size() && base::IsAsciiWhitespace(line[i])) in DoesLineBeginWithComment()
129 OutputString(" From " + location + ":" + base::IntToString(line_no) + in PrintDefaultValueInfo()
152 OutputString(" From " + location + ":" + base::IntToString(line_no) + in PrintArgHelp()
164 void BuildArgJson(base
[all...]
/third_party/mesa3d/src/gallium/frontends/lavapipe/
H A Dlvp_private.h187 struct vk_object_base base; member
211 struct vk_object_base base; member
221 struct vk_sync base; member
240 return container_of(sync, struct lvp_pipe_sync, base); in vk_sync_as_lvp_pipe_sync()
263 struct vk_object_base base; member
354 struct vk_object_base base; member
361 struct vk_object_base base; member
369 struct vk_object_base base; member
428 struct vk_object_base base; member
458 struct vk_object_base base; member
463 struct vk_object_base base; global() member
476 struct vk_object_base base; global() member
485 struct vk_object_base base; global() member
[all...]
/third_party/mesa3d/src/gallium/drivers/virgl/
H A Dvirgl_resource.c70 vs->base.is_format_supported(&vs->base, res->b.format, res->b.target, in virgl_can_readback_from_rendertarget()
103 virgl_has_readback_format(&vs->base, pipe_to_virgl_format(res->b.format), false) && in virgl_can_copy_transfer_from_host()
118 struct virgl_winsys *vws = virgl_screen(vctx->base.screen)->vws; in virgl_res_needs_flush()
119 struct virgl_resource *res = virgl_resource(trans->base.resource); in virgl_res_needs_flush()
121 if (trans->base.usage & PIPE_MAP_UNSYNCHRONIZED) in virgl_res_needs_flush()
158 struct virgl_screen *vs = virgl_screen(vctx->base.screen); in virgl_resource_transfer_prepare()
160 struct virgl_resource *res = virgl_resource(xfer->base.resource); in virgl_resource_transfer_prepare()
167 if (xfer->base.usage & PIPE_MAP_DIRECTLY) in virgl_resource_transfer_prepare()
179 readback = virgl_res_needs_readback(vctx, res, xfer->base in virgl_resource_transfer_prepare()
[all...]
H A Dvirgl_context.c174 struct virgl_winsys *vws = virgl_screen(vctx->base.screen)->vws; in virgl_attach_res_framebuffer()
202 struct virgl_winsys *vws = virgl_screen(vctx->base.screen)->vws; in virgl_attach_res_sampler_views()
216 struct virgl_winsys *vws = virgl_screen(vctx->base.screen)->vws; in virgl_attach_res_vertex_buffers()
230 struct virgl_winsys *vws = virgl_screen(vctx->base.screen)->vws; in virgl_attach_res_index_buffer()
240 struct virgl_winsys *vws = virgl_screen(vctx->base.screen)->vws; in virgl_attach_res_so_targets()
245 res = virgl_resource(vctx->so_targets[i].base.buffer); in virgl_attach_res_so_targets()
254 struct virgl_winsys *vws = virgl_screen(vctx->base.screen)->vws; in virgl_attach_res_uniform_buffers()
271 struct virgl_winsys *vws = virgl_screen(vctx->base.screen)->vws; in virgl_attach_res_shader_buffers()
288 struct virgl_winsys *vws = virgl_screen(vctx->base.screen)->vws; in virgl_attach_res_shader_images()
304 struct virgl_winsys *vws = virgl_screen(vctx->base in virgl_attach_res_atomic_buffers()
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/kernel/linux/linux-6.6/drivers/crypto/
H A Domap-sham.c172 struct omap_sham_hmac_ctx base[]; member
305 struct omap_sham_hmac_ctx *bctx = tctx->base; in omap_sham_copy_hash_omap4()
452 struct omap_sham_hmac_ctx *bctx = tctx->base; in omap_sham_write_ctrl_omap4()
844 base); in omap_sham_prepare_request()
992 struct omap_sham_hmac_ctx *bctx = tctx->base; in omap_sham_init()
1062 base); in omap_sham_hash_one_req()
1101 struct omap_sham_ctx *tctx = crypto_tfm_ctx(req->base.tfm); in omap_sham_finish_hmac()
1102 struct omap_sham_hmac_ctx *bctx = tctx->base; in omap_sham_finish_hmac()
1217 struct omap_sham_ctx *tctx = crypto_tfm_ctx(req->base.tfm); in omap_sham_final_shash()
1287 struct omap_sham_hmac_ctx *bctx = tctx->base; in omap_sham_setkey()
[all...]
/third_party/node/deps/v8/src/temporal/
H A Dtemporal-parser.cc7 #include "src/base/bounds.h"
17 inline constexpr bool IsNonZeroDecimalDigit(base::uc32 c) { in IsNonZeroDecimalDigit()
18 return base::IsInRange(c, '1', '9'); in IsNonZeroDecimalDigit()
22 inline constexpr bool IsTZLeadingChar(base::uc32 c) { in IsTZLeadingChar()
23 return base::IsInRange(AsciiAlphaToLower(c), 'a', 'z') || c == '.' || in IsTZLeadingChar()
28 inline constexpr bool IsTZChar(base::uc32 c) { in IsTZChar()
33 inline constexpr bool IsDecimalSeparator(base::uc32 c) { in IsDecimalSeparator()
38 inline constexpr bool IsDateTimeSeparator(base::uc32 c) { in IsDateTimeSeparator()
43 inline constexpr bool IsAsciiSign(base::uc32 c) { return c == '-' || c == '+'; } in IsAsciiSign()
46 inline constexpr bool IsSign(base
[all...]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dmub/src/
H A Ddmub_srv.c79 const uint8_t *base = (const uint8_t *)fb->cpu_addr; in dmub_flush_buffer_mem() local
90 dmub_memcpy(buf, base + pos, sizeof(buf)); in dmub_flush_buffer_mem()
94 dmub_memcpy(buf, base + pos, fb->size - end); in dmub_flush_buffer_mem()
261 inst->base = 0x0; in dmub_srv_calc_region_info()
262 inst->top = inst->base + params->inst_const_size; in dmub_srv_calc_region_info()
264 data->base = dmub_align(inst->top, 256); in dmub_srv_calc_region_info()
265 data->top = data->base + params->bss_data_size; in dmub_srv_calc_region_info()
272 stack->base = dmub_align(data->top, 256); in dmub_srv_calc_region_info()
273 stack->top = stack->base + DMUB_STACK_SIZE + DMUB_CONTEXT_SIZE; in dmub_srv_calc_region_info()
275 bios->base in dmub_srv_calc_region_info()
[all...]
/kernel/linux/linux-5.10/drivers/mailbox/
H A Dmtk-cmdq-mailbox.c56 void __iomem *base; member
71 void __iomem *base; member
98 writel(CMDQ_THR_SUSPEND, thread->base + CMDQ_THR_SUSPEND_TASK); in cmdq_thread_suspend()
101 if (!(readl(thread->base + CMDQ_THR_ENABLE_TASK) & CMDQ_THR_ENABLED)) in cmdq_thread_suspend()
104 if (readl_poll_timeout_atomic(thread->base + CMDQ_THR_CURR_STATUS, in cmdq_thread_suspend()
107 (u32)(thread->base - cmdq->base)); in cmdq_thread_suspend()
116 writel(CMDQ_THR_RESUME, thread->base + CMDQ_THR_SUSPEND_TASK); in cmdq_thread_resume()
124 writel(CMDQ_THR_ACTIVE_SLOT_CYCLES, cmdq->base + CMDQ_THR_SLOT_CYCLES); in cmdq_init()
126 writel(i, cmdq->base in cmdq_init()
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/kernel/linux/linux-5.10/drivers/net/phy/
H A Dsfp-bus.c60 // Alcatel Lucent G-010S-P can operate at 2500base-X, but
66 // Alcatel Lucent G-010S-A can operate at 2500base-X, but
72 // Huawei MA5671A can operate at 2500base-X, but report 1.2GBd
78 // Lantech 8330-262D-E can operate at 2500base-X, but
117 vs = sfp_strlen(id->base.vendor_name, ARRAY_SIZE(id->base.vendor_name)); in sfp_lookup_quirk()
118 ps = sfp_strlen(id->base.vendor_pn, ARRAY_SIZE(id->base.vendor_pn)); in sfp_lookup_quirk()
121 if (sfp_match(q->vendor, id->base.vendor_name, vs) && in sfp_lookup_quirk()
122 sfp_match(q->part, id->base in sfp_lookup_quirk()
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/kernel/linux/linux-5.10/sound/soc/mxs/
H A Dmxs-saif.c102 scr = __raw_readl(master_saif->base + SAIF_CTRL); in mxs_saif_set_clk()
155 __raw_writel(scr, master_saif->base + SAIF_CTRL); in mxs_saif_set_clk()
197 __raw_writel(scr, master_saif->base + SAIF_CTRL); in mxs_saif_set_clk()
213 stat = __raw_readl(saif->base + SAIF_STAT); in mxs_saif_put_mclk()
223 saif->base + SAIF_CTRL + MXS_SET_ADDR); in mxs_saif_put_mclk()
225 saif->base + SAIF_CTRL + MXS_CLR_ADDR); in mxs_saif_put_mclk()
251 saif->base + SAIF_CTRL + MXS_CLR_ADDR); in mxs_saif_get_mclk()
255 saif->base + SAIF_CTRL + MXS_CLR_ADDR); in mxs_saif_get_mclk()
263 stat = __raw_readl(saif->base + SAIF_STAT); in mxs_saif_get_mclk()
280 saif->base in mxs_saif_get_mclk()
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/i915/display/
H A Dintel_display.h260 base.head)
265 base.head) \
267 drm_plane_mask(&intel_plane->base))
272 base.head) \
278 base.head)
283 base.head) \
289 base.head)
294 base.head) \
296 drm_encoder_mask(&intel_encoder->base))
299 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/mxsfb/
H A Dmxsfb_kms.c64 ctrl1 = readl(mxsfb->base + LCDC_CTRL1); in mxsfb_set_formats()
96 writel(ctrl1, mxsfb->base + LCDC_CTRL1); in mxsfb_set_formats()
97 writel(ctrl, mxsfb->base + LCDC_CTRL); in mxsfb_set_formats()
107 mxsfb->base + mxsfb->devdata->transfer_count); in mxsfb_set_mode()
131 writel(vdctrl0, mxsfb->base + LCDC_VDCTRL0); in mxsfb_set_mode()
134 writel(m->crtc_vtotal, mxsfb->base + LCDC_VDCTRL1); in mxsfb_set_mode()
140 mxsfb->base + LCDC_VDCTRL2); in mxsfb_set_mode()
144 mxsfb->base + LCDC_VDCTRL3); in mxsfb_set_mode()
147 mxsfb->base + LCDC_VDCTRL4); in mxsfb_set_mode()
161 reg = readl(mxsfb->base in mxsfb_enable_controller()
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/kernel/linux/linux-6.6/drivers/hwtracing/coresight/
H A Dcoresight-etb10.c70 * @base: memory mapped base address for this component.
84 void __iomem *base; member
102 return readl_relaxed(drvdata->base + ETB_RAM_DEPTH_REG); in etb_get_buffer_depth()
110 CS_UNLOCK(drvdata->base); in __etb_enable_hw()
114 writel_relaxed(0x0, drvdata->base + ETB_RAM_WRITE_POINTER); in __etb_enable_hw()
117 writel_relaxed(0x0, drvdata->base + ETB_RWD_REG); in __etb_enable_hw()
120 writel_relaxed(0x0, drvdata->base + ETB_RAM_WRITE_POINTER); in __etb_enable_hw()
122 writel_relaxed(0x0, drvdata->base + ETB_RAM_READ_POINTER); in __etb_enable_hw()
124 writel_relaxed(drvdata->trigger_cntr, drvdata->base in __etb_enable_hw()
720 void __iomem *base; etb_probe() local
[all...]
/kernel/linux/linux-6.6/sound/soc/mxs/
H A Dmxs-saif.c102 scr = __raw_readl(master_saif->base + SAIF_CTRL); in mxs_saif_set_clk()
155 __raw_writel(scr, master_saif->base + SAIF_CTRL); in mxs_saif_set_clk()
197 __raw_writel(scr, master_saif->base + SAIF_CTRL); in mxs_saif_set_clk()
213 stat = __raw_readl(saif->base + SAIF_STAT); in mxs_saif_put_mclk()
223 saif->base + SAIF_CTRL + MXS_SET_ADDR); in mxs_saif_put_mclk()
225 saif->base + SAIF_CTRL + MXS_CLR_ADDR); in mxs_saif_put_mclk()
251 saif->base + SAIF_CTRL + MXS_CLR_ADDR); in mxs_saif_get_mclk()
255 saif->base + SAIF_CTRL + MXS_CLR_ADDR); in mxs_saif_get_mclk()
263 stat = __raw_readl(saif->base + SAIF_STAT); in mxs_saif_get_mclk()
280 saif->base in mxs_saif_get_mclk()
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/third_party/mesa3d/src/gallium/drivers/nouveau/nvc0/
H A Dnvc0_context.c42 struct nouveau_screen *screen = &nvc0->screen->base; in nvc0_svm_migrate()
84 struct nouveau_screen *screen = &nvc0->screen->base; in nvc0_flush()
89 PUSH_KICK(nvc0->base.pushbuf); /* fencing handled in kick_notify */ in nvc0_flush()
91 nouveau_context_update_frame_stats(&nvc0->base); in nvc0_flush()
97 struct nouveau_pushbuf *push = nvc0_context(pipe)->base.pushbuf; in nvc0_texture_barrier()
107 struct nouveau_pushbuf *push = nvc0->base.pushbuf; in nvc0_memory_barrier()
118 nvc0->base.vbo_dirty = true; in nvc0_memory_barrier()
157 nvc0->base.vbo_dirty = true; in nvc0_memory_barrier()
163 struct nouveau_pushbuf *push = nvc0_context(pipe)->base.pushbuf; in nvc0_emit_string_marker()
217 if (nvc0->screen->base in nvc0_context_unreference_resources()
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/kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/nvkm/engine/fifo/
H A Dchang84.c90 g84_fifo_chan_engine_fini(struct nvkm_fifo_chan *base, in g84_fifo_chan_engine_fini() argument
93 struct nv50_fifo_chan *chan = nv50_fifo_chan(base); in g84_fifo_chan_engine_fini()
95 struct nvkm_subdev *subdev = &fifo->base.engine.subdev; in g84_fifo_chan_engine_fini()
107 nvkm_wr32(device, 0x0032fc, chan->base.inst->addr >> 12); in g84_fifo_chan_engine_fini()
115 chan->base.chid, chan->base.object.client->name); in g84_fifo_chan_engine_fini()
133 g84_fifo_chan_engine_init(struct nvkm_fifo_chan *base, in g84_fifo_chan_engine_init() argument
136 struct nv50_fifo_chan *chan = nv50_fifo_chan(base); in g84_fifo_chan_engine_init()
160 g84_fifo_chan_engine_ctor(struct nvkm_fifo_chan *base, in g84_fifo_chan_engine_ctor() argument
164 struct nv50_fifo_chan *chan = nv50_fifo_chan(base); in g84_fifo_chan_engine_ctor()
174 g84_fifo_chan_object_ctor(struct nvkm_fifo_chan *base, struct nvkm_object *object) g84_fifo_chan_object_ctor() argument
205 g84_fifo_chan_init(struct nvkm_fifo_chan *base) g84_fifo_chan_init() argument
[all...]
/kernel/linux/linux-5.10/drivers/rtc/
H A Drtc-tegra.c51 void __iomem *base; /* NULL if not initialized */ member
64 return readl(info->base + TEGRA_RTC_REG_BUSY) & 1; in tegra_rtc_check_busy()
114 readl(info->base + TEGRA_RTC_REG_MILLI_SECONDS); in tegra_rtc_read_time()
115 sec = readl(info->base + TEGRA_RTC_REG_SHADOW_SECONDS); in tegra_rtc_read_time()
140 writel(sec, info->base + TEGRA_RTC_REG_SECONDS); in tegra_rtc_set_time()
143 readl(info->base + TEGRA_RTC_REG_SECONDS)); in tegra_rtc_set_time()
153 sec = readl(info->base + TEGRA_RTC_REG_SECONDS_ALARM0); in tegra_rtc_read_alarm()
164 value = readl(info->base + TEGRA_RTC_REG_INTR_STATUS); in tegra_rtc_read_alarm()
180 status = readl(info->base + TEGRA_RTC_REG_INTR_MASK); in tegra_rtc_alarm_irq_enable()
186 writel(status, info->base in tegra_rtc_alarm_irq_enable()
[all...]
/kernel/linux/linux-5.10/drivers/scsi/arm/
H A Dcumana_1.c48 u8 __iomem *base = hostdata->io; in cumanascsi_pwrite() local
53 writeb(0x02, base + CTRL); in cumanascsi_pwrite()
59 status = readb(base + STAT); in cumanascsi_pwrite()
78 writeb(0x12, base + CTRL); in cumanascsi_pwrite()
83 status = readb(base + STAT); in cumanascsi_pwrite()
93 status = readb(base + STAT); in cumanascsi_pwrite()
104 writeb(hostdata->ctrl | 0x40, base + CTRL); in cumanascsi_pwrite()
115 u8 __iomem *base = hostdata->io; in cumanascsi_pread() local
120 writeb(0x00, base + CTRL); in cumanascsi_pread()
125 status = readb(base in cumanascsi_pread()
186 u8 __iomem *base = hostdata->io; cumanascsi_read() local
202 u8 __iomem *base = hostdata->io; cumanascsi_write() local
299 void __iomem *base = priv(host)->io; cumanascsi1_remove() local
[all...]
/kernel/linux/linux-5.10/drivers/spi/
H A Dspi-oc-tiny.c41 void __iomem *base; member
76 writel(baud, hw->base + TINY_SPI_BAUD); in tiny_spi_setup_transfer()
77 writel(hw->mode, hw->base + TINY_SPI_CONTROL); in tiny_spi_setup_transfer()
95 while (!(readb(hw->base + TINY_SPI_STATUS) & in tiny_spi_wait_txr()
102 while (!(readb(hw->base + TINY_SPI_STATUS) & in tiny_spi_wait_txe()
125 hw->base + TINY_SPI_TXDATA); in tiny_spi_txrx_bufs()
128 hw->base + TINY_SPI_TXDATA); in tiny_spi_txrx_bufs()
130 writeb(TINY_SPI_STATUS_TXR, hw->base + TINY_SPI_STATUS); in tiny_spi_txrx_bufs()
133 hw->base + TINY_SPI_TXDATA); in tiny_spi_txrx_bufs()
135 writeb(TINY_SPI_STATUS_TXE, hw->base in tiny_spi_txrx_bufs()
[all...]

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