Lines Matching refs:base
19 void __iomem *base;
42 void __iomem *base;
51 writel(INDIRECT_CMD_CLR, ctx->base + INDIRECT_CMD_OFF);
53 ret = readl_poll_timeout(ctx->base + INDIRECT_CMD_OFF, cmd,
68 cmd = readl(ctx->base + INDIRECT_CMD_OFF);
72 writel(reg, ctx->base + INDIRECT_ADDR_OFF);
73 writel(INDIRECT_CMD_RD, ctx->base + INDIRECT_CMD_OFF);
75 ret = readl_poll_timeout(ctx->base + INDIRECT_CMD_OFF, ack,
81 tmpval = readl(ctx->base + INDIRECT_RD_OFF);
100 cmd = readl(ctx->base + INDIRECT_CMD_OFF);
104 writel(val, ctx->base + INDIRECT_WR_OFF);
105 writel(reg, ctx->base + INDIRECT_ADDR_OFF);
106 writel(INDIRECT_CMD_WR, ctx->base + INDIRECT_CMD_OFF);
108 ret = readl_poll_timeout(ctx->base + INDIRECT_CMD_OFF, ack,
121 static void pmci_write_fifo(void __iomem *base, const u32 *buf, size_t count)
124 writel(*buf++, base);
127 static void pmci_read_fifo(void __iomem *base, u32 *buf, size_t count)
130 *buf++ = readl(base);
142 false, pmci->base + M10BMC_N6000_FLASH_CTRL);
165 pmci_write_fifo(pmci->base + M10BMC_N6000_FLASH_FIFO,
177 pmci_write_fifo(pmci->base + M10BMC_N6000_FLASH_FIFO, &tmp, 1);
197 writel(addr + offset, pmci->base + M10BMC_N6000_FLASH_ADDR);
200 pmci->base + M10BMC_N6000_FLASH_CTRL);
202 ret = readl_poll_timeout((pmci->base + M10BMC_N6000_FLASH_CTRL), val,
210 pmci_read_fifo(pmci->base + M10BMC_N6000_FLASH_FIFO,
219 writel(0, pmci->base + M10BMC_N6000_FLASH_CTRL);
226 pmci_read_fifo(pmci->base + M10BMC_N6000_FLASH_FIFO, &tmp, 1);
229 writel(0, pmci->base + M10BMC_N6000_FLASH_CTRL);
356 .base = M10BMC_N6000_SYS_BASE,
395 pmci->base = devm_ioremap_resource(dev, &ddev->mmio_res);
396 if (IS_ERR(pmci->base))
397 return PTR_ERR(pmci->base);
405 ctx->base = pmci->base + M10BMC_N6000_INDIRECT_BASE;