Lines Matching refs:base
109 void __iomem *base;
120 spifc->base + SPIFC_A1_USER_CTRL0_REG);
122 return readl_poll_timeout(spifc->base + SPIFC_A1_USER_CTRL0_REG,
135 spifc->base + SPIFC_A1_DBUF_CTRL_REG);
136 ioread32_rep(spifc->base + SPIFC_A1_DBUF_DATA_REG, buf, count);
139 data = readl(spifc->base + SPIFC_A1_DBUF_DATA_REG);
152 spifc->base + SPIFC_A1_DBUF_CTRL_REG);
153 iowrite32_rep(spifc->base + SPIFC_A1_DBUF_DATA_REG, buf, count);
157 writel(data, spifc->base + SPIFC_A1_DBUF_DATA_REG);
163 writel(0, spifc->base + SPIFC_A1_USER_CTRL0_REG);
164 writel(0, spifc->base + SPIFC_A1_USER_CTRL1_REG);
165 writel(0, spifc->base + SPIFC_A1_USER_CTRL2_REG);
166 writel(0, spifc->base + SPIFC_A1_USER_CTRL3_REG);
174 val = readl(spifc->base + SPIFC_A1_USER_CTRL1_REG);
177 writel(val, spifc->base + SPIFC_A1_USER_CTRL1_REG);
185 writel(addr, spifc->base + SPIFC_A1_USER_ADDR_REG);
187 val = readl(spifc->base + SPIFC_A1_USER_CTRL1_REG);
190 writel(val, spifc->base + SPIFC_A1_USER_CTRL1_REG);
196 u32 val = readl(spifc->base + SPIFC_A1_USER_CTRL2_REG);
200 writel(val, spifc->base + SPIFC_A1_USER_CTRL2_REG);
206 u32 val = readl(spifc->base + SPIFC_A1_USER_CTRL3_REG);
213 writel(val, spifc->base + SPIFC_A1_USER_CTRL3_REG);
229 val = readl(spifc->base + SPIFC_A1_USER_CTRL1_REG);
234 writel(val, spifc->base + SPIFC_A1_USER_CTRL1_REG);
279 writel(0, spifc->base + SPIFC_A1_USER_DBUF_ADDR_REG);
305 regv = readl(spifc->base + SPIFC_A1_AHB_REQ_CTRL_REG);
307 writel(regv, spifc->base + SPIFC_A1_AHB_REQ_CTRL_REG);
309 regv = readl(spifc->base + SPIFC_A1_AHB_CTRL_REG);
311 writel(regv, spifc->base + SPIFC_A1_AHB_CTRL_REG);
313 writel(SPIFC_A1_ACTIMING0_VAL, spifc->base + SPIFC_A1_ACTIMING0_REG);
315 writel(0, spifc->base + SPIFC_A1_USER_DBUF_ADDR_REG);
339 spifc->base = devm_platform_ioremap_resource(pdev, 0);
340 if (IS_ERR(spifc->base))
341 return PTR_ERR(spifc->base);