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/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dml/dcn32/
H A Ddcn32_fpu.c176 double pstate_latency_us = clk_mgr->base.ctx->dc->dml.soc.dram_clock_change_latency_us; in dcn32_build_wm_range_table_fpu()
177 double fclk_change_latency_us = clk_mgr->base.ctx->dc->dml.soc.fclk_change_latency_us; in dcn32_build_wm_range_table_fpu()
178 double sr_exit_time_us = clk_mgr->base.ctx->dc->dml.soc.sr_exit_time_us; in dcn32_build_wm_range_table_fpu()
179 double sr_enter_plus_exit_time_us = clk_mgr->base.ctx->dc->dml.soc.sr_enter_plus_exit_time_us; in dcn32_build_wm_range_table_fpu()
181 uint16_t min_uclk_mhz = clk_mgr->base.bw_params->clk_table.entries[0].memclk_mhz; in dcn32_build_wm_range_table_fpu()
182 uint16_t min_dcfclk_mhz = clk_mgr->base.bw_params->clk_table.entries[0].dcfclk_mhz; in dcn32_build_wm_range_table_fpu()
184 uint16_t dcfclk_mhz_for_the_second_state = clk_mgr->base.ctx->dc->dml.soc.clock_limits[2].dcfclk_mhz; in dcn32_build_wm_range_table_fpu()
190 clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.min_dcfclk = dcfclk_mhz_for_the_second_state; in dcn32_build_wm_range_table_fpu()
192 clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.min_dcfclk = clk_mgr->base in dcn32_build_wm_range_table_fpu()
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/third_party/mesa3d/src/amd/common/
H A Dac_nir_lower_ngg.c322 nir_store_shared(b, nir_u2u8(b, surviving_invocations_in_current_wave), wave_id, .base = lds_addr_base); in repack_invocations_in_workgroup()
327 nir_ssa_def *packed_counts = nir_load_shared(b, 1, num_lds_dwords * 32, nir_imm_int(b, 0), .base = lds_addr_base, .align_mul = 8u); in repack_invocations_in_workgroup()
399 nir_ssa_def *vtx = nir_ubfe(b, nir_load_gs_vertex_offset_amd(b, .base = v / 2u), in ngg_nogs_init_vertex_indices_vars()
500 .base = io_sem.location, in emit_store_ngg_nogs_es_primitive_id()
796 nir_store_shared(b, nir_u2u8(b, es_exporter_tid), es_vertex_lds_addr, .base = lds_es_exporter_tid); in compact_vertices_after_culling()
800 nir_store_shared(b, pos, exporter_addr, .base = lds_es_pos_x); in compact_vertices_after_culling()
805 nir_intrinsic_instr *store = nir_store_shared(b, arg_val, exporter_addr, .base = lds_es_arg_0 + 4u * i); in compact_vertices_after_culling()
823 nir_ssa_def *exported_pos = nir_load_shared(b, 4, 32, es_vertex_lds_addr, .base = lds_es_pos_x); in compact_vertices_after_culling()
828 nir_ssa_def *arg_val = nir_load_shared(b, 1, 32, es_vertex_lds_addr, .base = lds_es_arg_0 + 4u * i); in compact_vertices_after_culling()
847 nir_ssa_def *exporter_vtx_idx = nir_load_shared(b, 1, 8, vtx_addr, .base in compact_vertices_after_culling()
1669 unsigned base = nir_intrinsic_base(intrin); lower_ngg_gs_store_output() local
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/third_party/skia/third_party/externals/harfbuzz/src/
H A Dhb-ot-layout-common.hh235 out (out_), base (base_) {} in subset_offset_array_t()
243 bool ret = o->serialize_subset (subset_context, offset, base); in operator ()()
255 const void *base; member
266 base (base_), arg (arg_) {} in subset_offset_array_arg_t()
274 bool ret = o->serialize_subset (subset_context, offset, base, arg); in operator ()()
286 const void *base; member
300 const void *base) const in operator ()()
301 { return subset_offset_array_t<OutputArray> (subset_context, out, base); } in operator ()()
307 const void *base, Arg &&arg) const in operator ()()
308 { return subset_offset_array_arg_t<OutputArray, Arg> (subset_context, out, base, ar in operator ()()
332 const void *base; global() member
369 const void *base; global() member
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/kernel/linux/linux-5.10/drivers/net/ethernet/dlink/
H A Dsundance.c410 void __iomem *base; member
449 void __iomem *ioaddr = np->base + ASICCtrl; in sundance_reset()
536 np->base = ioaddr; in sundance_probe1()
762 void __iomem *mdio_addr = np->base + MIICtrl; in mdio_read()
792 void __iomem *mdio_addr = np->base + MIICtrl; in mdio_write()
838 void __iomem *ioaddr = np->base; in netdev_open()
916 void __iomem *ioaddr = np->base; in check_duplex()
945 void __iomem *ioaddr = np->base; in netdev_timer()
962 void __iomem *ioaddr = np->base; in tx_timeout()
985 ioread32(np->base in tx_timeout()
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/kernel/linux/linux-6.6/drivers/net/ethernet/dlink/
H A Dsundance.c410 void __iomem *base; member
449 void __iomem *ioaddr = np->base + ASICCtrl; in sundance_reset()
538 np->base = ioaddr; in sundance_probe1()
764 void __iomem *mdio_addr = np->base + MIICtrl; in mdio_read()
794 void __iomem *mdio_addr = np->base + MIICtrl; in mdio_write()
840 void __iomem *ioaddr = np->base; in netdev_open()
918 void __iomem *ioaddr = np->base; in check_duplex()
947 void __iomem *ioaddr = np->base; in netdev_timer()
964 void __iomem *ioaddr = np->base; in tx_timeout()
987 ioread32(np->base in tx_timeout()
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/kernel/linux/linux-6.6/drivers/spi/
H A Dspi-omap2-mcspi.c121 /* Virtual base address of the controller */
122 void __iomem *base; member
137 void __iomem *base; member
151 writel_relaxed(val, mcspi->base + idx); in mcspi_write_reg()
158 return readl_relaxed(mcspi->base + idx); in mcspi_read_reg()
166 writel_relaxed(val, cs->base + idx); in mcspi_write_cs_reg()
173 return readl_relaxed(cs->base + idx); in mcspi_read_cs_reg()
447 void __iomem *chstat_reg = cs->base + OMAP2_MCSPI_CHSTAT0; in omap2_mcspi_rx_dma()
655 irqstat_reg = mcspi->base + OMAP2_MCSPI_IRQSTATUS; in omap2_mcspi_txrx_dma()
667 chstat_reg = cs->base in omap2_mcspi_txrx_dma()
694 void __iomem *base = cs->base; omap2_mcspi_txrx_pio() local
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/kernel/linux/linux-6.6/drivers/gpu/drm/msm/adreno/
H A Da6xx_gpu.c61 if (a6xx_gpu->has_whereami && !adreno_gpu->base.hw_apriv) { in update_shadow_rptr()
105 bool sysprof = refcount_read(&a6xx_gpu->base.base.sysprof_active) > 1; in a6xx_set_pagetable()
110 if (ctx->seqno == a6xx_gpu->base.base.cur_ctx_seqno) in a6xx_set_pagetable()
186 * For PM4 the GMU register offsets are calculated from the base of the in a6xx_submit()
1059 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; in a6xx_ucode_check_version()
1060 struct msm_gpu *gpu = &adreno_gpu->base; in a6xx_ucode_check_version()
1152 if ((adreno_gpu->base.hw_apriv || a6xx_gpu->has_whereami) && in a6xx_ucode_load()
1399 if (adreno_gpu->base in hw_init()
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/third_party/skia/third_party/externals/swiftshader/third_party/subzero/src/DartARM32/
H A Dassembler_arm.h37 W = 1 << 21, // writeback base register (or leave unchanged)
237 DA_W = (0|0|1) << 21, // decrement after with writeback to base
238 IA_W = (0|4|1) << 21, // increment after with writeback to base
239 DB_W = (8|0|1) << 21, // decrement before with writeback to base
240 IB_W = (8|4|1) << 21 // increment before with writeback to base
257 Offset = (8|4|0) << 21, // offset (w/o writeback to base)
260 NegOffset = (8|0|0) << 21, // negative offset (w/o writeback to base)
357 FieldAddress(Register base, int32_t disp) in FieldAddress() argument
358 : Address(base, disp - kHeapObjectTag) {} in FieldAddress()
361 FieldAddress(Register base, Registe
947 LoadFieldFromOffset(OperandSize type, Register reg, Register base, int32_t offset, Condition cond = AL) LoadFieldFromOffset() argument
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/third_party/node/deps/v8/src/compiler/backend/mips64/
H A Dinstruction-selector-mips64.cc5 #include "src/base/bits.h"
6 #include "src/base/platform/wrappers.h"
199 Node* base() const { in base() function
262 inputs[0] = g.UseRegister(m.base()); in TryEmitExtendingLoad()
360 Node* base = node->InputAt(0); in EmitLoad() local
366 g.UseRegister(base), g.UseImmediate(index)); in EmitLoad()
370 addr_reg, g.UseRegister(base), g.UseRegister(index)); in EmitLoad()
383 Node* base = node->InputAt(0); in EmitAddBeforeS128LoadStore() local
387 addr_reg, g.UseRegister(base), g.UseRegister(index)); in EmitAddBeforeS128LoadStore()
523 Node* base in VisitStore() local
1832 Node* base = node->InputAt(0); VisitUnalignedLoad() local
1885 Node* base = node->InputAt(0); VisitUnalignedStore() local
2159 Node* base = node->InputAt(0); VisitWord32Compare() local
2210 Node* base = node->InputAt(0); VisitWord32Compare() local
2289 Node* base = node->InputAt(0); VisitWord32Compare() local
2313 Node* base = node->InputAt(0); VisitWord32Compare() local
2339 Node* base = node->InputAt(0); VisitWord32Compare() local
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/kernel/linux/linux-5.10/drivers/gpu/drm/i915/
H A Dintel_pm.c488 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in vlv_get_fifo_size()
862 return crtc->active && crtc->base.primary->state->fb && in intel_crtc_active()
883 struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev); in pnv_update_wm()
905 crtc->base.primary->state->fb; in pnv_update_wm()
1137 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); in g4x_compute_wm()
1237 int num_levels = intel_wm_num_levels(to_i915(plane->base.dev)); in g4x_raw_plane_wm_compute()
1291 plane->base.name, in g4x_raw_plane_wm_compute()
1389 if (new_plane_state->hw.crtc != &crtc->base && in g4x_compute_pipe_wm()
1390 old_plane_state->hw.crtc != &crtc->base) in g4x_compute_pipe_wm()
1454 struct drm_i915_private *dev_priv = to_i915(crtc->base in g4x_compute_intermediate_wm()
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H A Di915_gem.c115 struct intel_runtime_pm *rpm = &to_i915(obj->base.dev)->runtime_pm; in i915_gem_object_unbind()
206 ret = drm_gem_handle_create(file, &obj->base, &handle); in i915_gem_create()
354 loff_t base, int offset, in gtt_user_read()
361 vaddr = io_mapping_map_atomic_wc(mapping, base); in gtt_user_read()
367 vaddr = io_mapping_map_wc(mapping, base, PAGE_SIZE); in gtt_user_read()
380 struct drm_i915_private *i915 = to_i915(obj->base.dev); in i915_gem_gtt_pread()
499 if (range_overflows_t(u64, args->offset, args->size, obj->base.size)) { in i915_gem_pread_ioctl()
538 loff_t base, int offset, in ggtt_write()
545 vaddr = io_mapping_map_atomic_wc(mapping, base); in ggtt_write()
550 vaddr = io_mapping_map_wc(mapping, base, PAGE_SIZ in ggtt_write()
353 gtt_user_read(struct io_mapping *mapping, loff_t base, int offset, char __user *user_data, int length) gtt_user_read() argument
537 ggtt_write(struct io_mapping *mapping, loff_t base, int offset, char __user *user_data, int length) ggtt_write() argument
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/kernel/linux/linux-5.10/drivers/net/phy/
H A Dphy.c288 cmd->base.speed = phydev->speed; in phy_ethtool_ksettings_get()
289 cmd->base.duplex = phydev->duplex; in phy_ethtool_ksettings_get()
290 cmd->base.master_slave_cfg = phydev->master_slave_get; in phy_ethtool_ksettings_get()
291 cmd->base.master_slave_state = phydev->master_slave_state; in phy_ethtool_ksettings_get()
293 cmd->base.port = PORT_BNC; in phy_ethtool_ksettings_get()
295 cmd->base.port = phydev->port; in phy_ethtool_ksettings_get()
296 cmd->base.transceiver = phy_is_internal(phydev) ? in phy_ethtool_ksettings_get()
298 cmd->base.phy_address = phydev->mdio.addr; in phy_ethtool_ksettings_get()
299 cmd->base.autoneg = phydev->autoneg; in phy_ethtool_ksettings_get()
300 cmd->base in phy_ethtool_ksettings_get()
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/kernel/linux/linux-5.10/drivers/gpu/drm/radeon/
H A Drs690.c152 u64 base; in rs690_mc_init() local
164 base = RREG32_MC(R_000100_MCCFG_FB_LOCATION); in rs690_mc_init()
165 base = G_000100_MC_FB_START(base) << 16; in rs690_mc_init()
173 base += 128 * 1024 * 1024; in rs690_mc_init()
191 DRM_INFO("Direct mapping: aper base at 0x%llx, replaced by direct mapping base 0x%llx.\n", in rs690_mc_init()
199 radeon_vram_location(rdev, &rdev->mc, base); in rs690_mc_init()
277 struct drm_display_mode *mode = &crtc->base.mode; in rs690_crtc_bandwidth_compute()
284 if (!crtc->base in rs690_crtc_bandwidth_compute()
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/kernel/linux/linux-6.6/drivers/staging/media/rkvdec/
H A Drkvdec-vp9.c140 struct rkvdec_run base; member
408 return vb2_dma_contig_plane_dma_addr(&buf->base.vb.vb2_buf, 0) + in get_mv_base_addr()
425 writel_relaxed(vb2_dma_contig_plane_dma_addr(&ref_buf->base.vb.vb2_buf, 0), in config_ref_registers()
428 if (&ref_buf->base.vb == run->base.bufs.dst) in config_ref_registers()
506 vp9_ctx->cur.timestamp = buf->base.vb.vb2_buf.timestamp; in update_ctx_cur_info()
532 dst = vb2_to_rkvdec_decoded_buf(&run->base.bufs.dst->vb2_buf); in config_registers()
533 ref_bufs[0] = get_ref_buf(ctx, &dst->base.vb, dec_params->last_frame_ts); in config_registers()
534 ref_bufs[1] = get_ref_buf(ctx, &dst->base.vb, dec_params->golden_frame_ts); in config_registers()
535 ref_bufs[2] = get_ref_buf(ctx, &dst->base in config_registers()
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/kernel/linux/linux-6.6/drivers/crypto/
H A Dimg-hash.c310 if (req->base.complete) in img_hash_finish_req()
494 rctx->fallback_req.base.flags = req->base.flags in img_hash_init()
558 rctx->fallback_req.base.flags = req->base.flags in img_hash_update()
573 rctx->fallback_req.base.flags = req->base.flags in img_hash_final()
587 rctx->fallback_req.base.flags = req->base.flags in img_hash_finup()
603 rctx->fallback_req.base in img_hash_import()
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/kernel/linux/linux-6.6/drivers/pinctrl/intel/
H A Dpinctrl-baytrail.c1394 u32 base, pin; in byt_gpio_irq_handler() local
1399 for (base = 0; base < vg->chip.ngpio; base += 32) { in byt_gpio_irq_handler()
1400 reg = byt_gpio_reg(vg, base, BYT_INT_STAT_REG); in byt_gpio_irq_handler()
1403 dev_warn(vg->dev, "Pin %i: can't retrieve INT_STAT%u\n", base / 32, base); in byt_gpio_irq_handler()
1411 generic_handle_domain_irq(vg->chip.irq.domain, base + pin); in byt_gpio_irq_handler()
1505 u32 base, value; in byt_gpio_irq_init_hw() local
1508 for (base in byt_gpio_irq_init_hw()
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/kernel/linux/linux-6.6/drivers/gpu/drm/i915/display/
H A Dintel_dpio_phy.c275 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in bxt_ddi_phy_set_signal_levels()
592 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in bxt_ddi_phy_set_lane_optim_mask()
620 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in bxt_ddi_phy_get_lane_lat_optim_mask()
643 switch (dig_port->base.port) { in vlv_dig_port_to_channel()
645 MISSING_CASE(dig_port->base.port); in vlv_dig_port_to_channel()
657 switch (dig_port->base.port) { in vlv_dig_port_to_phy()
659 MISSING_CASE(dig_port->base.port); in vlv_dig_port_to_phy()
688 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in chv_set_phy_signal_level()
784 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in chv_data_lane_soft_reset()
829 struct drm_i915_private *dev_priv = to_i915(encoder->base in chv_phy_pre_pll_enable()
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H A Dintel_hotplug_irq.c703 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in ibx_hotplug_enables()
741 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in ibx_hpd_enable_detection()
807 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in icp_ddi_hpd_enable_detection()
823 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in icp_tc_hpd_enable_detection()
885 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in dg1_hpd_enable_detection()
906 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in gen11_tc_hpd_enable_detection()
922 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in gen11_tbt_hpd_enable_detection()
931 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in gen11_hpd_enable_detection()
1001 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in mtp_ddi_hpd_enable_detection()
1017 struct drm_i915_private *i915 = to_i915(encoder->base in mtp_tc_hpd_enable_detection()
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/kernel/linux/linux-6.6/drivers/gpu/drm/radeon/
H A Drs690.c152 u64 base; in rs690_mc_init() local
164 base = RREG32_MC(R_000100_MCCFG_FB_LOCATION); in rs690_mc_init()
165 base = G_000100_MC_FB_START(base) << 16; in rs690_mc_init()
173 base += 128 * 1024 * 1024; in rs690_mc_init()
191 DRM_INFO("Direct mapping: aper base at 0x%llx, replaced by direct mapping base 0x%llx.\n", in rs690_mc_init()
199 radeon_vram_location(rdev, &rdev->mc, base); in rs690_mc_init()
277 struct drm_display_mode *mode = &crtc->base.mode; in rs690_crtc_bandwidth_compute()
284 if (!crtc->base in rs690_crtc_bandwidth_compute()
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/kernel/linux/linux-6.6/drivers/gpu/drm/tegra/
H A Ddrm.c122 pm_runtime_put(context->client->base.dev); in tegra_drm_context_free()
171 struct host1x_client *client = &context->client->base; in tegra_drm_submit()
254 * Gather buffer base address must be 4-bytes aligned, in tegra_drm_submit()
324 err = host1x_job_pin(job, context->client->base.dev); in tegra_drm_submit()
434 err = pm_runtime_resume_and_get(client->base.dev); in tegra_client_open()
440 pm_runtime_put(client->base.dev); in tegra_client_open()
447 pm_runtime_put(client->base.dev); in tegra_client_open()
474 if (client->base.class == args->client) { in tegra_open_channel()
531 if (args->index >= context->client->base.num_syncpts) { in tegra_get_syncpt()
536 syncpt = context->client->base in tegra_get_syncpt()
573 struct host1x_syncpt_base *base; tegra_get_syncpt_base() local
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/third_party/mesa3d/src/gallium/drivers/radeonsi/
H A Dsi_compute.c140 sel->info.base.cs.user_data_components_amd; in si_create_compute_state_async()
144 for (unsigned i = 0; i < MIN2(3, sel->info.base.num_ssbos) && user_sgprs <= 12; i++) { in si_create_compute_state_async()
153 unsigned non_fmask_images = u_bit_consecutive(0, sel->info.base.num_images); in si_create_compute_state_async()
159 non_fmask_images &= ~sel->info.base.msaa_images[0]; in si_create_compute_state_async()
162 unsigned num_sgprs = BITSET_TEST(sel->info.base.image_buffers, i) ? 4 : 8; in si_create_compute_state_async()
237 pipe_reference_init(&sel->base.reference, 1); in si_create_compute_state()
244 sel->info.base.shared_size = cso->req_local_mem; in si_create_compute_state()
530 lds_blocks += align(program->sel.info.base.shared_size, 256) >> 8; in si_switch_compute_shader()
532 lds_blocks += align(program->sel.info.base.shared_size, 512) >> 9; in si_switch_compute_shader()
681 dispatch.group_segment_size = util_cpu_to_le32(program->sel.info.base in si_setup_user_sgprs_co_v2()
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/third_party/node/deps/v8/src/regexp/
H A Dregexp-interpreter.cc9 #include "src/base/small-vector.h"
10 #include "src/base/strings.h"
40 base::Vector<const base::uc16> subject, in BackRefMatchesNoCase()
43 reinterpret_cast<Address>(const_cast<base::uc16*>(&subject.at(from))); in BackRefMatchesNoCase()
45 reinterpret_cast<Address>(const_cast<base::uc16*>(&subject.at(current))); in BackRefMatchesNoCase()
46 size_t length = len * base::kUC16Size; in BackRefMatchesNoCase()
57 base::Vector<const uint8_t> subject, bool unicode) { in BackRefMatchesNoCase()
161 base::SmallVector<ValueT, kStaticCapacity> data_;
204 base
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/kernel/linux/linux-5.10/lib/zstd/
H A Ddecompress.c84 const void *base; /* start of curr segment */ member
111 dctx->base = NULL; in ZSTD_decompressBegin()
578 {{0, 0, 4}}, /* 0 : base, symbol, bits */
646 {{0, 0, 6}}, /* 0 : base, symbol, bits */
714 {{0, 0, 5}}, /* 0 : base, symbol, bits */
874 const BYTE *base; member
880 size_t ZSTD_execSequenceLast7(BYTE *op, BYTE *const oend, seq_t sequence, const BYTE **litPtr, const BYTE *const litLimit, const BYTE *const base, in ZSTD_execSequenceLast7() argument
908 if (sequence.offset > (size_t)(oLitEnd - base)) { in ZSTD_execSequenceLast7()
912 match = dictEnd - (base - match); in ZSTD_execSequenceLast7()
923 match = base; in ZSTD_execSequenceLast7()
1007 ZSTD_execSequence(BYTE *op, BYTE *const oend, seq_t sequence, const BYTE **litPtr, const BYTE *const litLimit, const BYTE *const base, const BYTE *const vBase, const BYTE *const dictEnd) ZSTD_execSequence() argument
1102 const BYTE *const base = (const BYTE *)(dctx->base); ZSTD_decompressSequences() local
1263 ZSTD_execSequenceLong(BYTE *op, BYTE *const oend, seq_t sequence, const BYTE **litPtr, const BYTE *const litLimit, const BYTE *const base, const BYTE *const vBase, const BYTE *const dictEnd) ZSTD_execSequenceLong() argument
1357 const BYTE *const base = (const BYTE *)(dctx->base); ZSTD_decompressSequencesLong() local
[all...]
/third_party/node/deps/v8/src/wasm/
H A Dmodule-decoder.cc7 #include "src/base/functional.h"
8 #include "src/base/platform/platform.h"
9 #include "src/base/platform/wrappers.h"
148 using SpecialSectionPair = std::pair<base::Vector<const char>, SectionCode>; in IdentifyUnknownSectionInternal()
150 {base::StaticCharVector(kNameString), kNameSectionCode}, in IdentifyUnknownSectionInternal()
151 {base::StaticCharVector(kSourceMappingURLString), in IdentifyUnknownSectionInternal()
153 {base::StaticCharVector(kCompilationHintsString), in IdentifyUnknownSectionInternal()
155 {base::StaticCharVector(kBranchHintsString), kBranchHintsSectionCode}, in IdentifyUnknownSectionInternal()
156 {base::StaticCharVector(kDebugInfoString), kDebugInfoSectionCode}, in IdentifyUnknownSectionInternal()
157 {base in IdentifyUnknownSectionInternal()
[all...]
/kernel/linux/linux-5.10/drivers/gpio/
H A Dgpiolib.c112 if (gdev->base <= gpio && in gpio_to_desc()
113 gdev->base + gdev->ngpio > gpio) { in gpio_to_desc()
115 return &gdev->descs[gpio - gdev->base]; in gpio_to_desc()
162 return desc->gdev->base + (desc - &desc->gdev->descs[0]); in desc_to_gpio()
183 int base = ARCH_NR_GPIOS - ngpio; in gpiochip_find_base() local
187 if (gdev->base + gdev->ngpio <= base) in gpiochip_find_base()
190 base = gdev->base - ngpio; in gpiochip_find_base()
193 if (gpio_is_valid(base)) { in gpiochip_find_base()
574 int base = gc->base; gpiochip_add_data_with_key() local
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