Lines Matching refs:base
152 u64 base;
164 base = RREG32_MC(R_000100_MCCFG_FB_LOCATION);
165 base = G_000100_MC_FB_START(base) << 16;
173 base += 128 * 1024 * 1024;
191 DRM_INFO("Direct mapping: aper base at 0x%llx, replaced by direct mapping base 0x%llx.\n",
199 radeon_vram_location(rdev, &rdev->mc, base);
277 struct drm_display_mode *mode = &crtc->base.mode;
284 if (!crtc->base.enabled) {
351 a.full = dfixed_const(crtc->base.mode.crtc_htotal);
359 a.full = dfixed_const(crtc->base.mode.crtc_htotal);
360 b.full = dfixed_const(crtc->base.mode.crtc_hdisplay);
443 wm->priority_mark_max.full = dfixed_const(crtc->base.mode.crtc_hdisplay);
450 if (dfixed_trunc(estimated_width) > crtc->base.mode.crtc_hdisplay) {
599 if (rdev->mode_info.crtcs[0]->base.enabled)
600 mode0 = &rdev->mode_info.crtcs[0]->base.mode;
601 if (rdev->mode_info.crtcs[1]->base.enabled)
602 mode1 = &rdev->mode_info.crtcs[1]->base.mode;