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/third_party/node/lib/
H A Dpath.js135 * base?: string;
144 const base = pathObject.base ||
147 return base;
149 return dir === pathObject.root ? `${dir}${base}` : `${dir}${sep}${base}`;
566 // We get here if `from` is the exact base path for `to`.
579 // We get here if `to` is the exact base path for `from`.
907 * base: string;
915 const ret = { root: '', dir: '', base
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/third_party/node/deps/icu-small/source/i18n/
H A Dolsontz.cpp422 // immutable (except for the ID, which is in the base class). in setRawOffset()
880 OlsonTimeZone::getNextTransition(UDate base, UBool inclusive, TimeZoneTransition& result) const { in getNextTransition() argument
888 if (inclusive && base == firstFinalTZTransition->getTime()) { in getNextTransition()
891 } else if (base >= firstFinalTZTransition->getTime()) { in getNextTransition()
893 //return finalZone->getNextTransition(base, inclusive, result); in getNextTransition()
894 return finalZoneWithStartYear->getNextTransition(base, inclusive, result); in getNextTransition()
907 if (base > t || (!inclusive && base == t)) { in getNextTransition()
945 OlsonTimeZone::getPreviousTransition(UDate base, UBool inclusive, TimeZoneTransition& result) const { in getPreviousTransition() argument
953 if (inclusive && base in getPreviousTransition()
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/third_party/skia/third_party/externals/icu/source/i18n/
H A Dolsontz.cpp422 // immutable (except for the ID, which is in the base class). in setRawOffset()
881 OlsonTimeZone::getNextTransition(UDate base, UBool inclusive, TimeZoneTransition& result) const { in getNextTransition() argument
889 if (inclusive && base == firstFinalTZTransition->getTime()) { in getNextTransition()
892 } else if (base >= firstFinalTZTransition->getTime()) { in getNextTransition()
894 //return finalZone->getNextTransition(base, inclusive, result); in getNextTransition()
895 return finalZoneWithStartYear->getNextTransition(base, inclusive, result); in getNextTransition()
908 if (base > t || (!inclusive && base == t)) { in getNextTransition()
946 OlsonTimeZone::getPreviousTransition(UDate base, UBool inclusive, TimeZoneTransition& result) const { in getPreviousTransition() argument
954 if (inclusive && base in getPreviousTransition()
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/kernel/linux/linux-5.10/drivers/gpu/drm/sun4i/
H A Dsun8i_vi_scaler.c870 static void sun8i_vi_scaler_set_coeff(struct regmap *map, u32 base, in sun8i_vi_scaler_set_coeff() argument
890 regmap_write(map, SUN8I_SCALER_VSU_YHCOEFF0(base, i), in sun8i_vi_scaler_set_coeff()
892 regmap_write(map, SUN8I_SCALER_VSU_YHCOEFF1(base, i), in sun8i_vi_scaler_set_coeff()
894 regmap_write(map, SUN8I_SCALER_VSU_CHCOEFF0(base, i), in sun8i_vi_scaler_set_coeff()
896 regmap_write(map, SUN8I_SCALER_VSU_CHCOEFF1(base, i), in sun8i_vi_scaler_set_coeff()
903 regmap_write(map, SUN8I_SCALER_VSU_YVCOEFF(base, i), in sun8i_vi_scaler_set_coeff()
905 regmap_write(map, SUN8I_SCALER_VSU_CVCOEFF(base, i), in sun8i_vi_scaler_set_coeff()
912 u32 val, base; in sun8i_vi_scaler_enable() local
914 base = sun8i_vi_scaler_base(mixer, layer); in sun8i_vi_scaler_enable()
923 SUN8I_SCALER_VSU_CTRL(base), va in sun8i_vi_scaler_enable()
933 u32 base; sun8i_vi_scaler_setup() local
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/kernel/linux/linux-6.6/arch/x86/events/intel/
H A Dds.c765 struct bts_record *at, *base, *top; in intel_pmu_drain_bts_buffer() local
778 base = (struct bts_record *)(unsigned long)ds->bts_buffer_base; in intel_pmu_drain_bts_buffer()
781 if (top <= base) in intel_pmu_drain_bts_buffer()
800 for (at = base; at < top; at++) { in intel_pmu_drain_bts_buffer()
821 header.size * (top - base - skip))) in intel_pmu_drain_bts_buffer()
824 for (at = base; at < top; at++) { in intel_pmu_drain_bts_buffer()
1303 u32 base = MSR_RELOAD_PMC0; in intel_pmu_pebs_via_pt_enable() local
1315 base = MSR_RELOAD_FIXED_CTR0; in intel_pmu_pebs_via_pt_enable()
1322 wrmsrl(base + idx, value); in intel_pmu_pebs_via_pt_enable()
1661 * We use the interrupt regs as a base becaus in setup_pebs_fixed_sample_data()
1927 get_next_pebs_record_by_bit(void *base, void *top, int bit) get_next_pebs_record_by_bit() argument
2035 __intel_pmu_pebs_event(struct perf_event *event, struct pt_regs *iregs, struct perf_sample_data *data, void *base, void *top, int bit, int count, void (*setup_sample)(struct perf_event *, struct pt_regs *, void *, struct perf_sample_data *, struct pt_regs *)) __intel_pmu_pebs_event() argument
2156 void *base, *at, *top; intel_pmu_drain_pebs_nhm() local
2273 void *base, *at, *top; intel_pmu_drain_pebs_icl() local
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/kernel/linux/linux-6.6/drivers/gpu/drm/sun4i/
H A Dsun8i_vi_scaler.c870 static void sun8i_vi_scaler_set_coeff(struct regmap *map, u32 base, in sun8i_vi_scaler_set_coeff() argument
890 regmap_write(map, SUN8I_SCALER_VSU_YHCOEFF0(base, i), in sun8i_vi_scaler_set_coeff()
892 regmap_write(map, SUN8I_SCALER_VSU_YHCOEFF1(base, i), in sun8i_vi_scaler_set_coeff()
894 regmap_write(map, SUN8I_SCALER_VSU_CHCOEFF0(base, i), in sun8i_vi_scaler_set_coeff()
896 regmap_write(map, SUN8I_SCALER_VSU_CHCOEFF1(base, i), in sun8i_vi_scaler_set_coeff()
903 regmap_write(map, SUN8I_SCALER_VSU_YVCOEFF(base, i), in sun8i_vi_scaler_set_coeff()
905 regmap_write(map, SUN8I_SCALER_VSU_CVCOEFF(base, i), in sun8i_vi_scaler_set_coeff()
912 u32 val, base; in sun8i_vi_scaler_enable() local
914 base = sun8i_vi_scaler_base(mixer, layer); in sun8i_vi_scaler_enable()
923 SUN8I_SCALER_VSU_CTRL(base), va in sun8i_vi_scaler_enable()
933 u32 base; sun8i_vi_scaler_setup() local
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/kernel/linux/linux-6.6/sound/pci/emu10k1/
H A Demumixer.c77 #define PAIR_PS(base, one, two, sfx) base " " one sfx, base " " two sfx
78 #define LR_PS(base, sfx) PAIR_PS(base, "Left", "Right", sfx)
84 #define PAIR_REGS(base, one, two) \
85 base ## one ## 1, \
86 base ## two ## 1
88 #define LR_REGS(base) PAIR_REGS(base, _LEF
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/third_party/node/deps/v8/src/compiler/backend/
H A Dinstruction.h11 #include "src/base/compiler-specific.h"
12 #include "src/base/numbers/double.h"
151 using KindField = base::BitField64<Kind, 0, 3>;
361 // instead of using the base::BitField utility class.
365 using VirtualRegisterField = base::BitField64<uint32_t, 3, 32>;
367 // base::BitFields for all unallocated operands.
368 using BasicPolicyField = base::BitField64<BasicPolicy, 35, 1>;
371 using FixedSlotIndexField = base::BitField64<int, 36, 28>;
374 using ExtendedPolicyField = base::BitField64<ExtendedPolicy, 36, 3>;
375 using LifetimeField = base
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/third_party/mesa3d/src/gallium/drivers/d3d12/
H A Dd3d12_compiler.cpp96 struct d3d12_screen *screen = d3d12_screen(ctx->base.screen); in compile_nir()
113 screen->base.get_paramf(&screen->base, PIPE_CAPF_MAX_TEXTURE_LOD_BIAS)); in compile_nir()
356 if (((ctx->gfx_pipeline_state.rast->base.fill_front == PIPE_POLYGON_MODE_LINE && in fill_mode_lowered()
357 ctx->gfx_pipeline_state.rast->base.cull_face != PIPE_FACE_FRONT) || in fill_mode_lowered()
358 (ctx->gfx_pipeline_state.rast->base.fill_back == PIPE_POLYGON_MODE_LINE && in fill_mode_lowered()
359 ctx->gfx_pipeline_state.rast->base.cull_face == PIPE_FACE_FRONT)) && in fill_mode_lowered()
364 if (ctx->gfx_pipeline_state.rast->base.fill_front == PIPE_POLYGON_MODE_POINT) in fill_mode_lowered()
393 ctx->gfx_pipeline_state.rast->base.point_size > 1.0) && in needs_point_sprite_lowering()
400 (ctx->gfx_pipeline_state.rast->base in needs_point_sprite_lowering()
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/kernel/linux/linux-6.6/drivers/net/ethernet/marvell/mvpp2/
H A Dmvpp2_main.c1697 val = readl(port->base + MVPP22_GMAC_INT_SUM_MASK); in mvpp22_gop_unmask_irq()
1699 writel(val, port->base + MVPP22_GMAC_INT_SUM_MASK); in mvpp22_gop_unmask_irq()
1704 val = readl(port->base + MVPP22_XLG_EXT_INT_MASK); in mvpp22_gop_unmask_irq()
1709 writel(val, port->base + MVPP22_XLG_EXT_INT_MASK); in mvpp22_gop_unmask_irq()
1718 val = readl(port->base + MVPP22_XLG_EXT_INT_MASK); in mvpp22_gop_mask_irq()
1721 writel(val, port->base + MVPP22_XLG_EXT_INT_MASK); in mvpp22_gop_mask_irq()
1727 val = readl(port->base + MVPP22_GMAC_INT_SUM_MASK); in mvpp22_gop_mask_irq()
1729 writel(val, port->base + MVPP22_GMAC_INT_SUM_MASK); in mvpp22_gop_mask_irq()
1737 mvpp2_modify(port->base + MVPP22_GMAC_INT_SUM_MASK, in mvpp22_gop_setup_irq()
1745 val = readl(port->base in mvpp22_gop_setup_irq()
7412 void __iomem *base; mvpp2_get_sram() local
7437 void __iomem *base; mvpp2_probe() local
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/base/security/crypto_framework/test/unittest/src/
H A Dcrypto_ecc_key_util_test.cpp334 const char *classname = returnObj->base.getClass(); in HWTEST_F()
359 returnObj->base.destroy(&g_obj); in HWTEST_F()
433 const char *classname = returnKeyPair->base.getClass(); in HWTEST_F()
465 returnKeyPair->base.destroy(&(returnKeyPair->base)); in HWTEST_F()
492 returnKeyPair->base.destroy(nullptr); in HWTEST_F()
520 returnKeyPair->base.destroy(&g_obj); in HWTEST_F()
545 const char *classname = returnKeyPair->pubKey->base.base.getClass(); in HWTEST_F()
655 const char * format = returnKeyPair->pubKey->base in HWTEST_F()
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H A Dcrypto_dsa_verify_test.cpp48 const char *verifyClassName = verify->base.getClass(); in HWTEST_F()
61 verify->base.destroy(&(verify->base)); in HWTEST_F()
/kernel/linux/linux-6.6/drivers/perf/
H A Darm-cmn.c303 void __iomem *base; member
313 void __iomem *base; member
327 void __iomem *base; member
1369 writel_relaxed(0, cmn->dtc[0].base + CMN_DT_PMCR); in arm_cmn_set_state()
1378 cmn->dtc[0].base + CMN_DT_PMCR); in arm_cmn_clear_state()
1403 reg = readq_relaxed(dtm->base + offset); in arm_cmn_read_dtm()
1413 u64 val = readq_relaxed(dtc->base + CMN_DT_PMCCNTR); in arm_cmn_read_cc()
1415 writeq_relaxed(CMN_CC_INIT, dtc->base + CMN_DT_PMCCNTR); in arm_cmn_read_cc()
1423 val = readl_relaxed(dtc->base + pmevcnt); in arm_cmn_read_counter()
1424 writel_relaxed(CMN_COUNTER_INIT, dtc->base in arm_cmn_read_counter()
1530 void __iomem *base = dn->pmu_base + CMN_DTM_OFFSET(hw->dtm_offset); arm_cmn_event_start() local
1558 void __iomem *base = dn->pmu_base + CMN_DTM_OFFSET(hw->dtm_offset); arm_cmn_event_stop() local
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/third_party/node/deps/v8/src/wasm/
H A Dgraph-builder-interface.cc84 using ValueVector = base::SmallVector<Value, 8>;
85 using NodeVector = base::SmallVector<TFNode*, 8>;
127 base::MutexGuard mutex_guard(&feedbacks.mutex); in StartFunction()
418 void AllocateLocals(FullDecoder* decoder, base::Vector<Value> local_values) { in AllocateLocals()
494 GetNodes(values.begin(), base::VectorOf(stack_values)); in DoReturn()
502 builder_->TraceFunctionExit(base::VectorOf(values), decoder->position()); in DoReturn()
504 builder_->Return(base::VectorOf(values)); in DoReturn()
823 void SimdOp(FullDecoder* decoder, WasmOpcode opcode, base::Vector<Value> args, in SimdOp()
833 base::Vector<Value> inputs, Value* result) { in SimdLaneOp()
848 const base in Throw()
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/third_party/mesa3d/src/gallium/drivers/zink/
H A Dzink_descriptors.c89 struct zink_program_descriptor_data base; member
127 return sampler_view->base.target == PIPE_BUFFER ? in get_sampler_view_hash()
134 if (!image_view || !image_view->base.resource) in get_image_view_hash()
136 return image_view->base.resource->target == PIPE_BUFFER ? in get_image_view_hash()
144 (is_buffer ? zink_screen(ctx->base.screen)->null_descriptor_hashes.buffer_view : in zink_get_sampler_view_hash()
145 zink_screen(ctx->base.screen)->null_descriptor_hashes.image_view); in zink_get_sampler_view_hash()
152 (is_buffer ? zink_screen(ctx->base.screen)->null_descriptor_hashes.buffer_view : in zink_get_image_view_hash()
153 zink_screen(ctx->base.screen)->null_descriptor_hashes.image_view); in zink_get_image_view_hash()
160 return dsurf->is_buffer ? (dsurf->bufferview ? dsurf->bufferview->hash : zink_screen(ctx->base.screen)->null_descriptor_hashes.buffer_view) : in get_descriptor_surface_hash()
161 (dsurf->surface ? dsurf->surface->hash : zink_screen(ctx->base in get_descriptor_surface_hash()
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/kernel/linux/linux-6.6/drivers/net/vmxnet3/
H A Dvmxnet3_drv.c368 BUG_ON(VMXNET3_TXDESC_GET_EOP(&(tq->tx_ring.base[eop_idx].txd)) != 1); in vmxnet3_unmap_pkt()
411 gdesc = tq->comp_ring.base + tq->comp_ring.next2proc; in vmxnet3_tq_tx_complete()
423 gdesc = tq->comp_ring.base + tq->comp_ring.next2proc; in vmxnet3_tq_tx_complete()
489 if (tq->tx_ring.base) { in vmxnet3_tq_destroy()
492 tq->tx_ring.base, tq->tx_ring.basePA); in vmxnet3_tq_destroy()
493 tq->tx_ring.base = NULL; in vmxnet3_tq_destroy()
495 if (tq->data_ring.base) { in vmxnet3_tq_destroy()
498 tq->data_ring.base, tq->data_ring.basePA); in vmxnet3_tq_destroy()
499 tq->data_ring.base = NULL; in vmxnet3_tq_destroy()
501 if (tq->comp_ring.base) { in vmxnet3_tq_destroy()
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/third_party/mesa3d/src/gallium/frontends/nine/
H A Ddevice9.c188 HRESULT hr = NineUnknown_ctor(&This->base, pParams); in NineDevice9_ctor()
662 NineUnknown_dtor(&This->base); in NineDevice9_dtor()
857 util_format_unpack_rgba_8unorm_rect(surf->base.info.format, ptr, transfer->stride, in NineDevice9_SetCursorProperties()
865 util_format_unpack_rgba_8unorm_rect(surf->base.info.format, in NineDevice9_SetCursorProperties()
1346 if (surface->base.resource && Discard_or_Lockable && (type != 1)) in create_zs_or_rt_surface()
1347 surface->base.resource->flags |= NINE_RESOURCE_FLAG_LOCKABLE; in create_zs_or_rt_surface()
1417 user_assert(dst->base.pool == D3DPOOL_DEFAULT, D3DERR_INVALIDCALL); in NineDevice9_UpdateSurface()
1418 user_assert(src->base.pool == D3DPOOL_SYSTEMMEM, D3DERR_INVALIDCALL); in NineDevice9_UpdateSurface()
1460 const unsigned w = util_format_get_blockwidth(dst->base.info.format); in NineDevice9_UpdateSurface()
1461 const unsigned h = util_format_get_blockheight(dst->base in NineDevice9_UpdateSurface()
3143 unsigned base; NineDevice9_DrawIndexedPrimitiveUP() local
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/base/startup/init/services/loopevent/task/
H A Dle_task.h79 BaseTask base; member
85 BaseTask base; member
120 BaseTask base; member
/kernel/linux/linux-5.10/arch/arm/mach-mvebu/
H A Dboard-v7.c87 u64 base, size; in mvebu_scan_mem() local
89 base = dt_mem_next_cell(dt_root_addr_cells, &reg); in mvebu_scan_mem()
92 memblock_reserve(base, MVEBU_DDR_TRAINING_AREA_SZ); in mvebu_scan_mem()
/kernel/linux/linux-5.10/arch/x86/mm/
H A Dmmap.c118 static void arch_pick_mmap_base(unsigned long *base, unsigned long *legacy_base, in arch_pick_mmap_base() argument
124 *base = *legacy_base; in arch_pick_mmap_base()
126 *base = mmap_base(random_factor, task_size, rlim_stack); in arch_pick_mmap_base()
142 * The mmap syscall mapping base decision depends solely on the in arch_pick_mmap_layout()
H A Dkaslr.c19 * options and randomizes the base and space between each. The size of the
49 unsigned long *base; member
63 /* Initialize base and padding for each memory region randomized with KASLR */
95 BUG_ON(kaslr_regions[0].base != &page_offset_base); in kernel_randomize_memory()
129 *kaslr_regions[i].base = vaddr; in kernel_randomize_memory()
/kernel/linux/linux-5.10/arch/arm/mach-highbank/
H A Dhighbank.c33 unsigned long base; in highbank_scu_map_io() local
35 /* Get SCU base */ in highbank_scu_map_io()
36 asm("mrc p15, 4, %0, c15, c0, 0" : "=r" (base)); in highbank_scu_map_io()
38 scu_base_addr = ioremap(base, SZ_4K); in highbank_scu_map_io()
/kernel/linux/linux-5.10/arch/ia64/uv/kernel/
H A Dsetup.c38 static __init void get_lowmem_redirect(unsigned long *base, unsigned long *size) in get_lowmem_redirect() argument
46 if (alias.s.base == 0) { in get_lowmem_redirect()
49 *base = (unsigned long)redirect.s.dest_base << DEST_SHIFT; in get_lowmem_redirect()
100 printk(KERN_DEBUG "UV: global MMR base 0x%lx\n", mmr_base); in uv_setup()
/kernel/linux/linux-5.10/arch/x86/kernel/
H A Dstep.c32 unsigned long base; in convert_ip_to_linear() local
42 base = get_desc_base(desc); in convert_ip_to_linear()
47 addr += base; in convert_ip_to_linear()
/kernel/linux/linux-5.10/arch/sh/boards/mach-x3proto/
H A Dgpio.c81 .base = -1,
118 x3proto_gpio_chip.label, x3proto_gpio_chip.base, in x3proto_gpio_setup()
119 x3proto_gpio_chip.base + x3proto_gpio_chip.ngpio, in x3proto_gpio_setup()

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