Lines Matching refs:base
303 void __iomem *base;
313 void __iomem *base;
327 void __iomem *base;
1369 writel_relaxed(0, cmn->dtc[0].base + CMN_DT_PMCR);
1378 cmn->dtc[0].base + CMN_DT_PMCR);
1403 reg = readq_relaxed(dtm->base + offset);
1413 u64 val = readq_relaxed(dtc->base + CMN_DT_PMCCNTR);
1415 writeq_relaxed(CMN_CC_INIT, dtc->base + CMN_DT_PMCCNTR);
1423 val = readl_relaxed(dtc->base + pmevcnt);
1424 writel_relaxed(CMN_COUNTER_INIT, dtc->base + pmevcnt);
1436 writel_relaxed(CMN_COUNTER_INIT, cmn->dtc[i].base + pmevcnt);
1522 writeq_relaxed(CMN_CC_INIT, cmn->dtc[i].base + CMN_DT_PMCCNTR);
1530 void __iomem *base = dn->pmu_base + CMN_DTM_OFFSET(hw->dtm_offset);
1532 writeq_relaxed(val, base + CMN_DTM_WPn_VAL(wp_idx));
1533 writeq_relaxed(mask, base + CMN_DTM_WPn_MASK(wp_idx));
1558 void __iomem *base = dn->pmu_base + CMN_DTM_OFFSET(hw->dtm_offset);
1560 writeq_relaxed(0, base + CMN_DTM_WPn_MASK(wp_idx));
1561 writeq_relaxed(~0ULL, base + CMN_DTM_WPn_VAL(wp_idx));
1782 writel_relaxed(dtm->pmu_config_low, dtm->base + CMN_DTM_PMU_CONFIG);
1849 writel_relaxed(cfg, dtm->base + CMN_DTM_WPn_CONFIG(wp_idx));
1871 writeq_relaxed(reg, dtm->base + CMN_DTM_PMU_CONFIG);
1973 u32 status = readl_relaxed(dtc->base + CMN_DT_PMOVSR);
1995 writel_relaxed(status, dtc->base + CMN_DT_PMOVSR_CLR);
2035 dtm->base = xp->pmu_base + CMN_DTM_OFFSET(idx);
2037 writeq_relaxed(dtm->pmu_config_low, dtm->base + CMN_DTM_PMU_CONFIG);
2040 writeq_relaxed(0, dtm->base + CMN_DTM_WPn_MASK(i));
2041 writeq_relaxed(~0ULL, dtm->base + CMN_DTM_WPn_VAL(i));
2049 dtc->base = dn->pmu_base - CMN_PMU_OFFSET;
2054 writel_relaxed(CMN_DT_DTC_CTL_DT_EN, dtc->base + CMN_DT_DTC_CTL);
2055 writel_relaxed(CMN_DT_PMCR_PMU_EN | CMN_DT_PMCR_OVFL_INTR_EN, dtc->base + CMN_DT_PMCR);
2056 writeq_relaxed(0, dtc->base + CMN_DT_PMCCNTR);
2057 writel_relaxed(0x1ff, dtc->base + CMN_DT_PMOVSR_CLR);
2135 u64 reg = readq_relaxed(cmn->base + offset + CMN_NODE_INFO);
2141 node->pmu_base = cmn->base + offset + CMN_PMU_OFFSET;
2183 cfg_region = cmn->base + rgn_offset;
2220 reg = readq_relaxed(cmn->base + xp_offset[i] + CMN_CHILD_INFO);
2246 void __iomem *xp_region = cmn->base + xp_offset[i];
2350 * base address lets us handle the second pmu_event_sel
2423 cmn->base = devm_ioremap(cmn->dev, cfg->start, resource_size(cfg));
2424 if (!cmn->base)
2456 cmn->base = devm_platform_ioremap_resource(pdev, 0);
2457 if (IS_ERR(cmn->base))
2458 return PTR_ERR(cmn->base);
2518 writel_relaxed(0, cmn->dtc[0].base + CMN_DT_DTC_CTL);