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/kernel/linux/linux-6.6/drivers/i2c/busses/
H A Di2c-elektor.c37 static int base; variable
136 if (!request_region(base, 2, pcf_isa_ops.name)) { in pcf_isa_init()
138 "in use\n", pcf_isa_ops.name, base); in pcf_isa_init()
141 base_iomem = ioport_map(base, 2); in pcf_isa_init()
144 pcf_isa_ops.name, base); in pcf_isa_init()
145 release_region(base, 2); in pcf_isa_init()
149 if (!request_mem_region(base, 2, pcf_isa_ops.name)) { in pcf_isa_init()
151 "is in use\n", pcf_isa_ops.name, base); in pcf_isa_init()
154 base_iomem = ioremap(base, 2); in pcf_isa_init()
157 "failed\n", pcf_isa_ops.name, base); in pcf_isa_init()
[all...]
/kernel/linux/linux-6.6/drivers/irqchip/
H A Dirq-loongson-pch-lpc.c30 void __iomem *base; member
47 writel(0x1 << d->hwirq, priv->base + LPC_INT_CLR); in lpc_irq_ack()
57 writel(readl(priv->base + LPC_INT_ENA) & (~(0x1 << (d->hwirq))), in lpc_irq_mask()
58 priv->base + LPC_INT_ENA); in lpc_irq_mask()
68 writel(readl(priv->base + LPC_INT_ENA) | (0x1 << (d->hwirq)), in lpc_irq_unmask()
69 priv->base + LPC_INT_ENA); in lpc_irq_unmask()
82 val = readl(priv->base + LPC_INT_POL); in lpc_irq_set_type()
89 writel(val, priv->base + LPC_INT_POL); in lpc_irq_set_type()
111 pending = readl(priv->base + LPC_INT_ENA); in lpc_irq_dispatch()
112 pending &= readl(priv->base in lpc_irq_dispatch()
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/third_party/gn/src/gn/
H A Dsetup_unittest.cc7 #include "base/command_line.h"
8 #include "base/files/file_path.h"
9 #include "base/files/file_util.h"
10 #include "base/files/scoped_temp_dir.h"
19 static void WriteFile(const base::FilePath& file, const std::string& data) { in WriteFile()
21 base::WriteFile(file, data.data(), data.size())); in WriteFile()
25 base::CommandLine cmdline(base::CommandLine::NO_PROGRAM); in TEST_F()
29 base::ScopedTempDir in_temp_dir; in TEST_F()
31 base in TEST_F()
[all...]
/third_party/skia/third_party/externals/zlib/google/
H A Dzip_writer.cc7 #include "base/files/file.h"
8 #include "base/logging.h"
9 #include "base/strings/string_util.h"
21 base::File file, in AddFileContentToZip()
22 const base::FilePath& file_path) { in AddFileContentToZip()
41 const base::FilePath& path, in OpenNewFileEntry()
43 base::Time last_modified) { in OpenNewFileEntry()
46 base::ReplaceSubstringsAfterOffset(&str_path, 0u, "\\", "/"); in OpenNewFileEntry()
59 const base::FilePath& path, in AddFileEntryToZip()
60 base in AddFileEntryToZip()
[all...]
/kernel/linux/linux-5.10/arch/arm/mach-aspeed/
H A Dplatsmp.c17 void __iomem *base; in aspeed_g6_boot_secondary() local
19 base = of_iomap(secboot_node, 0); in aspeed_g6_boot_secondary()
20 if (!base) { in aspeed_g6_boot_secondary()
21 pr_err("could not map the secondary boot base!"); in aspeed_g6_boot_secondary()
25 writel_relaxed(0, base + BOOT_ADDR); in aspeed_g6_boot_secondary()
26 writel_relaxed(__pa_symbol(secondary_startup_arm), base + BOOT_ADDR); in aspeed_g6_boot_secondary()
27 writel_relaxed((0xABBAAB00 | (cpu & 0xff)), base + BOOT_SIG); in aspeed_g6_boot_secondary()
31 iounmap(base); in aspeed_g6_boot_secondary()
38 void __iomem *base; in aspeed_g6_smp_prepare_cpus() local
46 base in aspeed_g6_smp_prepare_cpus()
[all...]
/kernel/linux/linux-6.6/arch/arm/mach-aspeed/
H A Dplatsmp.c17 void __iomem *base; in aspeed_g6_boot_secondary() local
19 base = of_iomap(secboot_node, 0); in aspeed_g6_boot_secondary()
20 if (!base) { in aspeed_g6_boot_secondary()
21 pr_err("could not map the secondary boot base!"); in aspeed_g6_boot_secondary()
25 writel_relaxed(0, base + BOOT_ADDR); in aspeed_g6_boot_secondary()
26 writel_relaxed(__pa_symbol(secondary_startup_arm), base + BOOT_ADDR); in aspeed_g6_boot_secondary()
27 writel_relaxed((0xABBAAB00 | (cpu & 0xff)), base + BOOT_SIG); in aspeed_g6_boot_secondary()
31 iounmap(base); in aspeed_g6_boot_secondary()
38 void __iomem *base; in aspeed_g6_smp_prepare_cpus() local
46 base in aspeed_g6_smp_prepare_cpus()
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/kernel/linux/linux-5.10/arch/arm64/crypto/
H A Dsha256-glue.c74 .base.cra_name = "sha256",
75 .base.cra_driver_name = "sha256-arm64",
76 .base.cra_priority = 125,
77 .base.cra_blocksize = SHA256_BLOCK_SIZE,
78 .base.cra_module = THIS_MODULE,
86 .base.cra_name = "sha224",
87 .base.cra_driver_name = "sha224-arm64",
88 .base.cra_priority = 125,
89 .base.cra_blocksize = SHA224_BLOCK_SIZE,
90 .base
[all...]
H A Dsha3-ce-glue.c115 .base.cra_name = "sha3-224",
116 .base.cra_driver_name = "sha3-224-ce",
117 .base.cra_blocksize = SHA3_224_BLOCK_SIZE,
118 .base.cra_module = THIS_MODULE,
119 .base.cra_priority = 200,
126 .base.cra_name = "sha3-256",
127 .base.cra_driver_name = "sha3-256-ce",
128 .base.cra_blocksize = SHA3_256_BLOCK_SIZE,
129 .base.cra_module = THIS_MODULE,
130 .base
[all...]
/kernel/linux/linux-6.6/arch/arm64/crypto/
H A Dsha256-glue.c75 .base.cra_name = "sha256",
76 .base.cra_driver_name = "sha256-arm64",
77 .base.cra_priority = 125,
78 .base.cra_blocksize = SHA256_BLOCK_SIZE,
79 .base.cra_module = THIS_MODULE,
87 .base.cra_name = "sha224",
88 .base.cra_driver_name = "sha224-arm64",
89 .base.cra_priority = 125,
90 .base.cra_blocksize = SHA224_BLOCK_SIZE,
91 .base
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H A Dsha3-ce-glue.c115 .base.cra_name = "sha3-224",
116 .base.cra_driver_name = "sha3-224-ce",
117 .base.cra_blocksize = SHA3_224_BLOCK_SIZE,
118 .base.cra_module = THIS_MODULE,
119 .base.cra_priority = 200,
126 .base.cra_name = "sha3-256",
127 .base.cra_driver_name = "sha3-256-ce",
128 .base.cra_blocksize = SHA3_256_BLOCK_SIZE,
129 .base.cra_module = THIS_MODULE,
130 .base
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/kernel/linux/linux-6.6/drivers/video/
H A Daperture.c37 * resource_size_t base, size;
43 * base = mem->start;
46 * ret = aperture_remove_conflicting_devices(base, size, "example");
87 * resource_size_t base, size;
92 * base = mem->start;
95 * ret = devm_aperture_acquire_for_platform_device(pdev, base, size);
135 resource_size_t base; member
164 resource_size_t base, resource_size_t size, in devm_aperture_acquire()
167 size_t end = base + size; in devm_aperture_acquire()
175 if (overlap(base, en in devm_aperture_acquire()
163 devm_aperture_acquire(struct device *dev, resource_size_t base, resource_size_t size, void (*detach)(struct device *)) devm_aperture_acquire() argument
239 devm_aperture_acquire_for_platform_device(struct platform_device *pdev, resource_size_t base, resource_size_t size) devm_aperture_acquire_for_platform_device() argument
247 aperture_detach_devices(resource_size_t base, resource_size_t size) aperture_detach_devices() argument
284 aperture_remove_conflicting_devices(resource_size_t base, resource_size_t size, const char *name) aperture_remove_conflicting_devices() argument
350 resource_size_t base, size; aperture_remove_conflicting_pci_devices() local
[all...]
/third_party/node/deps/v8/third_party/zlib/google/
H A Dzip_reader.h14 #include "base/callback.h"
15 #include "base/files/file.h"
16 #include "base/files/file_path.h"
17 #include "base/memory/weak_ptr.h"
18 #include "base/numerics/safe_conversions.h"
19 #include "base/time/time.h"
44 virtual void SetTimeModified(const base::Time& time) {} in SetTimeModified()
82 using SuccessCallback = base::OnceClosure;
84 using FailureCallback = base::OnceClosure;
87 using ProgressCallback = base
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/kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/
H A Dnv50.c24 #define nv50_instmem(p) container_of((p), struct nv50_instmem, base)
33 struct nvkm_instmem base; member
43 #define nv50_instobj(p) container_of((p), struct nv50_instobj, base.memory)
46 struct nvkm_instobj base; member
60 struct nvkm_device *device = imem->base.subdev.device; in nv50_instobj_wr32_slow()
61 u64 base = (nvkm_memory_addr(iobj->ram) + offset) & 0xffffff00000ULL; in nv50_instobj_wr32_slow() local
65 spin_lock_irqsave(&imem->base.lock, flags); in nv50_instobj_wr32_slow()
66 if (unlikely(imem->addr != base)) { in nv50_instobj_wr32_slow()
67 nvkm_wr32(device, 0x001700, base >> 16); in nv50_instobj_wr32_slow()
68 imem->addr = base; in nv50_instobj_wr32_slow()
80 u64 base = (nvkm_memory_addr(iobj->ram) + offset) & 0xffffff00000ULL; nv50_instobj_rd32_slow() local
356 nv50_instobj_new(struct nvkm_instmem *base, u32 size, u32 align, bool zero, struct nvkm_memory **pmemory) nv50_instobj_new() argument
381 nv50_instmem_fini(struct nvkm_instmem *base) nv50_instmem_fini() argument
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/msm/disp/dpu1/catalog/
H A Ddpu_5_0_sm8150.h26 .base = 0x0, .len = 0x45c,
44 .base = 0x1000, .len = 0x1e0,
49 .base = 0x1200, .len = 0x1e0,
54 .base = 0x1400, .len = 0x1e0,
59 .base = 0x1600, .len = 0x1e0,
64 .base = 0x1800, .len = 0x1e0,
69 .base = 0x1a00, .len = 0x1e0,
78 .base = 0x4000, .len = 0x1f0,
86 .base = 0x6000, .len = 0x1f0,
94 .base
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/third_party/mesa3d/src/intel/vulkan/
H A Danv_measure.c35 struct intel_measure_batch base; member
122 measure->base.timestamps = measure->bo->map; in anv_measure_init()
144 if (measure->base.frame == 0) in anv_measure_start_snapshot()
145 measure->base.frame = device_frame; in anv_measure_start_snapshot()
149 // if (!measure->base.framebuffer && in anv_measure_start_snapshot()
152 // measure->base.framebuffer = framebuffer; in anv_measure_start_snapshot()
156 // framebuffer == measure->base.framebuffer || in anv_measure_start_snapshot()
159 unsigned index = measure->base.index++; in anv_measure_start_snapshot()
170 struct intel_measure_snapshot *snapshot = &(measure->base.snapshots[index]); in anv_measure_start_snapshot()
174 snapshot->event_count = measure->base in anv_measure_start_snapshot()
396 struct intel_measure_batch *base = &measure->base; _anv_measure_submit() local
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/third_party/mesa3d/src/gallium/drivers/lima/
H A Dlima_state.c53 util_copy_framebuffer_state(&fb->base, framebuffer); in lima_set_framebuffer_state()
76 so->base = *cso; in lima_create_depth_stencil_alpha_state()
106 so->base = *cso; in lima_create_rasterizer_state()
136 so->base = *cso; in lima_create_blend_state()
226 bool halfz = ctx->rasterizer && ctx->rasterizer->base.clip_halfz; in lima_set_viewport_states()
229 ctx->viewport.near = ctx->rasterizer && ctx->rasterizer->base.depth_clip_near ? near : 0.0f; in lima_set_viewport_states()
230 ctx->viewport.far = ctx->rasterizer && ctx->rasterizer->base.depth_clip_far ? far : 1.0f; in lima_set_viewport_states()
358 so->base = *cso; in lima_create_sampler_view()
361 so->base.texture = prsc; in lima_create_sampler_view()
362 so->base in lima_create_sampler_view()
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/kernel/linux/linux-5.10/drivers/ide/
H A Dtx4939ide.c84 static u16 tx4939ide_readw(void __iomem *base, u32 reg) in tx4939ide_readw() argument
86 return __raw_readw(base + tx4939ide_swizzlew(reg)); in tx4939ide_readw()
88 static u8 tx4939ide_readb(void __iomem *base, u32 reg) in tx4939ide_readb() argument
90 return __raw_readb(base + tx4939ide_swizzleb(reg)); in tx4939ide_readb()
92 static void tx4939ide_writel(u32 val, void __iomem *base, u32 reg) in tx4939ide_writel() argument
94 __raw_writel(val, base + tx4939ide_swizzlel(reg)); in tx4939ide_writel()
96 static void tx4939ide_writew(u16 val, void __iomem *base, u32 reg) in tx4939ide_writew() argument
98 __raw_writew(val, base + tx4939ide_swizzlew(reg)); in tx4939ide_writew()
100 static void tx4939ide_writeb(u8 val, void __iomem *base, u32 reg) in tx4939ide_writeb() argument
102 __raw_writeb(val, base in tx4939ide_writeb()
151 void __iomem *base = TX4939IDE_BASE(hwif); tx4939ide_check_error_ints() local
176 void __iomem *base; tx4939ide_clear_irq() local
193 void __iomem *base = TX4939IDE_BASE(hwif); tx4939ide_cable_detect() local
204 void __iomem *base = TX4939IDE_BASE(hwif); tx4939ide_dma_host_set() local
218 tx4939ide_clear_dma_status(void __iomem *base) tx4939ide_clear_dma_status() argument
290 void __iomem *base = TX4939IDE_BASE(hwif); tx4939ide_dma_setup() local
318 void __iomem *base = TX4939IDE_BASE(hwif); tx4939ide_dma_end() local
345 void __iomem *base = TX4939IDE_BASE(hwif); tx4939ide_dma_test_irq() local
384 void __iomem *base = TX4939IDE_BASE(hwif); tx4939ide_dma_sff_read_status() local
394 void __iomem *base = TX4939IDE_BASE(hwif); tx4939ide_init_hwif() local
423 void __iomem *base = TX4939IDE_BASE(hwif); tx4939ide_tf_load_fixup() local
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/kernel/linux/linux-6.6/drivers/clk/stm32/
H A Dclk-stm32-core.c24 void __iomem *base) in stm32_rcc_clock_init()
50 data->check_security(base, cfg_clock)) in stm32_rcc_clock_init()
54 hw = (*cfg_clock->func)(dev, data, base, &rlock, in stm32_rcc_clock_init()
71 void __iomem *base) in stm32_rcc_init()
83 err = stm32_rcc_reset_init(dev, match, base); in stm32_rcc_init()
90 err = stm32_rcc_clock_init(dev, match, base); in stm32_rcc_init()
99 static u8 stm32_mux_get_parent(void __iomem *base, in stm32_mux_get_parent() argument
107 val = readl(base + mux->offset) >> mux->shift; in stm32_mux_get_parent()
113 static int stm32_mux_set_parent(void __iomem *base, in stm32_mux_set_parent() argument
120 u32 reg = readl(base in stm32_mux_set_parent()
22 stm32_rcc_clock_init(struct device *dev, const struct of_device_id *match, void __iomem *base) stm32_rcc_clock_init() argument
70 stm32_rcc_init(struct device *dev, const struct of_device_id *match_data, void __iomem *base) stm32_rcc_init() argument
131 stm32_gate_endisable(void __iomem *base, struct clk_stm32_clock_data *data, u16 gate_id, int enable) stm32_gate_endisable() argument
157 stm32_gate_disable_unused(void __iomem *base, struct clk_stm32_clock_data *data, u16 gate_id) stm32_gate_disable_unused() argument
173 stm32_gate_is_enabled(void __iomem *base, struct clk_stm32_clock_data *data, u16 gate_id) stm32_gate_is_enabled() argument
205 stm32_divider_get_rate(void __iomem *base, struct clk_stm32_clock_data *data, u16 div_id, unsigned long parent_rate) stm32_divider_get_rate() argument
228 stm32_divider_set_rate(void __iomem *base, struct clk_stm32_clock_data *data, u16 div_id, unsigned long rate, unsigned long parent_rate) stm32_divider_set_rate() argument
624 clk_stm32_mux_register(struct device *dev, const struct stm32_rcc_match_data *data, void __iomem *base, spinlock_t *lock, const struct clock_config *cfg) clk_stm32_mux_register() argument
645 clk_stm32_gate_register(struct device *dev, const struct stm32_rcc_match_data *data, void __iomem *base, spinlock_t *lock, const struct clock_config *cfg) clk_stm32_gate_register() argument
666 clk_stm32_div_register(struct device *dev, const struct stm32_rcc_match_data *data, void __iomem *base, spinlock_t *lock, const struct clock_config *cfg) clk_stm32_div_register() argument
687 clk_stm32_composite_register(struct device *dev, const struct stm32_rcc_match_data *data, void __iomem *base, spinlock_t *lock, const struct clock_config *cfg) clk_stm32_composite_register() argument
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/
H A Ddcn316_clk_mgr.c67 container_of(clk_mgr, struct clk_mgr_dcn316, base)
202 if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) { in dcn316_update_clocks()
203 if (clk_mgr->base.clks.dppclk_khz > new_clocks->dppclk_khz) in dcn316_update_clocks()
478 struct clk_bw_params *bw_params = clk_mgr->base.bw_params; in dcn316_clk_mgr_helper_populate_bw_params()
576 clk_mgr->base.base.ctx = ctx; in dcn316_clk_mgr_construct()
577 clk_mgr->base.base.funcs = &dcn316_funcs; in dcn316_clk_mgr_construct()
579 clk_mgr->base.pp_smu = pp_smu; in dcn316_clk_mgr_construct()
581 clk_mgr->base in dcn316_clk_mgr_construct()
[all...]
/third_party/node/deps/zlib/google/
H A Dzip_reader.cc10 #include "base/check.h"
11 #include "base/files/file.h"
12 #include "base/files/file_util.h"
13 #include "base/functional/bind.h"
14 #include "base/i18n/icu_string_conversions.h"
15 #include "base/logging.h"
16 #include "base/numerics/safe_conversions.h"
17 #include "base/strings/strcat.h"
18 #include "base/strings/string_piece.h"
19 #include "base/string
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/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dce112/
H A Ddce112_resource.c505 return &tg110->base; in dce112_timing_generator_create()
521 return &enc110->base; in dce112_stream_encoder_create()
591 return &dce_mi->base; in dce112_mem_input_create()
613 return &transform->base; in dce112_transform_create()
646 return &enc110->base; in dce112_link_encoder_create()
663 return &panel_cntl->base; in dce112_panel_cntl_create()
678 return &ipp->base; in dce112_ipp_create()
693 return &opp->base; in dce112_opp_create()
713 return &aux_engine->base; in dce112_aux_engine_create()
764 clk_src->base in dce112_clock_source_create()
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dce112/
H A Ddce112_resource.c502 return &tg110->base; in dce112_timing_generator_create()
518 return &enc110->base; in dce112_stream_encoder_create()
588 return &dce_mi->base; in dce112_mem_input_create()
610 return &transform->base; in dce112_transform_create()
644 return &enc110->base; in dce112_link_encoder_create()
661 return &panel_cntl->base; in dce112_panel_cntl_create()
676 return &ipp->base; in dce112_ipp_create()
691 return &opp->base; in dce112_opp_create()
711 return &aux_engine->base; in dce112_aux_engine_create()
762 clk_src->base in dce112_clock_source_create()
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/msm/dsi/phy/
H A Ddsi_phy_14nm.c114 void __iomem *base = pll_14nm->phy->pll_base; in pll_14nm_poll_for_ready() local
119 val = dsi_phy_read(base + REG_DSI_14nm_PHY_PLL_RESET_SM_READY_STATUS); in pll_14nm_poll_for_ready()
133 val = dsi_phy_read(base + REG_DSI_14nm_PHY_PLL_RESET_SM_READY_STATUS); in pll_14nm_poll_for_ready()
286 void __iomem *base = pll->phy->pll_base; in pll_db_commit_ssc() local
291 dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_SSC_ADJ_PER1, data); in pll_db_commit_ssc()
294 dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_SSC_ADJ_PER2, data); in pll_db_commit_ssc()
298 dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_SSC_PER1, data); in pll_db_commit_ssc()
301 dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_SSC_PER2, data); in pll_db_commit_ssc()
305 dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_SSC_STEP_SIZE1, data); in pll_db_commit_ssc()
308 dsi_phy_write(base in pll_db_commit_ssc()
321 void __iomem *base = pll->phy->pll_base; pll_db_commit_common() local
385 void __iomem *base = pll->phy->pll_base; pll_db_commit_14nm() local
494 void __iomem *base = pll_14nm->phy->pll_base; dsi_pll_14nm_vco_recalc_rate() local
533 void __iomem *base = pll_14nm->phy->pll_base; dsi_pll_14nm_vco_prepare() local
607 void __iomem *base = pll_14nm->phy->base; dsi_pll_14nm_postdiv_recalc_rate() local
640 void __iomem *base = pll_14nm->phy->base; dsi_pll_14nm_postdiv_set_rate() local
742 void __iomem *base = phy->pll_base; dsi_14nm_set_usecase() local
910 void __iomem *base = phy->lane_base; dsi_14nm_dphy_set_timing() local
950 void __iomem *base = phy->base; dsi_14nm_phy_enable() local
[all...]
/kernel/linux/linux-5.10/drivers/crypto/ux500/cryp/
H A Dcryp.c29 * @device_data: Pointer to the device data struct for base address.
38 peripheralid2 = readl_relaxed(&device_data->base->periphId2); in cryp_check()
45 readl_relaxed(&device_data->base->periphId0)) in cryp_check()
47 readl_relaxed(&device_data->base->periphId1)) in cryp_check()
49 readl_relaxed(&device_data->base->periphId3)) in cryp_check()
51 readl_relaxed(&device_data->base->pcellId0)) in cryp_check()
53 readl_relaxed(&device_data->base->pcellId1)) in cryp_check()
55 readl_relaxed(&device_data->base->pcellId2)) in cryp_check()
57 readl_relaxed(&device_data->base->pcellId3))) { in cryp_check()
66 * @device_data: Pointer to the device data struct for base addres
[all...]
/kernel/linux/linux-5.10/drivers/watchdog/
H A Dimx7ulp_wdt.c51 void __iomem *base; member
55 static int imx7ulp_wdt_wait(void __iomem *base, u32 mask) in imx7ulp_wdt_wait() argument
57 u32 val = readl(base + WDOG_CS); in imx7ulp_wdt_wait()
59 if (!(val & mask) && readl_poll_timeout_atomic(base + WDOG_CS, val, in imx7ulp_wdt_wait()
71 u32 val = readl(wdt->base + WDOG_CS); in imx7ulp_wdt_enable()
75 writel(UNLOCK, wdt->base + WDOG_CNT); in imx7ulp_wdt_enable()
76 ret = imx7ulp_wdt_wait(wdt->base, WDOG_CS_ULK); in imx7ulp_wdt_enable()
80 writel(val | WDOG_CS_EN, wdt->base + WDOG_CS); in imx7ulp_wdt_enable()
82 writel(val & ~WDOG_CS_EN, wdt->base + WDOG_CS); in imx7ulp_wdt_enable()
83 imx7ulp_wdt_wait(wdt->base, WDOG_CS_RC in imx7ulp_wdt_enable()
91 imx7ulp_wdt_is_enabled(void __iomem *base) imx7ulp_wdt_is_enabled() argument
176 imx7ulp_wdt_init(void __iomem *base, unsigned int timeout) imx7ulp_wdt_init() argument
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