| /kernel/linux/linux-5.10/drivers/soc/bcm/brcmstb/pm/ |
| H A D | pm-mips.c | 80 #define AON_SAVE_SRAM(base, idx, val) \
81 __raw_writel(val, base + (idx << 2))
134 void __iomem *base = ctrl.aon_ctrl_base; in brcmstb_pm_handshake() local
138 tmp = __raw_readl(base + AON_CTRL_HOST_MISC_CMDS); in brcmstb_pm_handshake()
140 __raw_writel(tmp, base + AON_CTRL_HOST_MISC_CMDS); in brcmstb_pm_handshake()
141 (void)__raw_readl(base + AON_CTRL_HOST_MISC_CMDS); in brcmstb_pm_handshake()
143 __raw_writel(0, base + AON_CTRL_PM_INITIATE); in brcmstb_pm_handshake()
144 (void)__raw_readl(base + AON_CTRL_PM_INITIATE); in brcmstb_pm_handshake()
146 base + AON_CTRL_PM_INITIATE); in brcmstb_pm_handshake()
156 void __iomem *base in brcmstb_pm_s5() local
383 void __iomem *base; brcmstb_pm_init() local
[all...] |
| /kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/nvkm/engine/fifo/ |
| H A D | channv50.c | 46 nv50_fifo_chan_engine_fini(struct nvkm_fifo_chan *base, in nv50_fifo_chan_engine_fini() argument
49 struct nv50_fifo_chan *chan = nv50_fifo_chan(base); in nv50_fifo_chan_engine_fini()
51 struct nvkm_subdev *subdev = &fifo->base.engine.subdev; in nv50_fifo_chan_engine_fini()
75 nvkm_wr32(device, 0x0032fc, chan->base.inst->addr >> 12); in nv50_fifo_chan_engine_fini()
81 chan->base.chid, chan->base.object.client->name); in nv50_fifo_chan_engine_fini()
102 nv50_fifo_chan_engine_init(struct nvkm_fifo_chan *base, in nv50_fifo_chan_engine_init() argument
105 struct nv50_fifo_chan *chan = nv50_fifo_chan(base); in nv50_fifo_chan_engine_init()
129 nv50_fifo_chan_engine_dtor(struct nvkm_fifo_chan *base, in nv50_fifo_chan_engine_dtor() argument
132 struct nv50_fifo_chan *chan = nv50_fifo_chan(base); in nv50_fifo_chan_engine_dtor()
137 nv50_fifo_chan_engine_ctor(struct nvkm_fifo_chan *base, struct nvkm_engine *engine, struct nvkm_object *object) nv50_fifo_chan_engine_ctor() argument
151 nv50_fifo_chan_object_dtor(struct nvkm_fifo_chan *base, int cookie) nv50_fifo_chan_object_dtor() argument
158 nv50_fifo_chan_object_ctor(struct nvkm_fifo_chan *base, struct nvkm_object *object) nv50_fifo_chan_object_ctor() argument
179 nv50_fifo_chan_fini(struct nvkm_fifo_chan *base) nv50_fifo_chan_fini() argument
193 nv50_fifo_chan_init(struct nvkm_fifo_chan *base) nv50_fifo_chan_init() argument
206 nv50_fifo_chan_dtor(struct nvkm_fifo_chan *base) nv50_fifo_chan_dtor() argument
[all...] |
| /kernel/linux/linux-6.6/drivers/soc/bcm/brcmstb/pm/ |
| H A D | pm-mips.c | 80 #define AON_SAVE_SRAM(base, idx, val) \
81 __raw_writel(val, base + (idx << 2))
134 void __iomem *base = ctrl.aon_ctrl_base; in brcmstb_pm_handshake() local
138 tmp = __raw_readl(base + AON_CTRL_HOST_MISC_CMDS); in brcmstb_pm_handshake()
140 __raw_writel(tmp, base + AON_CTRL_HOST_MISC_CMDS); in brcmstb_pm_handshake()
141 (void)__raw_readl(base + AON_CTRL_HOST_MISC_CMDS); in brcmstb_pm_handshake()
143 __raw_writel(0, base + AON_CTRL_PM_INITIATE); in brcmstb_pm_handshake()
144 (void)__raw_readl(base + AON_CTRL_PM_INITIATE); in brcmstb_pm_handshake()
146 base + AON_CTRL_PM_INITIATE); in brcmstb_pm_handshake()
156 void __iomem *base in brcmstb_pm_s5() local
383 void __iomem *base; brcmstb_pm_init() local
[all...] |
| /kernel/linux/linux-6.6/drivers/phy/qualcomm/ |
| H A D | phy-qcom-pcie2.c | 41 void __iomem *base; member
75 val = readl(qphy->base + PCIE20_PARF_PHY_REFCLK_CTRL2); in qcom_pcie2_phy_power_on()
77 writel(val, qphy->base + PCIE20_PARF_PHY_REFCLK_CTRL2); in qcom_pcie2_phy_power_on()
82 val = readl(qphy->base + PCIE20_PARF_PHY_REFCLK_CTRL2); in qcom_pcie2_phy_power_on()
84 writel(val, qphy->base + PCIE20_PARF_PHY_REFCLK_CTRL2); in qcom_pcie2_phy_power_on()
87 val = readl(qphy->base + PCIE20_PARF_PHY_REFCLK_CTRL3); in qcom_pcie2_phy_power_on()
89 writel(val, qphy->base + PCIE20_PARF_PHY_REFCLK_CTRL3); in qcom_pcie2_phy_power_on()
94 val = readl(qphy->base + PCIE2_PHY_RESET_CTRL); in qcom_pcie2_phy_power_on()
96 writel(val, qphy->base + PCIE2_PHY_RESET_CTRL); in qcom_pcie2_phy_power_on()
99 val = readl(qphy->base in qcom_pcie2_phy_power_on()
[all...] |
| /kernel/linux/linux-6.6/net/sctp/ |
| H A D | endpointola.c | 39 * Initialize the base fields of the endpoint structure.
63 /* Initialize the base structure. */ in sctp_endpoint_init()
65 ep->base.type = SCTP_EP_TYPE_SOCKET; in sctp_endpoint_init()
68 refcount_set(&ep->base.refcnt, 1); in sctp_endpoint_init()
69 ep->base.dead = false; in sctp_endpoint_init()
72 sctp_inq_init(&ep->base.inqueue); in sctp_endpoint_init()
75 sctp_inq_set_th_handler(&ep->base.inqueue, sctp_endpoint_bh_rcv); in sctp_endpoint_init()
78 sctp_bind_addr_init(&ep->base.bind_addr, 0); in sctp_endpoint_init()
112 ep->base.sk = sk; in sctp_endpoint_init()
113 ep->base in sctp_endpoint_init()
[all...] |
| /third_party/mesa3d/src/gbm/backends/dri/ |
| H A D | gbm_dri.c | 101 struct gbm_dri_device *dri = gbm_dri_device(surf->base.gbm); in dri_get_buffers()
114 struct gbm_dri_device *dri = gbm_dri_device(surf->base.gbm); in dri_flush_front_buffer()
127 struct gbm_dri_device *dri = gbm_dri_device(surf->base.gbm); in dri_get_buffers_with_format()
158 struct gbm_dri_device *dri = gbm_dri_device(surf->base.gbm); in image_get_buffers()
179 *width = surf->base.v0.width; in swrast_get_drawable_info()
180 *height = surf->base.v0.height; in swrast_get_drawable_info()
195 struct gbm_dri_device *dri = gbm_dri_device(surf->base.gbm); in swrast_put_image2()
227 struct gbm_dri_device *dri = gbm_dri_device(surf->base.gbm); in swrast_get_image()
236 .base = { __DRI_USE_INVALIDATE, 1 }
240 .base
[all...] |
| /kernel/linux/linux-6.6/drivers/gpu/drm/i915/display/ |
| H A D | intel_pps.c | 101 dig_port->base.base.base.id, dig_port->base.base.name)) in vlv_power_sequencer_kick()
107 dig_port->base.base.base.id, dig_port->base.base in vlv_power_sequencer_kick()
[all...] |
| /kernel/linux/linux-6.6/drivers/memory/ |
| H A D | emif.c | 42 * @base: base address of memory-mapped IO registers.
61 void __iomem *base; member
178 void __iomem *base = emif->base; in get_emif_bus_width() local
180 width = (readl(base + EMIF_SDRAM_CONFIG) & NARROW_MODE_MASK) in get_emif_bus_width()
190 void __iomem *base = emif->base; in set_lpmode() local
226 temp = readl(base + EMIF_POWER_MANAGEMENT_CONTROL); in set_lpmode()
229 writel(temp, base in set_lpmode()
464 void __iomem *base; get_temperature_level() local
503 void __iomem *base = emif->base; setup_temperature_sensitive_regs() local
531 handle_temp_alert(void __iomem *base, struct emif_data *emif) handle_temp_alert() argument
593 void __iomem *base = emif->base; emif_interrupt_handler() local
658 void __iomem *base = emif->base; clear_all_interrupts() local
669 void __iomem *base = emif->base; disable_and_clear_all_interrupts() local
685 void __iomem *base = emif->base; setup_interrupts() local
716 void __iomem *base = emif->base; emif_onetime_settings() local
[all...] |
| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dcn201/ |
| H A D | dcn201_resource.c | 637 return &dpp->base; in dcn201_dpp_create()
655 return &ipp->base; in dcn201_ipp_create()
671 return &opp->base; in dcn201_opp_create()
690 return &aux_engine->base; in dcn201_aux_engine_create()
736 return &mpc201->base; in dcn201_mpc_create()
752 return &hubbub->base; in dcn201_hubbub_create()
765 tgn10->base.inst = instance; in dcn201_timing_generator_create()
766 tgn10->base.ctx = ctx; in dcn201_timing_generator_create()
774 return &tgn10->base; in dcn201_timing_generator_create()
809 return &enc10->base; in dcn201_link_encoder_create()
[all...] |
| /kernel/linux/linux-5.10/crypto/ |
| H A D | simd.c | 54 struct crypto_skcipher *child = &ctx->cryptd_tfm->base; in simd_skcipher_setkey()
74 child = &ctx->cryptd_tfm->base; in simd_skcipher_encrypt()
95 child = &ctx->cryptd_tfm->base; in simd_skcipher_decrypt()
131 reqsize = max(reqsize, crypto_skcipher_reqsize(&cryptd_tfm->base)); in simd_skcipher_init()
166 if (snprintf(alg->base.cra_name, CRYPTO_MAX_ALG_NAME, "%s", algname) >= in simd_skcipher_create_compat()
170 if (snprintf(alg->base.cra_driver_name, CRYPTO_MAX_ALG_NAME, "%s", in simd_skcipher_create_compat()
174 alg->base.cra_flags = CRYPTO_ALG_ASYNC | in simd_skcipher_create_compat()
175 (ialg->base.cra_flags & CRYPTO_ALG_INHERITED_FLAGS); in simd_skcipher_create_compat()
176 alg->base.cra_priority = ialg->base in simd_skcipher_create_compat()
[all...] |
| /kernel/linux/linux-5.10/drivers/mtd/chips/ |
| H A D | cfi_probe.c | 27 static int cfi_probe_chip(struct map_info *map, __u32 base,
38 #define xip_allowed(base, map) \
40 (void) map_read(map, base); \
45 #define xip_enable(base, map, cfi) \
47 cfi_qry_mode_off(base, map, cfi); \
48 xip_allowed(base, map); \
51 #define xip_disable_qry(base, map, cfi) \
54 cfi_qry_mode_on(base, map, cfi); \
60 #define xip_allowed(base, map) do { } while (0)
61 #define xip_enable(base, ma
95 cfi_probe_chip(struct map_info *map, __u32 base, unsigned long *chip_map, struct cfi_private *cfi) cfi_probe_chip() argument
198 __u32 base = 0; cfi_chip_setup() local
[all...] |
| /kernel/linux/linux-6.6/drivers/mtd/chips/ |
| H A D | cfi_probe.c | 28 static int cfi_probe_chip(struct map_info *map, __u32 base,
39 #define xip_allowed(base, map) \
41 (void) map_read(map, base); \
46 #define xip_enable(base, map, cfi) \
48 cfi_qry_mode_off(base, map, cfi); \
49 xip_allowed(base, map); \
52 #define xip_disable_qry(base, map, cfi) \
55 cfi_qry_mode_on(base, map, cfi); \
61 #define xip_allowed(base, map) do { } while (0)
62 #define xip_enable(base, ma
96 cfi_probe_chip(struct map_info *map, __u32 base, unsigned long *chip_map, struct cfi_private *cfi) cfi_probe_chip() argument
199 __u32 base = 0; cfi_chip_setup() local
[all...] |
| /kernel/linux/linux-6.6/crypto/ |
| H A D | simd.c | 54 struct crypto_skcipher *child = &ctx->cryptd_tfm->base; in simd_skcipher_setkey()
74 child = &ctx->cryptd_tfm->base; in simd_skcipher_encrypt()
95 child = &ctx->cryptd_tfm->base; in simd_skcipher_decrypt()
131 reqsize = max(reqsize, crypto_skcipher_reqsize(&cryptd_tfm->base)); in simd_skcipher_init()
166 if (snprintf(alg->base.cra_name, CRYPTO_MAX_ALG_NAME, "%s", algname) >= in simd_skcipher_create_compat()
170 if (snprintf(alg->base.cra_driver_name, CRYPTO_MAX_ALG_NAME, "%s", in simd_skcipher_create_compat()
174 alg->base.cra_flags = CRYPTO_ALG_ASYNC | in simd_skcipher_create_compat()
175 (ialg->base.cra_flags & CRYPTO_ALG_INHERITED_FLAGS); in simd_skcipher_create_compat()
176 alg->base.cra_priority = ialg->base in simd_skcipher_create_compat()
[all...] |
| /kernel/linux/linux-6.6/drivers/i2c/busses/ |
| H A D | i2c-gxp.c | 78 void __iomem *base; member
110 writew(value, drvdata->base + GXP_I2CMCMD); in gxp_i2c_start()
163 writeb(slave->addr << 1, drvdata->base + GXP_I2COWNADR); in gxp_i2c_reg_slave()
165 SLAVE_EVT_STALL, drvdata->base + GXP_I2CSCMD); in gxp_i2c_reg_slave()
176 writeb(0x00, drvdata->base + GXP_I2COWNADR); in gxp_i2c_unreg_slave()
178 SLAVE_EVT_MASK, drvdata->base + GXP_I2CSCMD); in gxp_i2c_unreg_slave()
198 writeb(MASTER_EVT_CLR | STOP_CMD, drvdata->base + GXP_I2CMCMD); in gxp_i2c_stop()
222 writew(value, drvdata->base + GXP_I2CMCMD); in gxp_i2c_restart()
229 value = readb(drvdata->base + GXP_I2CSTAT); in gxp_i2c_chk_addr_ack()
251 drvdata->base in gxp_i2c_chk_addr_ack()
[all...] |
| /kernel/linux/linux-5.10/drivers/phy/marvell/ |
| H A D | phy-mvebu-cp110-comphy.c | 19 /* Relative to priv->base */
254 void __iomem *base; member
343 val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG0(lane->id)); in mvebu_comphy_ethernet_init_reset()
380 writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG0(lane->id)); in mvebu_comphy_ethernet_init_reset()
405 val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id)); in mvebu_comphy_ethernet_init_reset()
409 writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id)); in mvebu_comphy_ethernet_init_reset()
412 val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id)); in mvebu_comphy_ethernet_init_reset()
415 writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id)); in mvebu_comphy_ethernet_init_reset()
426 val = readl(priv->base + MVEBU_COMPHY_MISC_CTRL0(lane->id)); in mvebu_comphy_ethernet_init_reset()
430 writel(val, priv->base in mvebu_comphy_ethernet_init_reset()
[all...] |
| /kernel/linux/linux-5.10/drivers/pcmcia/ |
| H A D | rsrc_nonstatic.c | 49 u_long base, num; member
73 claim_region(struct pcmcia_socket *s, resource_size_t base, in claim_region() argument
79 res = pcmcia_make_resource(base, size, type | IORESOURCE_BUSY, name); in claim_region()
108 static int add_interval(struct resource_map *map, u_long base, u_long num) in add_interval() argument
113 if ((p != map) && (p->base+p->num >= base)) { in add_interval()
114 p->num = max(num + base - p->base, p->num); in add_interval()
117 if ((p->next == map) || (p->next->base > base in add_interval()
132 sub_interval(struct resource_map *map, u_long base, u_long num) sub_interval() argument
182 do_io_probe(struct pcmcia_socket *s, unsigned int base, unsigned int num) do_io_probe() argument
344 do_validate_mem(struct pcmcia_socket *s, unsigned long base, unsigned long size, int validate (struct pcmcia_socket *s, struct resource *res, unsigned int *value)) do_validate_mem() argument
400 do_mem_probe(struct pcmcia_socket *s, u_long base, u_long num, int validate (struct pcmcia_socket *s, struct resource *res, unsigned int *value), int fallback (struct pcmcia_socket *s, struct resource *res, unsigned int *value)) do_mem_probe() argument
682 __nonstatic_find_io_region(struct pcmcia_socket *s, unsigned long base, int num, unsigned long align) __nonstatic_find_io_region() argument
716 nonstatic_find_io(struct pcmcia_socket *s, unsigned int attr, unsigned int *base, unsigned int num, unsigned int align, struct resource **parent) nonstatic_find_io() argument
805 nonstatic_find_mem_region(u_long base, u_long num, u_long align, int low, struct pcmcia_socket *s) nonstatic_find_mem_region() argument
[all...] |
| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dce/ |
| H A D | dce_link_encoder.c | 57 enc110->base.ctx
59 enc110->base.ctx->logger
127 struct dc_bios *bp = enc110->base.ctx->dc_bios; in link_transmitter_control()
299 struct dc_context *ctx = enc110->base.ctx; in setup_panel_mode()
429 enc110->base.funcs->setup(&enc110->base, SIGNAL_TYPE_DISPLAY_PORT); in set_dp_phy_pattern_hbr2_compliance_cp2520_2()
482 enc110->base.funcs->setup(&enc110->base, SIGNAL_TYPE_DISPLAY_PORT); in dce60_set_dp_phy_pattern_hbr2_compliance_cp2520_2()
627 struct dc_context *ctx = enc110->base.ctx; in aux_initialize()
628 enum hpd_source_id hpd_source = enc110->base in aux_initialize()
[all...] |
| /kernel/linux/linux-6.6/drivers/pcmcia/ |
| H A D | rsrc_nonstatic.c | 49 u_long base, num; member
73 claim_region(struct pcmcia_socket *s, resource_size_t base, in claim_region() argument
79 res = pcmcia_make_resource(base, size, type | IORESOURCE_BUSY, name); in claim_region()
108 static int add_interval(struct resource_map *map, u_long base, u_long num) in add_interval() argument
113 if ((p != map) && (p->base+p->num >= base)) { in add_interval()
114 p->num = max(num + base - p->base, p->num); in add_interval()
117 if ((p->next == map) || (p->next->base > base in add_interval()
132 sub_interval(struct resource_map *map, u_long base, u_long num) sub_interval() argument
182 do_io_probe(struct pcmcia_socket *s, unsigned int base, unsigned int num) do_io_probe() argument
344 do_validate_mem(struct pcmcia_socket *s, unsigned long base, unsigned long size, int (*validate)(struct pcmcia_socket *s, struct resource *res, unsigned int *value)) do_validate_mem() argument
400 do_mem_probe(struct pcmcia_socket *s, u_long base, u_long num, int (*validate)(struct pcmcia_socket *s, struct resource *res, unsigned int *value), int (*fallback)(struct pcmcia_socket *s, struct resource *res, unsigned int *value)) do_mem_probe() argument
682 __nonstatic_find_io_region(struct pcmcia_socket *s, unsigned long base, int num, unsigned long align) __nonstatic_find_io_region() argument
716 nonstatic_find_io(struct pcmcia_socket *s, unsigned int attr, unsigned int *base, unsigned int num, unsigned int align, struct resource **parent) nonstatic_find_io() argument
805 nonstatic_find_mem_region(u_long base, u_long num, u_long align, int low, struct pcmcia_socket *s) nonstatic_find_mem_region() argument
[all...] |
| /kernel/linux/linux-6.6/drivers/phy/marvell/ |
| H A D | phy-mvebu-cp110-comphy.c | 20 /* Relative to priv->base */
259 void __iomem *base; member
348 val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG0(lane->id)); in mvebu_comphy_ethernet_init_reset()
385 writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG0(lane->id)); in mvebu_comphy_ethernet_init_reset()
410 val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id)); in mvebu_comphy_ethernet_init_reset()
414 writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id)); in mvebu_comphy_ethernet_init_reset()
417 val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id)); in mvebu_comphy_ethernet_init_reset()
420 writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id)); in mvebu_comphy_ethernet_init_reset()
431 val = readl(priv->base + MVEBU_COMPHY_MISC_CTRL0(lane->id)); in mvebu_comphy_ethernet_init_reset()
435 writel(val, priv->base in mvebu_comphy_ethernet_init_reset()
[all...] |
| /kernel/linux/linux-5.10/drivers/gpio/ |
| H A D | gpio-ftgpio010.c | 45 * @base: remapped I/O-memory base
52 void __iomem *base; member
61 writel(BIT(irqd_to_hwirq(d)), g->base + GPIO_INT_CLR); in ftgpio_gpio_ack_irq()
70 val = readl(g->base + GPIO_INT_EN); in ftgpio_gpio_mask_irq()
72 writel(val, g->base + GPIO_INT_EN); in ftgpio_gpio_mask_irq()
81 val = readl(g->base + GPIO_INT_EN); in ftgpio_gpio_unmask_irq()
83 writel(val, g->base + GPIO_INT_EN); in ftgpio_gpio_unmask_irq()
93 reg_type = readl(g->base + GPIO_INT_TYPE); in ftgpio_gpio_set_irq_type()
94 reg_level = readl(g->base in ftgpio_gpio_set_irq_type()
[all...] |
| /kernel/linux/linux-5.10/drivers/gpu/drm/omapdrm/dss/ |
| H A D | hdmi_wp.c | 22 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, hdmi_read_reg(wp->base, r)) in hdmi_wp_dump()
46 return hdmi_read_reg(wp->base, HDMI_WP_IRQSTATUS); in hdmi_wp_get_irqstatus()
51 hdmi_write_reg(wp->base, HDMI_WP_IRQSTATUS, irqstatus); in hdmi_wp_set_irqstatus()
53 hdmi_read_reg(wp->base, HDMI_WP_IRQSTATUS); in hdmi_wp_set_irqstatus()
58 hdmi_write_reg(wp->base, HDMI_WP_IRQENABLE_SET, mask); in hdmi_wp_set_irqenable()
63 hdmi_write_reg(wp->base, HDMI_WP_IRQENABLE_CLR, mask); in hdmi_wp_clear_irqenable()
70 if (REG_GET(wp->base, HDMI_WP_PWR_CTRL, 5, 4) == val) in hdmi_wp_set_phy_pwr()
74 REG_FLD_MOD(wp->base, HDMI_WP_PWR_CTRL, val, 7, 6); in hdmi_wp_set_phy_pwr()
77 if (hdmi_wait_for_bit_change(wp->base, HDMI_WP_PWR_CTRL, 5, 4, val) in hdmi_wp_set_phy_pwr()
90 REG_FLD_MOD(wp->base, HDMI_WP_PWR_CTR in hdmi_wp_set_pll_pwr()
[all...] |
| /kernel/linux/linux-5.10/drivers/phy/tegra/ |
| H A D | xusb.h | 53 struct tegra_xusb_lane base; member
59 return container_of(lane, struct tegra_xusb_usb3_lane, base); in to_usb3_lane()
63 struct tegra_xusb_lane base; member
72 return container_of(lane, struct tegra_xusb_usb2_lane, base); in to_usb2_lane()
76 struct tegra_xusb_lane base; member
82 return container_of(lane, struct tegra_xusb_ulpi_lane, base); in to_ulpi_lane()
86 struct tegra_xusb_lane base; member
101 return container_of(lane, struct tegra_xusb_hsic_lane, base); in to_hsic_lane()
105 struct tegra_xusb_lane base; member
111 return container_of(lane, struct tegra_xusb_pcie_lane, base); in to_pcie_lane()
115 struct tegra_xusb_lane base; global() member
178 struct tegra_xusb_pad base; global() member
191 struct tegra_xusb_pad base; global() member
205 struct tegra_xusb_pad base; global() member
215 struct tegra_xusb_pad base; global() member
228 struct tegra_xusb_pad base; global() member
243 struct tegra_xusb_pad base; global() member
299 struct tegra_xusb_port base; global() member
320 struct tegra_xusb_port base; global() member
335 struct tegra_xusb_port base; global() member
347 struct tegra_xusb_port base; global() member
[all...] |
| /kernel/linux/linux-5.10/drivers/video/fbdev/omap2/omapfb/dss/ |
| H A D | hdmi_wp.c | 23 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, hdmi_read_reg(wp->base, r)) in hdmi_wp_dump()
47 return hdmi_read_reg(wp->base, HDMI_WP_IRQSTATUS); in hdmi_wp_get_irqstatus()
52 hdmi_write_reg(wp->base, HDMI_WP_IRQSTATUS, irqstatus); in hdmi_wp_set_irqstatus()
54 hdmi_read_reg(wp->base, HDMI_WP_IRQSTATUS); in hdmi_wp_set_irqstatus()
59 hdmi_write_reg(wp->base, HDMI_WP_IRQENABLE_SET, mask); in hdmi_wp_set_irqenable()
64 hdmi_write_reg(wp->base, HDMI_WP_IRQENABLE_CLR, mask); in hdmi_wp_clear_irqenable()
71 if (REG_GET(wp->base, HDMI_WP_PWR_CTRL, 5, 4) == val) in hdmi_wp_set_phy_pwr()
75 REG_FLD_MOD(wp->base, HDMI_WP_PWR_CTRL, val, 7, 6); in hdmi_wp_set_phy_pwr()
78 if (hdmi_wait_for_bit_change(wp->base, HDMI_WP_PWR_CTRL, 5, 4, val) in hdmi_wp_set_phy_pwr()
91 REG_FLD_MOD(wp->base, HDMI_WP_PWR_CTR in hdmi_wp_set_pll_pwr()
[all...] |
| /kernel/linux/linux-6.6/drivers/rtc/ |
| H A D | rtc-mpfs.c | 58 void __iomem *base; member
65 ctrl = readl(rtcdev->base + CONTROL_REG); in mpfs_rtc_start()
68 writel(ctrl, rtcdev->base + CONTROL_REG); in mpfs_rtc_start()
73 u32 val = readl(rtcdev->base + CONTROL_REG); in mpfs_rtc_clear_irq()
77 writel(val, rtcdev->base + CONTROL_REG); in mpfs_rtc_clear_irq()
83 (void)readl(rtcdev->base + CONTROL_REG); in mpfs_rtc_clear_irq()
91 time = readl(rtcdev->base + DATETIME_LOWER_REG); in mpfs_rtc_readtime()
92 time |= ((u64)readl(rtcdev->base + DATETIME_UPPER_REG) & DATETIME_UPPER_MASK) << 32; in mpfs_rtc_readtime()
107 writel((u32)time, rtcdev->base + DATETIME_LOWER_REG); in mpfs_rtc_settime()
108 writel((u32)(time >> 32) & DATETIME_UPPER_MASK, rtcdev->base in mpfs_rtc_settime()
[all...] |
| /kernel/linux/linux-6.6/drivers/video/fbdev/omap2/omapfb/dss/ |
| H A D | hdmi_wp.c | 23 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, hdmi_read_reg(wp->base, r)) in hdmi_wp_dump()
47 return hdmi_read_reg(wp->base, HDMI_WP_IRQSTATUS); in hdmi_wp_get_irqstatus()
52 hdmi_write_reg(wp->base, HDMI_WP_IRQSTATUS, irqstatus); in hdmi_wp_set_irqstatus()
54 hdmi_read_reg(wp->base, HDMI_WP_IRQSTATUS); in hdmi_wp_set_irqstatus()
59 hdmi_write_reg(wp->base, HDMI_WP_IRQENABLE_SET, mask); in hdmi_wp_set_irqenable()
64 hdmi_write_reg(wp->base, HDMI_WP_IRQENABLE_CLR, mask); in hdmi_wp_clear_irqenable()
71 if (REG_GET(wp->base, HDMI_WP_PWR_CTRL, 5, 4) == val) in hdmi_wp_set_phy_pwr()
75 REG_FLD_MOD(wp->base, HDMI_WP_PWR_CTRL, val, 7, 6); in hdmi_wp_set_phy_pwr()
78 if (hdmi_wait_for_bit_change(wp->base, HDMI_WP_PWR_CTRL, 5, 4, val) in hdmi_wp_set_phy_pwr()
91 REG_FLD_MOD(wp->base, HDMI_WP_PWR_CTR in hdmi_wp_set_pll_pwr()
[all...] |