Lines Matching refs:base
80 #define AON_SAVE_SRAM(base, idx, val) \
81 __raw_writel(val, base + (idx << 2))
134 void __iomem *base = ctrl.aon_ctrl_base;
138 tmp = __raw_readl(base + AON_CTRL_HOST_MISC_CMDS);
140 __raw_writel(tmp, base + AON_CTRL_HOST_MISC_CMDS);
141 (void)__raw_readl(base + AON_CTRL_HOST_MISC_CMDS);
143 __raw_writel(0, base + AON_CTRL_PM_INITIATE);
144 (void)__raw_readl(base + AON_CTRL_PM_INITIATE);
146 base + AON_CTRL_PM_INITIATE);
156 void __iomem *base = ctrl.aon_ctrl_base;
164 __raw_writel(0x10, base + AON_CTRL_PM_CPU_WAIT_COUNT);
165 (void)__raw_readl(base + AON_CTRL_PM_CPU_WAIT_COUNT);
168 __raw_writel(PM_COLD_CONFIG, base + AON_CTRL_PM_CTRL);
169 (void)__raw_readl(base + AON_CTRL_PM_CTRL);
171 __raw_writel((PM_COLD_CONFIG | PM_PWR_DOWN), base +
173 (void)__raw_readl(base + AON_CTRL_PM_CTRL);
257 * 0: AON_CTRl base register
258 * 1: DDR_PHY base register
259 * 2: TIMERS base resgister
383 void __iomem *base;
387 base = brcmstb_ioremap_match(aon_ctrl_dt_ids, 0, NULL);
388 if (IS_ERR(base)) {
392 ctrl.aon_ctrl_base = base;
395 base = brcmstb_ioremap_match(aon_ctrl_dt_ids, 1, NULL);
396 if (IS_ERR(base)) {
400 ctrl.aon_sram_base = base;
411 base = brcmstb_ioremap_node(dn, 0);
412 if (IS_ERR(base)) {
417 ctrl.memcs[i].ddr_phy_base = base;
422 base = brcmstb_ioremap_match(arb_dt_ids, 0, NULL);
423 if (IS_ERR(base)) {
427 ctrl.memcs[0].arb_base = base;
430 base = brcmstb_ioremap_match(timers_ids, 0, NULL);
431 if (IS_ERR(base)) {
435 ctrl.timers_base = base;
454 return PTR_ERR(base);