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/third_party/libinput/src/
H A Dlibinput.c164 struct libinput_event base; member
168 struct libinput_event base; member
176 struct libinput_event base; member
191 struct libinput_event base; member
199 struct libinput_event base; member
210 struct libinput_event base; member
223 struct libinput_event base; member
248 struct libinput_event base; member
479 require_event_type(libinput_event_get_context(&event->base), in libinput_event_keyboard_get_time()
480 event->base in libinput_event_keyboard_get_time()
[all...]
/kernel/linux/linux-5.10/drivers/clk/samsung/
H A Dclk-cpu.c137 static void exynos_set_safe_div(void __iomem *base, unsigned long div, in exynos_set_safe_div() argument
142 div0 = readl(base + E4210_DIV_CPU0); in exynos_set_safe_div()
144 writel(div0, base + E4210_DIV_CPU0); in exynos_set_safe_div()
145 wait_until_divider_stable(base + E4210_DIV_STAT_CPU0, mask); in exynos_set_safe_div()
150 struct exynos_cpuclk *cpuclk, void __iomem *base) in exynos_cpuclk_pre_rate_change()
175 if (readl(base + E4210_SRC_CPU) & E4210_MUX_HPM_MASK) in exynos_cpuclk_pre_rate_change()
176 div1 = readl(base + E4210_DIV_CPU1) & in exynos_cpuclk_pre_rate_change()
202 exynos_set_safe_div(base, alt_div, alt_div_mask); in exynos_cpuclk_pre_rate_change()
207 mux_reg = readl(base + E4210_SRC_CPU); in exynos_cpuclk_pre_rate_change()
208 writel(mux_reg | (1 << 16), base in exynos_cpuclk_pre_rate_change()
149 exynos_cpuclk_pre_rate_change(struct clk_notifier_data *ndata, struct exynos_cpuclk *cpuclk, void __iomem *base) exynos_cpuclk_pre_rate_change() argument
226 exynos_cpuclk_post_rate_change(struct clk_notifier_data *ndata, struct exynos_cpuclk *cpuclk, void __iomem *base) exynos_cpuclk_post_rate_change() argument
265 exynos5433_set_safe_div(void __iomem *base, unsigned long div, unsigned long mask) exynos5433_set_safe_div() argument
277 exynos5433_cpuclk_pre_rate_change(struct clk_notifier_data *ndata, struct exynos_cpuclk *cpuclk, void __iomem *base) exynos5433_cpuclk_pre_rate_change() argument
337 exynos5433_cpuclk_post_rate_change(struct clk_notifier_data *ndata, struct exynos_cpuclk *cpuclk, void __iomem *base) exynos5433_cpuclk_post_rate_change() argument
365 void __iomem *base; exynos_cpuclk_notifier_cb() local
388 void __iomem *base; exynos5433_cpuclk_notifier_cb() local
[all...]
/kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/nvkm/subdev/clk/
H A Dgk20a.c67 struct nvkm_device *device = clk->base.subdev.device; in gk20a_pllg_read_mnp()
79 struct nvkm_device *device = clk->base.subdev.device; in gk20a_pllg_write_mnp()
104 struct nvkm_subdev *subdev = &clk->base.subdev; in gk20a_pllg_calc_mnp()
213 struct nvkm_subdev *subdev = &clk->base.subdev; in gk20a_pllg_slide()
258 struct nvkm_device *device = clk->base.subdev.device; in gk20a_pllg_enable()
286 struct nvkm_device *device = clk->base.subdev.device; in gk20a_pllg_disable()
298 struct nvkm_subdev *subdev = &clk->base.subdev; in gk20a_pllg_program_mnp()
368 .base = {
374 .base = {
380 .base
460 gk20a_clk_read(struct nvkm_clk *base, enum nv_clk_src src) gk20a_clk_read() argument
480 gk20a_clk_calc(struct nvkm_clk *base, struct nvkm_cstate *cstate) gk20a_clk_calc() argument
489 gk20a_clk_prog(struct nvkm_clk *base) gk20a_clk_prog() argument
502 gk20a_clk_tidy(struct nvkm_clk *base) gk20a_clk_tidy() argument
543 gk20a_clk_fini(struct nvkm_clk *base) gk20a_clk_fini() argument
565 gk20a_clk_init(struct nvkm_clk *base) gk20a_clk_init() argument
[all...]
/kernel/linux/linux-6.6/drivers/clk/samsung/
H A Dclk-cpu.c137 static void exynos_set_safe_div(void __iomem *base, unsigned long div, in exynos_set_safe_div() argument
142 div0 = readl(base + E4210_DIV_CPU0); in exynos_set_safe_div()
144 writel(div0, base + E4210_DIV_CPU0); in exynos_set_safe_div()
145 wait_until_divider_stable(base + E4210_DIV_STAT_CPU0, mask); in exynos_set_safe_div()
150 struct exynos_cpuclk *cpuclk, void __iomem *base) in exynos_cpuclk_pre_rate_change()
175 if (readl(base + E4210_SRC_CPU) & E4210_MUX_HPM_MASK) in exynos_cpuclk_pre_rate_change()
176 div1 = readl(base + E4210_DIV_CPU1) & in exynos_cpuclk_pre_rate_change()
202 exynos_set_safe_div(base, alt_div, alt_div_mask); in exynos_cpuclk_pre_rate_change()
207 mux_reg = readl(base + E4210_SRC_CPU); in exynos_cpuclk_pre_rate_change()
208 writel(mux_reg | (1 << 16), base in exynos_cpuclk_pre_rate_change()
149 exynos_cpuclk_pre_rate_change(struct clk_notifier_data *ndata, struct exynos_cpuclk *cpuclk, void __iomem *base) exynos_cpuclk_pre_rate_change() argument
226 exynos_cpuclk_post_rate_change(struct clk_notifier_data *ndata, struct exynos_cpuclk *cpuclk, void __iomem *base) exynos_cpuclk_post_rate_change() argument
265 exynos5433_set_safe_div(void __iomem *base, unsigned long div, unsigned long mask) exynos5433_set_safe_div() argument
277 exynos5433_cpuclk_pre_rate_change(struct clk_notifier_data *ndata, struct exynos_cpuclk *cpuclk, void __iomem *base) exynos5433_cpuclk_pre_rate_change() argument
337 exynos5433_cpuclk_post_rate_change(struct clk_notifier_data *ndata, struct exynos_cpuclk *cpuclk, void __iomem *base) exynos5433_cpuclk_post_rate_change() argument
365 void __iomem *base; exynos_cpuclk_notifier_cb() local
388 void __iomem *base; exynos5433_cpuclk_notifier_cb() local
[all...]
/kernel/linux/linux-6.6/drivers/perf/hisilicon/
H A Dhisi_uncore_l3c_pmu.c72 val = readl(l3c_pmu->base + L3C_TRACETAG_CTRL); in hisi_l3c_pmu_config_req_tracetag()
75 writel(val, l3c_pmu->base + L3C_TRACETAG_CTRL); in hisi_l3c_pmu_config_req_tracetag()
78 val = readl(l3c_pmu->base + L3C_PERF_CTRL); in hisi_l3c_pmu_config_req_tracetag()
80 writel(val, l3c_pmu->base + L3C_PERF_CTRL); in hisi_l3c_pmu_config_req_tracetag()
93 val = readl(l3c_pmu->base + L3C_TRACETAG_CTRL); in hisi_l3c_pmu_clear_req_tracetag()
96 writel(val, l3c_pmu->base + L3C_TRACETAG_CTRL); in hisi_l3c_pmu_clear_req_tracetag()
99 val = readl(l3c_pmu->base + L3C_PERF_CTRL); in hisi_l3c_pmu_clear_req_tracetag()
101 writel(val, l3c_pmu->base + L3C_PERF_CTRL); in hisi_l3c_pmu_clear_req_tracetag()
123 val = readl(l3c_pmu->base + reg); in hisi_l3c_pmu_write_ds()
126 writel(val, l3c_pmu->base in hisi_l3c_pmu_write_ds()
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/msm/disp/dpu1/catalog/
H A Ddpu_5_1_sc8180x.h26 .base = 0x0, .len = 0x45c,
43 .base = 0x1000, .len = 0x1e0,
48 .base = 0x1200, .len = 0x1e0,
53 .base = 0x1400, .len = 0x1e0,
58 .base = 0x1600, .len = 0x1e0,
63 .base = 0x1800, .len = 0x1e0,
68 .base = 0x1a00, .len = 0x1e0,
77 .base = 0x4000, .len = 0x1f0,
85 .base = 0x6000, .len = 0x1f0,
93 .base
[all...]
H A Ddpu_8_1_sm8450.h24 .base = 0x0, .len = 0x494,
44 .base = 0x15000, .len = 0x204,
49 .base = 0x16000, .len = 0x204,
54 .base = 0x17000, .len = 0x204,
59 .base = 0x18000, .len = 0x204,
64 .base = 0x19000, .len = 0x204,
69 .base = 0x1a000, .len = 0x204,
78 .base = 0x4000, .len = 0x32c,
86 .base = 0x6000, .len = 0x32c,
94 .base
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/nouveau/nvkm/subdev/clk/
H A Dgk20a.c67 struct nvkm_device *device = clk->base.subdev.device; in gk20a_pllg_read_mnp()
79 struct nvkm_device *device = clk->base.subdev.device; in gk20a_pllg_write_mnp()
104 struct nvkm_subdev *subdev = &clk->base.subdev; in gk20a_pllg_calc_mnp()
213 struct nvkm_subdev *subdev = &clk->base.subdev; in gk20a_pllg_slide()
258 struct nvkm_device *device = clk->base.subdev.device; in gk20a_pllg_enable()
286 struct nvkm_device *device = clk->base.subdev.device; in gk20a_pllg_disable()
298 struct nvkm_subdev *subdev = &clk->base.subdev; in gk20a_pllg_program_mnp()
368 .base = {
374 .base = {
380 .base
460 gk20a_clk_read(struct nvkm_clk *base, enum nv_clk_src src) gk20a_clk_read() argument
480 gk20a_clk_calc(struct nvkm_clk *base, struct nvkm_cstate *cstate) gk20a_clk_calc() argument
489 gk20a_clk_prog(struct nvkm_clk *base) gk20a_clk_prog() argument
502 gk20a_clk_tidy(struct nvkm_clk *base) gk20a_clk_tidy() argument
543 gk20a_clk_fini(struct nvkm_clk *base) gk20a_clk_fini() argument
565 gk20a_clk_init(struct nvkm_clk *base) gk20a_clk_init() argument
[all...]
/kernel/linux/linux-5.10/drivers/clocksource/
H A Dtimer-efm32.c44 void __iomem *base; member
53 writel_relaxed(TIMERn_CMD_STOP, ddata->base + TIMERn_CMD); in efm32_clock_event_shutdown()
62 writel_relaxed(TIMERn_CMD_STOP, ddata->base + TIMERn_CMD); in efm32_clock_event_set_oneshot()
67 ddata->base + TIMERn_CTRL); in efm32_clock_event_set_oneshot()
76 writel_relaxed(TIMERn_CMD_STOP, ddata->base + TIMERn_CMD); in efm32_clock_event_set_periodic()
77 writel_relaxed(ddata->periodic_top, ddata->base + TIMERn_TOP); in efm32_clock_event_set_periodic()
81 ddata->base + TIMERn_CTRL); in efm32_clock_event_set_periodic()
82 writel_relaxed(TIMERn_CMD_START, ddata->base + TIMERn_CMD); in efm32_clock_event_set_periodic()
92 writel_relaxed(TIMERn_CMD_STOP, ddata->base + TIMERn_CMD); in efm32_clock_event_set_next_event()
93 writel_relaxed(evt, ddata->base in efm32_clock_event_set_next_event()
125 void __iomem *base; efm32_clocksource_init() local
183 void __iomem *base; efm32_clockevent_init() local
[all...]
H A Dtimer-ixp4xx.c57 void __iomem *base; member
80 return __raw_readl(local_ixp4xx_timer->base + IXP4XX_OSTS_OFFSET); in ixp4xx_read_timer()
100 tmr->base + IXP4XX_OSST_OFFSET); in ixp4xx_timer_interrupt()
113 val = __raw_readl(tmr->base + IXP4XX_OSRT1_OFFSET); in ixp4xx_set_next_event()
117 tmr->base + IXP4XX_OSRT1_OFFSET); in ixp4xx_set_next_event()
127 val = __raw_readl(tmr->base + IXP4XX_OSRT1_OFFSET); in ixp4xx_shutdown()
129 __raw_writel(val, tmr->base + IXP4XX_OSRT1_OFFSET); in ixp4xx_shutdown()
139 tmr->base + IXP4XX_OSRT1_OFFSET); in ixp4xx_set_oneshot()
151 __raw_writel(val, tmr->base + IXP4XX_OSRT1_OFFSET); in ixp4xx_set_periodic()
161 val = __raw_readl(tmr->base in ixp4xx_resume()
173 ixp4xx_timer_register(void __iomem *base, int timer_irq, unsigned int timer_freq) ixp4xx_timer_register() argument
252 void __iomem *base; ixp4xx_timer_setup() local
265 void __iomem *base; ixp4xx_of_timer_init() local
[all...]
/kernel/linux/linux-5.10/include/crypto/internal/
H A Dhash.h36 char head[offsetof(struct ahash_alg, halg.base)];
37 struct crypto_instance base; member
47 char head[offsetof(struct shash_alg, base)];
48 struct crypto_instance base; member
55 struct crypto_spawn base; member
59 struct crypto_spawn base; member
83 !(alg->base.cra_flags & CRYPTO_ALG_OPTIONAL_KEY); in crypto_shash_alg_needs_key()
94 crypto_drop_spawn(&spawn->base); in crypto_drop_ahash()
100 return __crypto_hash_alg_common(spawn->base.alg); in crypto_spawn_ahash_alg()
117 crypto_drop_spawn(&spawn->base); in crypto_drop_shash()
[all...]
/kernel/linux/linux-6.6/drivers/watchdog/
H A Dsunplus_wdt.c46 void __iomem *base; member
55 void __iomem *base = priv->base; in sp_wdt_restart() local
57 writel(WDT_STOP, base + WDT_CTRL); in sp_wdt_restart()
58 writel(WDT_UNLOCK, base + WDT_CTRL); in sp_wdt_restart()
59 writel(0x0001, base + WDT_CNT); in sp_wdt_restart()
60 writel(WDT_LOCK, base + WDT_CTRL); in sp_wdt_restart()
61 writel(WDT_RESUME, base + WDT_CTRL); in sp_wdt_restart()
69 void __iomem *base = priv->base; in sp_wdt_ping() local
93 void __iomem *base = priv->base; sp_wdt_stop() local
103 void __iomem *base = priv->base; sp_wdt_start() local
113 void __iomem *base = priv->base; sp_wdt_get_timeleft() local
[all...]
/third_party/musl/ldso/
H A Ddlstart.c24 size_t *rel, rel_size, base; in _dlstart_c() local
50 base = aux[AT_BASE]; in _dlstart_c()
51 if (!base) base = aux[AT_PHDR] & -4096; in _dlstart_c()
53 segs[0].addr = base; in _dlstart_c()
56 Ehdr *eh = (void *)base; in _dlstart_c()
57 Phdr *ph = (void *)(base + eh->e_phoff); in _dlstart_c()
62 dynv = (void *)(base + ph->p_vaddr); in _dlstart_c()
77 base = 0; in _dlstart_c()
104 base in _dlstart_c()
[all...]
/kernel/linux/linux-5.10/include/sound/
H A Dsnd_wavefront.h23 unsigned long base; /* I/O port address */ member
52 unsigned long base; /* low i/o port address */ member
55 #define mpu_data_port base
56 #define mpu_command_port base + 1 /* write semantics */
57 #define mpu_status_port base + 1 /* read semantics */
58 #define data_port base + 2
59 #define status_port base + 3 /* read semantics */
60 #define control_port base + 3 /* write semantics */
61 #define block_port base + 4 /* 16 bit, writeonly */
62 #define last_block_port base
[all...]
/kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/
H A Dbusnv50.c24 #define nv50_i2c_bus(p) container_of((p), struct nv50_i2c_bus, base)
30 struct nvkm_i2c_bus base; member
36 nv50_i2c_bus_drive_scl(struct nvkm_i2c_bus *base, int state) in nv50_i2c_bus_drive_scl() argument
38 struct nv50_i2c_bus *bus = nv50_i2c_bus(base); in nv50_i2c_bus_drive_scl()
39 struct nvkm_device *device = bus->base.pad->i2c->subdev.device; in nv50_i2c_bus_drive_scl()
46 nv50_i2c_bus_drive_sda(struct nvkm_i2c_bus *base, int state) in nv50_i2c_bus_drive_sda() argument
48 struct nv50_i2c_bus *bus = nv50_i2c_bus(base); in nv50_i2c_bus_drive_sda()
49 struct nvkm_device *device = bus->base.pad->i2c->subdev.device; in nv50_i2c_bus_drive_sda()
56 nv50_i2c_bus_sense_scl(struct nvkm_i2c_bus *base) in nv50_i2c_bus_sense_scl() argument
58 struct nv50_i2c_bus *bus = nv50_i2c_bus(base); in nv50_i2c_bus_sense_scl()
64 nv50_i2c_bus_sense_sda(struct nvkm_i2c_bus *base) nv50_i2c_bus_sense_sda() argument
72 nv50_i2c_bus_init(struct nvkm_i2c_bus *base) nv50_i2c_bus_init() argument
[all...]
/kernel/linux/linux-6.6/drivers/power/reset/
H A Dgemini-poweroff.c33 void __iomem *base; member
42 val = readl(gpw->base + GEMINI_PWC_CTRLREG); in gemini_powerbutton_interrupt()
44 writel(val, gpw->base + GEMINI_PWC_CTRLREG); in gemini_powerbutton_interrupt()
46 val = readl(gpw->base + GEMINI_PWC_STATREG); in gemini_powerbutton_interrupt()
82 val = readl(gpw->base + GEMINI_PWC_CTRLREG); in gemini_poweroff()
84 writel(val, gpw->base + GEMINI_PWC_CTRLREG); in gemini_poweroff()
88 writel(val, gpw->base + GEMINI_PWC_CTRLREG); in gemini_poweroff()
103 gpw->base = devm_platform_ioremap_resource(pdev, 0); in gemini_poweroff_probe()
104 if (IS_ERR(gpw->base)) in gemini_poweroff_probe()
105 return PTR_ERR(gpw->base); in gemini_poweroff_probe()
[all...]
/kernel/linux/linux-6.6/include/sound/
H A Dsnd_wavefront.h23 unsigned long base; /* I/O port address */ member
52 unsigned long base; /* low i/o port address */ member
55 #define mpu_data_port base
56 #define mpu_command_port base + 1 /* write semantics */
57 #define mpu_status_port base + 1 /* read semantics */
58 #define data_port base + 2
59 #define status_port base + 3 /* read semantics */
60 #define control_port base + 3 /* write semantics */
61 #define block_port base + 4 /* 16 bit, writeonly */
62 #define last_block_port base
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/
H A Dbusnv50.c24 #define nv50_i2c_bus(p) container_of((p), struct nv50_i2c_bus, base)
30 struct nvkm_i2c_bus base; member
36 nv50_i2c_bus_drive_scl(struct nvkm_i2c_bus *base, int state) in nv50_i2c_bus_drive_scl() argument
38 struct nv50_i2c_bus *bus = nv50_i2c_bus(base); in nv50_i2c_bus_drive_scl()
39 struct nvkm_device *device = bus->base.pad->i2c->subdev.device; in nv50_i2c_bus_drive_scl()
46 nv50_i2c_bus_drive_sda(struct nvkm_i2c_bus *base, int state) in nv50_i2c_bus_drive_sda() argument
48 struct nv50_i2c_bus *bus = nv50_i2c_bus(base); in nv50_i2c_bus_drive_sda()
49 struct nvkm_device *device = bus->base.pad->i2c->subdev.device; in nv50_i2c_bus_drive_sda()
56 nv50_i2c_bus_sense_scl(struct nvkm_i2c_bus *base) in nv50_i2c_bus_sense_scl() argument
58 struct nv50_i2c_bus *bus = nv50_i2c_bus(base); in nv50_i2c_bus_sense_scl()
64 nv50_i2c_bus_sense_sda(struct nvkm_i2c_bus *base) nv50_i2c_bus_sense_sda() argument
72 nv50_i2c_bus_init(struct nvkm_i2c_bus *base) nv50_i2c_bus_init() argument
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/nouveau/nvkm/subdev/fb/
H A Dgf100.c32 gf100_fb_intr(struct nvkm_fb *base) in gf100_fb_intr() argument
34 struct gf100_fb *fb = gf100_fb(base); in gf100_fb_intr()
35 struct nvkm_subdev *subdev = &fb->base.subdev; in gf100_fb_intr()
45 gf100_fb_oneinit(struct nvkm_fb *base) in gf100_fb_oneinit() argument
47 struct gf100_fb *fb = gf100_fb(base); in gf100_fb_oneinit()
48 struct nvkm_device *device = fb->base.subdev.device; in gf100_fb_oneinit()
49 int ret, size = 1 << (fb->base.page ? fb->base.page : 17); in gf100_fb_oneinit()
55 true, &fb->base.mmu_rd); in gf100_fb_oneinit()
60 true, &fb->base in gf100_fb_oneinit()
87 gf100_fb_init(struct nvkm_fb *base) gf100_fb_init() argument
99 gf100_fb_dtor(struct nvkm_fb *base) gf100_fb_dtor() argument
[all...]
/third_party/curl/lib/
H A Dinet_ntop.c99 int base; in inet_ntop6() member
113 best.base = -1; in inet_ntop6()
114 cur.base = -1; in inet_ntop6()
120 if(cur.base == -1) { in inet_ntop6()
121 cur.base = i; cur.len = 1; in inet_ntop6()
126 else if(cur.base != -1) { in inet_ntop6()
127 if(best.base == -1 || cur.len > best.len) in inet_ntop6()
129 cur.base = -1; in inet_ntop6()
132 if((cur.base != -1) && (best.base in inet_ntop6()
[all...]
/third_party/node/deps/cares/src/lib/
H A Dinet_ntop.c117 int base, len; in inet_ntop6() member
132 best.base = -1; in inet_ntop6()
134 cur.base = -1; in inet_ntop6()
138 if (cur.base == -1) { in inet_ntop6()
139 cur.base = i, cur.len = 1; in inet_ntop6()
144 if (cur.base != -1) { in inet_ntop6()
145 if (best.base == -1 || cur.len > best.len) { in inet_ntop6()
148 cur.base = -1; in inet_ntop6()
152 if (cur.base != -1) { in inet_ntop6()
153 if (best.base in inet_ntop6()
[all...]
/third_party/musl/porting/liteos_a/kernel/src/stdlib/
H A Dstrtol.c8 static unsigned long long strtox(const char *s, char **p, int base, unsigned long long lim) in strtox() argument
13 unsigned long long y = __intscan(&f, base, 1, lim); in strtox()
21 unsigned long long strtoull(const char *restrict s, char **restrict p, int base) in strtoull() argument
23 return strtox(s, p, base, ULLONG_MAX); in strtoull()
26 long long strtoll(const char *restrict s, char **restrict p, int base) in strtoll() argument
28 return strtox(s, p, base, LLONG_MIN); in strtoll()
31 unsigned long strtoul(const char *restrict s, char **restrict p, int base) in strtoul() argument
33 return strtox(s, p, base, ULONG_MAX); in strtoul()
36 long strtol(const char *restrict s, char **restrict p, int base) in strtol() argument
38 return strtox(s, p, base, in strtol()
41 strtoimax(const char *restrict s, char **restrict p, int base) strtoimax() argument
46 strtoumax(const char *restrict s, char **restrict p, int base) strtoumax() argument
[all...]
/third_party/skia/third_party/externals/libjpeg-turbo/gtest/
H A Dgtest-utils.cpp21 #include "base/strings/utf_string_conversions.h"
26 base::FilePath path; in GetTargetDirectory()
27 base::PathService::Get(base::DIR_CURRENT, &path); in GetTargetDirectory()
28 return base::UTF8ToWide(path.MaybeAsASCII()); in GetTargetDirectory()
35 base::FilePath path; in GetTargetDirectory()
36 base::PathService::Get(base::DIR_CURRENT, &path); in GetTargetDirectory()
42 void GetTestFilePath(base::FilePath* path, const std::string filename) { in GetTestFilePath()
43 ASSERT_TRUE(base in GetTestFilePath()
[all...]
/kernel/linux/linux-5.10/drivers/pci/controller/
H A Dpcie-brcmstb.c255 void __iomem *base; member
268 /* This is the base pointer for interrupt status/set/clr regs */
275 void __iomem *base; member
322 static int brcm_pcie_mdio_read(void __iomem *base, u8 port, u8 regad, u32 *val) in brcm_pcie_mdio_read() argument
328 base + PCIE_RC_DL_MDIO_ADDR); in brcm_pcie_mdio_read()
329 readl(base + PCIE_RC_DL_MDIO_ADDR); in brcm_pcie_mdio_read()
331 data = readl(base + PCIE_RC_DL_MDIO_RD_DATA); in brcm_pcie_mdio_read()
334 data = readl(base + PCIE_RC_DL_MDIO_RD_DATA); in brcm_pcie_mdio_read()
342 static int brcm_pcie_mdio_write(void __iomem *base, u8 port, in brcm_pcie_mdio_write() argument
349 base in brcm_pcie_mdio_write()
683 void __iomem *base = pcie->base; brcm_pcie_rc_mode() local
711 void __iomem *base = pcie->base; brcm_pcie_map_conf() local
860 void __iomem *base = pcie->base; brcm_pcie_setup() local
1042 void __iomem *base = pcie->base; brcm_pcie_enter_l23() local
1079 void __iomem *base = pcie->base; brcm_phy_cntl() local
1113 void __iomem *base = pcie->base; brcm_pcie_turn_off() local
1150 void __iomem *base; brcm_pcie_resume() local
[all...]
/kernel/linux/linux-5.10/drivers/phy/qualcomm/
H A Dphy-qcom-pcie2.c41 void __iomem *base; member
75 val = readl(qphy->base + PCIE20_PARF_PHY_REFCLK_CTRL2); in qcom_pcie2_phy_power_on()
77 writel(val, qphy->base + PCIE20_PARF_PHY_REFCLK_CTRL2); in qcom_pcie2_phy_power_on()
82 val = readl(qphy->base + PCIE20_PARF_PHY_REFCLK_CTRL2); in qcom_pcie2_phy_power_on()
84 writel(val, qphy->base + PCIE20_PARF_PHY_REFCLK_CTRL2); in qcom_pcie2_phy_power_on()
87 val = readl(qphy->base + PCIE20_PARF_PHY_REFCLK_CTRL3); in qcom_pcie2_phy_power_on()
89 writel(val, qphy->base + PCIE20_PARF_PHY_REFCLK_CTRL3); in qcom_pcie2_phy_power_on()
94 val = readl(qphy->base + PCIE2_PHY_RESET_CTRL); in qcom_pcie2_phy_power_on()
96 writel(val, qphy->base + PCIE2_PHY_RESET_CTRL); in qcom_pcie2_phy_power_on()
99 val = readl(qphy->base in qcom_pcie2_phy_power_on()
[all...]

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