phy-qcom-pcie2.c - OpenGrok cross reference for /kernel/linux/linux-5.10/drivers/phy/qualcomm/phy-qcom-pcie2.c

Lines Matching refs:base
41 	void __iomem *base;
75 	val = readl(qphy->base + PCIE20_PARF_PHY_REFCLK_CTRL2);
77 	writel(val, qphy->base + PCIE20_PARF_PHY_REFCLK_CTRL2);
82 	val = readl(qphy->base + PCIE20_PARF_PHY_REFCLK_CTRL2);
84 	writel(val, qphy->base + PCIE20_PARF_PHY_REFCLK_CTRL2);
87 	val = readl(qphy->base + PCIE20_PARF_PHY_REFCLK_CTRL3);
89 	writel(val, qphy->base + PCIE20_PARF_PHY_REFCLK_CTRL3);
94 	val = readl(qphy->base + PCIE2_PHY_RESET_CTRL);
96 	writel(val, qphy->base + PCIE2_PHY_RESET_CTRL);
99 	val = readl(qphy->base + PCIE20_PARF_PCS_SWING_CTRL1);
102 	writel(val, qphy->base + PCIE20_PARF_PCS_SWING_CTRL1);
104 	val = readl(qphy->base + PCIE20_PARF_PCS_SWING_CTRL2);
107 	writel(val, qphy->base + PCIE20_PARF_PCS_SWING_CTRL2);
110 	val = readl(qphy->base + PCIE20_PARF_PCS_DEEMPH1);
113 	writel(val, qphy->base + PCIE20_PARF_PCS_DEEMPH1);
115 	val = readl(qphy->base + PCIE20_PARF_PCS_DEEMPH2);
118 	writel(val, qphy->base + PCIE20_PARF_PCS_DEEMPH2);
120 	val = readl(qphy->base + PCIE20_PARF_PCS_DEEMPH3);
123 	writel(val, qphy->base + PCIE20_PARF_PCS_DEEMPH3);
126 	val = readl(qphy->base + PCIE20_PARF_CONFIGBITS);
129 	writel(val, qphy->base + PCIE20_PARF_CONFIGBITS);
132 	val = readl(qphy->base + PCIE20_PARF_PHY_CTRL3);
135 	writel(val, qphy->base + PCIE20_PARF_PHY_CTRL3);
138 	val = readl(qphy->base + PCIE20_PARF_PCS_CTRL);
140 	writel(val, qphy->base + PCIE20_PARF_PCS_CTRL);
143 	val = readl(qphy->base + PCIE2_PHY_RESET_CTRL);
145 	writel(val, qphy->base + PCIE2_PHY_RESET_CTRL);
163 	ret = readl_poll_timeout(qphy->base + PCIE20_PARF_PHY_STTS, val,
177 	val = readl(qphy->base + PCIE2_PHY_RESET_CTRL);
179 	writel(val, qphy->base + PCIE2_PHY_RESET_CTRL);
265 	qphy->base = devm_ioremap_resource(dev, res);
266 	if (IS_ERR(qphy->base))
267 		return PTR_ERR(qphy->base);