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/kernel/linux/linux-5.10/drivers/gpu/drm/msm/disp/dpu1/
H A Ddpu_crtc.c90 drm_get_format_name(format->base.pixel_format, &format_name), in _dpu_crtc_setup_blend_cfg()
146 crtc->base.id, in _dpu_crtc_blend_setup_mixer()
148 plane->base.id, in _dpu_crtc_blend_setup_mixer()
150 state->fb ? state->fb->base.id : -1); in _dpu_crtc_blend_setup_mixer()
152 format = to_dpu_format(msm_framebuffer_format(pstate->base.fb)); in _dpu_crtc_blend_setup_mixer()
166 format->base.pixel_format, in _dpu_crtc_blend_setup_mixer()
310 DRM_DEBUG_KMS("crtc%d event:%u ts:%lld\n", crtc->base.id, fevent->event, in dpu_crtc_frame_event_work()
339 crtc->base.id, ktime_to_ns(fevent->ts)); in dpu_crtc_frame_event_work()
386 DRM_ERROR_RATELIMITED("crtc%d event %d overflow\n", crtc->base.id, event); in dpu_crtc_frame_event_cb()
495 crtc->base in dpu_crtc_atomic_begin()
[all...]
/kernel/linux/linux-5.10/drivers/gpu/drm/vc4/
H A Dvc4_gem.c126 bo_state[i].paddr = vc4_bo->base.paddr; in vc4_get_hang_state_ioctl()
127 bo_state[i].size = vc4_bo->base.base.size; in vc4_get_hang_state_ioctl()
199 bo = to_vc4_bo(&exec[i]->bo[j]->base); in vc4_save_hang_state()
207 drm_gem_object_get(&exec[i]->bo[j]->base); in vc4_save_hang_state()
208 kernel_state->bo[k++] = &exec[i]->bo[j]->base; in vc4_save_hang_state()
215 drm_gem_object_get(&bo->base.base); in vc4_save_hang_state()
216 kernel_state->bo[k++] = &bo->base.base; in vc4_save_hang_state()
[all...]
/kernel/linux/linux-6.6/drivers/net/ethernet/hisilicon/
H A Dhip04_eth.c210 void __iomem *base; member
284 writel_relaxed(val, priv->base + GE_PORT_MODE); in hip04_config_port()
287 writel_relaxed(val, priv->base + GE_DUPLEX_TYPE); in hip04_config_port()
290 writel_relaxed(val, priv->base + GE_MODE_CHANGE_REG); in hip04_config_port()
316 val = readl_relaxed(priv->base + PPE_CFG_STS_MODE); in hip04_config_fifo()
318 writel_relaxed(val, priv->base + PPE_CFG_STS_MODE); in hip04_config_fifo()
325 writel_relaxed(val, priv->base + PPE_CFG_QOS_VMID_GEN); in hip04_config_fifo()
336 writel_relaxed(val, priv->base + PPE_CFG_RX_CTRL_REG); in hip04_config_fifo()
339 writel_relaxed(val, priv->base + PPE_CFG_RX_PKT_MODE_REG); in hip04_config_fifo()
342 writel_relaxed(val, priv->base in hip04_config_fifo()
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/i915/display/
H A Dintel_display_types.h136 struct drm_framebuffer base; member
156 struct drm_encoder base; member
207 * pre-filled the pipe config. Note that intel_encoder->base.crtc must
593 struct drm_connector base; member
630 struct drm_connector_state base; member
636 #define to_intel_digital_connector_state(x) container_of(x, struct intel_digital_connector_state, base)
651 struct drm_atomic_state base; member
775 u32 base; member
1436 struct drm_crtc base; member
1511 struct drm_plane base; member
1519 u32 base, cntl, size; global() member
1827 struct intel_encoder base; global() member
1872 struct intel_encoder base; global() member
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/third_party/icu/icu4j/main/classes/collate/src/com/ibm/icu/impl/coll/
H A DCollationDataBuilder.java52 base = null; in CollationDataBuilder()
73 base = b; in initForTailoring()
75 // For a tailoring, the default is to fall back to the base. in initForTailoring()
100 return base.isCompressibleLeadByte(b); in isCompressibleLeadByte()
186 // If c has contextual base mappings or if we add a contextual mapping, in addCE32()
187 // then copy the base mappings. in addCE32()
188 // Otherwise we just override the base mapping. in addCE32()
189 int baseCE32 = base.getFinalCE32(base.getCE32(c)); in addCE32()
277 ce32 = base in optimize()
1370 protected CollationData base; global() field in CollationDataBuilder
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/third_party/icu/ohos_icu4j/src/main/java/ohos/global/icu/impl/coll/
H A DCollationDataBuilder.java53 base = null; in CollationDataBuilder()
74 base = b; in initForTailoring()
76 // For a tailoring, the default is to fall back to the base. in initForTailoring()
101 return base.isCompressibleLeadByte(b); in isCompressibleLeadByte()
187 // If c has contextual base mappings or if we add a contextual mapping, in addCE32()
188 // then copy the base mappings. in addCE32()
189 // Otherwise we just override the base mapping. in addCE32()
190 int baseCE32 = base.getFinalCE32(base.getCE32(c)); in addCE32()
278 ce32 = base in optimize()
1339 protected CollationData base; global() field in CollationDataBuilder
[all...]
/third_party/mesa3d/src/gallium/drivers/crocus/
H A Dcrocus_resolve.c69 struct crocus_resource *rb_res = (void *) surf->base.texture; in disable_rb_aux_buffer()
72 surf->base.u.tex.level >= min_level && in disable_rb_aux_buffer()
73 surf->base.u.tex.level < min_level + num_levels) { in disable_rb_aux_buffer()
101 if (isv->res->base.b.target != PIPE_BUFFER) { in resolve_sampler_views()
117 (isv->base.format == PIPE_FORMAT_X24S8_UINT || in resolve_sampler_views()
118 isv->base.format == PIPE_FORMAT_X32_S8X24_UINT || in resolve_sampler_views()
119 isv->base.format == PIPE_FORMAT_S8_UINT)) { in resolve_sampler_views()
121 crocus_get_depth_stencil_resources(&batch->screen->devinfo, isv->base.texture, &zres, &sres); in resolve_sampler_views()
140 struct pipe_image_view *pview = &shs->image[i].base; in resolve_image_views()
143 if (res->base in resolve_image_views()
[all...]
/third_party/python/Objects/
H A Dtypeobject.c287 subclasses. This function is called after the base in PyType_Modified()
328 Check that all base classes or elements of the MRO of type are in type_mro_modified()
329 able to be cached. This function is called after the base in type_mro_modified()
752 PyTypeObject *base = (PyTypeObject*)ob; in type_set_bases() local
754 if (PyType_IsSubtype(base, type) || in type_set_bases()
757 base->tp_mro which would gonna be updated inside in type_set_bases()
760 However, base->tp_base has already been assigned (see in type_set_bases()
764 (base->tp_mro != NULL && type_is_subtype_base_chain(base, type))) in type_set_bases()
772 // Compute the new MRO and the new base clas in type_set_bases()
1201 PyTypeObject *type, *base; subtype_traverse() local
1271 PyTypeObject *type, *base; subtype_clear() local
1304 PyTypeObject *type, *base; subtype_dealloc() local
1930 PyTypeObject *base = _PyType_CAST(PyTuple_GET_ITEM(bases, i)); mro_implementation() local
1944 PyTypeObject *base = _PyType_CAST(PyTuple_GET_ITEM(bases, 0)); mro_implementation() local
1981 PyTypeObject *base = _PyType_CAST(PyTuple_GET_ITEM(bases, i)); mro_implementation() local
2038 PyTypeObject *base = (PyTypeObject*)obj; mro_check() local
2176 PyTypeObject *base, *winner, *candidate; best_base() local
2233 extra_ivars(PyTypeObject *type, PyTypeObject *base) extra_ivars() argument
2262 PyTypeObject *base; solid_base() local
2322 PyTypeObject *base; subtype_dict() local
2346 PyTypeObject *base; subtype_setdict() local
2531 PyTypeObject *base; global() member
2663 PyTypeObject *base = _PyType_CAST(obj); type_new_slots_bases() local
3030 PyTypeObject *base = ctx->base; type_new_set_slots() local
3239 PyObject *base = PyTuple_GET_ITEM(ctx->bases, i); type_new_get_bases() local
3278 PyTypeObject *base = best_base(ctx->bases); type_new_get_bases() local
3381 PyTypeObject *type, *base; PyType_FromModuleAndSpec() local
3793 PyObject *base = PyTuple_GET_ITEM(mro, i); find_name_in_mro() local
4226 PyObject *base = PySequence_GetItem(bases, i); merge_class_dict() local
4698 PyTypeObject *base = a->tp_base; same_slots_added() local
5779 inherit_special(PyTypeObject *type, PyTypeObject *base) inherit_special() argument
5850 inherit_slots(PyTypeObject *type, PyTypeObject *base) inherit_slots() argument
6086 PyTypeObject *base = type->tp_base; type_ready_set_bases() local
6122 PyTypeObject *base = type->tp_base; type_ready_set_bases() local
6228 PyTypeObject *base = _PyType_CAST(PyTuple_GET_ITEM(mro, i)); type_ready_mro() local
6248 type_ready_inherit_as_structs(PyTypeObject *type, PyTypeObject *base) type_ready_inherit_as_structs() argument
6268 inherit_patma_flags(PyTypeObject *type, PyTypeObject *base) inherit_patma_flags() argument
6278 PyTypeObject *base = type->tp_base; type_ready_inherit() local
6367 PyTypeObject *base = type->tp_base; type_ready_set_new() local
6528 add_subclass(PyTypeObject *base, PyTypeObject *type) add_subclass() argument
6568 PyTypeObject *base = _PyType_CAST(obj); add_all_subclasses() local
6577 remove_subclass(PyTypeObject *base, PyTypeObject *type) remove_subclass() argument
6610 PyObject *base = PyTuple_GET_ITEM(bases, i); remove_all_subclasses() local
6907 PyTypeObject *base = _PyType_CAST(PyTuple_GET_ITEM(mro, i)); hackcheck() local
[all...]
/kernel/linux/linux-5.10/drivers/crypto/qce/
H A Dsha.c128 struct qce_alg_template *tmpl = to_ahash_tmpl(req->base.tfm); in qce_ahash_init()
239 struct qce_alg_template *tmpl = to_ahash_tmpl(req->base.tfm); in qce_ahash_update()
306 return qce->async_req_enqueue(tmpl->qce, &req->base); in qce_ahash_update()
312 struct qce_alg_template *tmpl = to_ahash_tmpl(req->base.tfm); in qce_ahash_final()
333 return qce->async_req_enqueue(tmpl->qce, &req->base); in qce_ahash_final()
339 struct qce_alg_template *tmpl = to_ahash_tmpl(req->base.tfm); in qce_ahash_digest()
359 return qce->async_req_enqueue(tmpl->qce, &req->base); in qce_ahash_digest()
366 struct qce_sha_ctx *ctx = crypto_tfm_ctx(&tfm->base); in qce_ahash_hmac_setkey()
490 struct crypto_alg *base; in qce_ahash_register_one() local
516 base in qce_ahash_register_one()
[all...]
/kernel/linux/linux-5.10/drivers/spi/
H A Dspi-axi-spi-engine.c87 void __iomem *base; member
299 void __iomem *addr = spi_engine->base + SPI_ENGINE_REG_CMD_FIFO; in spi_engine_write_cmd_fifo()
303 n = readl_relaxed(spi_engine->base + SPI_ENGINE_REG_CMD_FIFO_ROOM); in spi_engine_write_cmd_fifo()
319 void __iomem *addr = spi_engine->base + SPI_ENGINE_REG_SDO_DATA_FIFO; in spi_engine_write_tx_fifo()
323 n = readl_relaxed(spi_engine->base + SPI_ENGINE_REG_SDO_FIFO_ROOM); in spi_engine_write_tx_fifo()
341 void __iomem *addr = spi_engine->base + SPI_ENGINE_REG_SDI_DATA_FIFO; in spi_engine_read_rx_fifo()
345 n = readl_relaxed(spi_engine->base + SPI_ENGINE_REG_SDI_FIFO_LEVEL); in spi_engine_read_rx_fifo()
368 pending = readl_relaxed(spi_engine->base + SPI_ENGINE_REG_INT_PENDING); in spi_engine_irq()
372 spi_engine->base + SPI_ENGINE_REG_INT_PENDING); in spi_engine_irq()
374 spi_engine->base in spi_engine_irq()
[all...]
H A Dspi-qcom-qspi.c140 void __iomem *base; member
174 pio_xfer_cfg = readl(ctrl->base + PIO_XFER_CFG); in qcom_qspi_pio_xfer_cfg()
184 writel(pio_xfer_cfg, ctrl->base + PIO_XFER_CFG); in qcom_qspi_pio_xfer_cfg()
191 pio_xfer_ctrl = readl(ctrl->base + PIO_XFER_CTRL); in qcom_qspi_pio_xfer_ctrl()
194 writel(pio_xfer_ctrl, ctrl->base + PIO_XFER_CTRL); in qcom_qspi_pio_xfer_ctrl()
204 writel(QSPI_ALL_IRQS, ctrl->base + MSTR_INT_STATUS); in qcom_qspi_pio_xfer()
211 writel(ints, ctrl->base + MSTR_INT_EN); in qcom_qspi_pio_xfer()
224 writel(0, ctrl->base + MSTR_INT_EN); in qcom_qspi_handle_err()
313 mstr_cfg = readl(ctrl->base + MSTR_CONFIG); in qcom_qspi_prepare_message()
325 writel(mstr_cfg, ctrl->base in qcom_qspi_prepare_message()
[all...]
/kernel/linux/linux-6.6/drivers/spi/
H A Dspi-axi-spi-engine.c87 void __iomem *base; member
295 void __iomem *addr = spi_engine->base + SPI_ENGINE_REG_CMD_FIFO; in spi_engine_write_cmd_fifo()
299 n = readl_relaxed(spi_engine->base + SPI_ENGINE_REG_CMD_FIFO_ROOM); in spi_engine_write_cmd_fifo()
315 void __iomem *addr = spi_engine->base + SPI_ENGINE_REG_SDO_DATA_FIFO; in spi_engine_write_tx_fifo()
319 n = readl_relaxed(spi_engine->base + SPI_ENGINE_REG_SDO_FIFO_ROOM); in spi_engine_write_tx_fifo()
337 void __iomem *addr = spi_engine->base + SPI_ENGINE_REG_SDI_DATA_FIFO; in spi_engine_read_rx_fifo()
341 n = readl_relaxed(spi_engine->base + SPI_ENGINE_REG_SDI_FIFO_LEVEL); in spi_engine_read_rx_fifo()
364 pending = readl_relaxed(spi_engine->base + SPI_ENGINE_REG_INT_PENDING); in spi_engine_irq()
368 spi_engine->base + SPI_ENGINE_REG_INT_PENDING); in spi_engine_irq()
370 spi_engine->base in spi_engine_irq()
[all...]
/kernel/linux/linux-6.6/drivers/crypto/qce/
H A Dsha.c136 struct qce_alg_template *tmpl = to_ahash_tmpl(req->base.tfm); in qce_ahash_init()
187 struct qce_alg_template *tmpl = to_ahash_tmpl(req->base.tfm); in qce_ahash_update()
273 return qce->async_req_enqueue(tmpl->qce, &req->base); in qce_ahash_update()
279 struct qce_alg_template *tmpl = to_ahash_tmpl(req->base.tfm); in qce_ahash_final()
300 return qce->async_req_enqueue(tmpl->qce, &req->base); in qce_ahash_final()
306 struct qce_alg_template *tmpl = to_ahash_tmpl(req->base.tfm); in qce_ahash_digest()
326 return qce->async_req_enqueue(tmpl->qce, &req->base); in qce_ahash_digest()
333 struct qce_sha_ctx *ctx = crypto_tfm_ctx(&tfm->base); in qce_ahash_hmac_setkey()
457 struct crypto_alg *base; in qce_ahash_register_one() local
483 base in qce_ahash_register_one()
[all...]
/kernel/linux/linux-6.6/drivers/perf/
H A Dfsl_imx8_ddr_perf.c98 void __iomem *base; member
359 void __iomem *base = pmu->base; in ddr_perf_read_counter() local
366 base += ddr_perf_is_enhanced_filtered(event) ? COUNTER_DPCR1 : in ddr_perf_read_counter()
368 return readl_relaxed(base + counter * 4); in ddr_perf_read_counter()
431 writel(0, pmu->base + reg); in ddr_perf_counter_enable()
445 writel(val, pmu->base + reg); in ddr_perf_counter_enable()
448 val = readl_relaxed(pmu->base + reg) & CNTL_EN_MASK; in ddr_perf_counter_enable()
449 writel(val, pmu->base + reg); in ddr_perf_counter_enable()
457 val = readl_relaxed(pmu->base in ddr_perf_counter_overflow()
603 ddr_perf_init(struct ddr_pmu *pmu, void __iomem *base, struct device *dev) ddr_perf_init() argument
694 void __iomem *base; ddr_perf_probe() local
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/
H A Ddrm_mode_config.c116 put_user(fb->base.id, fb_id + count)) { in drm_mode_getresources()
133 if (drm_lease_held(file_priv, crtc->base.id)) { in drm_mode_getresources()
135 put_user(crtc->base.id, crtc_id + count)) in drm_mode_getresources()
146 put_user(encoder->base.id, encoder_id + count)) in drm_mode_getresources()
161 if (drm_lease_held(file_priv, connector->base.id)) { in drm_mode_getresources()
163 put_user(connector->base.id, connector_id + count)) { in drm_mode_getresources()
551 drm_printf(&p, "framebuffer[%u]:\n", fb->base.id); in drm_mode_config_cleanup()
553 drm_framebuffer_free(&fb->base.refcount); in drm_mode_config_cleanup()
597 encoder->base.id, encoder->name, in validate_encoder_possible_clones()
599 other->base in validate_encoder_possible_clones()
[all...]
/third_party/node/deps/v8/src/wasm/
H A Dwasm-external-refs.cc12 #include "src/base/bits.h"
13 #include "src/base/ieee754.h"
14 #include "src/base/safe_conversions.h"
35 #include "src/base/memory.h"
43 using base::ReadUnalignedValue;
44 using base::WriteUnalignedValue;
128 uint32_t leading_zeros = base::bits::CountLeadingZeros(input); in uint64_to_float32_wrapper()
129 uint32_t trailing_zeros = base::bits::CountTrailingZeros(input); in uint64_to_float32_wrapper()
193 if (base::IsValueInRangeForNumericType<int64_t>(input)) { in float32_to_int64_wrapper()
202 if (base in float32_to_uint64_wrapper()
[all...]
/third_party/mesa3d/src/gallium/drivers/nouveau/nvc0/
H A Dnvc0_query_hw.c47 nouveau_fence_work(screen->base.fence.current, in nvc0_hw_query_allocate()
52 hq->mm = nouveau_mm_allocate(screen->base.mm_GART, size, &hq->bo, in nvc0_hw_query_allocate()
58 ret = nouveau_bo_map(hq->bo, 0, nvc0->base.client); in nvc0_hw_query_allocate()
130 struct nouveau_pushbuf *push = nvc0->base.pushbuf; in nvc0_hw_query_write_compute_invocations()
144 struct nouveau_pushbuf *push = nvc0->base.pushbuf; in nvc0_hw_begin_query()
229 struct nouveau_pushbuf *push = nvc0->base.pushbuf; in nvc0_hw_end_query()
304 nouveau_fence_ref(nvc0->screen->base.fence.current, &hq->fence); in nvc0_hw_end_query()
322 nvc0_hw_query_update(nvc0->base.client, q); in nvc0_hw_get_query_result()
329 PUSH_KICK(nvc0->base.pushbuf); in nvc0_hw_get_query_result()
333 if (nouveau_bo_wait(hq->bo, NOUVEAU_BO_RD, nvc0->base in nvc0_hw_get_query_result()
[all...]
H A Dnvc0_surface.c90 struct nouveau_bo *bo = mt->base.bo; in nvc0_2d_texture_set()
103 width = u_minify(mt->base.base.width0, level) << mt->ms_x; in nvc0_2d_texture_set()
104 height = u_minify(mt->base.base.height0, level) << mt->ms_y; in nvc0_2d_texture_set()
105 depth = u_minify(mt->base.base.depth0, level); in nvc0_2d_texture_set()
168 const enum pipe_format dfmt = dst->base.base.format; in nvc0_2d_texture_do_copy()
169 const enum pipe_format sfmt = src->base in nvc0_2d_texture_do_copy()
[all...]
/third_party/python/Lib/distutils/
H A Dmsvc9compiler.py64 for base in HKEYS:
65 d = cls.read_values(base, path)
71 def read_keys(cls, base, key):
74 handle = RegOpenKeyEx(base, key)
89 def read_values(cls, base, key):
95 handle = RegOpenKeyEx(base, key)
153 for base in HKEYS:
155 h = RegOpenKeyEx(base, p)
159 d = Reg.get_value(base, r"%s\%s" % (p, key))
318 # base clas
[all...]
/foundation/graphic/graphic_3d/lume/metaobject/src/
H A Dregister_anys.cpp15 #include <base/math/matrix.h>
16 #include <base/math/quaternion.h>
17 #include <base/math/vector.h>
19 #include <meta/base/meta_types.h>
20 #include <meta/base/namespace.h>
21 #include <meta/base/time_span.h>
22 #include <meta/base/type_traits.h>
/foundation/graphic/graphic_3d/lume/LumeEngine/src/perf/
H A Dperformance_data_manager.h23 #include <base/containers/fixed_string.h>
24 #include <base/containers/string.h>
25 #include <base/containers/string_view.h>
26 #include <base/containers/unique_ptr.h>
27 #include <base/containers/unordered_map.h>
28 #include <base/containers/vector.h>
29 #include <base/namespace.h>
/foundation/graphic/graphic_3d/lume/LumeEngine/src/os/ohos/
H A Dohos_filesystem.cpp26 #include <base/containers/iterator.h>
27 #include <base/containers/string.h>
28 #include <base/containers/string_view.h>
29 #include <base/containers/type_traits.h>
30 #include <base/containers/unique_ptr.h>
31 #include <base/containers/vector.h>
32 #include <base/namespace.h>
/foundation/graphic/graphic_3d/lume/LumeEngine/api/core/perf/
H A Dintf_performance_data_manager.h21 #include <base/containers/fixed_string.h>
22 #include <base/containers/refcnt_ptr.h>
23 #include <base/containers/string_view.h>
24 #include <base/containers/unordered_map.h>
25 #include <base/containers/vector.h>
26 #include <base/namespace.h>
27 #include <base/util/uid.h>
/kernel/linux/linux-5.10/drivers/crypto/vmx/
H A Daes_ctr.c133 .base.cra_name = "ctr(aes)",
134 .base.cra_driver_name = "p8_aes_ctr",
135 .base.cra_module = THIS_MODULE,
136 .base.cra_priority = 2000,
137 .base.cra_flags = CRYPTO_ALG_NEED_FALLBACK,
138 .base.cra_blocksize = 1,
139 .base.cra_ctxsize = sizeof(struct p8_aes_ctr_ctx),
H A Daes_cbc.c118 .base.cra_name = "cbc(aes)",
119 .base.cra_driver_name = "p8_aes_cbc",
120 .base.cra_module = THIS_MODULE,
121 .base.cra_priority = 2000,
122 .base.cra_flags = CRYPTO_ALG_NEED_FALLBACK,
123 .base.cra_blocksize = AES_BLOCK_SIZE,
124 .base.cra_ctxsize = sizeof(struct p8_aes_cbc_ctx),

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