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/kernel/linux/linux-6.6/drivers/gpu/drm/loongson/
H A Dlsdc_drv.h124 struct drm_crtc base; member
147 struct drm_plane base; member
165 struct drm_plane base; member
233 return container_of(crtc, struct lsdc_crtc, base); in to_lsdc_crtc()
239 return container_of(crtc, struct lsdc_display_pipe, crtc.base); in crtc_to_display_pipe()
245 return container_of(plane, struct lsdc_primary, base); in to_lsdc_primary()
251 return container_of(plane, struct lsdc_cursor, base); in to_lsdc_cursor()
255 struct drm_crtc_state base; member
266 struct drm_device base; member
307 return container_of(ddev, struct lsdc_device, base); in to_lsdc()
311 to_lsdc_crtc_state(struct drm_crtc_state *base) to_lsdc_crtc_state() argument
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/nouveau/nvkm/engine/disp/
H A Dchan.c34 u64 size, base = chan->func->user(chan, &size); in nvkm_disp_chan_rd32() local
36 *data = nvkm_rd32(device, base + addr); in nvkm_disp_chan_rd32()
45 u64 size, base = chan->func->user(chan, &size); in nvkm_disp_chan_wr32() local
47 nvkm_wr32(device, base + addr, data); in nvkm_disp_chan_wr32()
74 const u64 base = device->func->resource_addr(device, 0); in nvkm_disp_chan_map() local
77 *addr = base + chan->func->user(chan, size); in nvkm_disp_chan_map()
88 nvkm_disp_chan_child_del_(struct nvkm_oproxy *base) in nvkm_disp_chan_child_del_() argument
90 struct nvkm_disp_chan_object *object = container_of(base, typeof(*object), oproxy); in nvkm_disp_chan_child_del_()
115 *pobject = &object->oproxy.base; in nvkm_disp_chan_child_new()
140 if (sclass->engine && sclass->engine->func->base in nvkm_disp_chan_child_get()
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/kernel/linux/linux-6.6/drivers/irqchip/
H A Dirq-mbigen.c60 * @base: mapped address of this mbigen chip.
64 void __iomem *base; member
106 void __iomem *base = data->chip_data; in mbigen_eoi_irq() local
111 writel_relaxed(mask, base + addr); in mbigen_eoi_irq()
118 void __iomem *base = data->chip_data; in mbigen_set_type() local
126 val = readl_relaxed(base + addr); in mbigen_set_type()
133 writel_relaxed(val, base + addr); in mbigen_set_type()
150 void __iomem *base = d->chip_data; in mbigen_write_msg() local
156 base += get_mbigen_vec_reg(d->hwirq); in mbigen_write_msg()
157 val = readl_relaxed(base); in mbigen_write_msg()
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H A Dirq-mvebu-icu.c53 void __iomem *base; member
81 writel_relaxed(msg[0].address_hi, icu->base + subset->offset_set_ah); in mvebu_icu_init()
82 writel_relaxed(msg[0].address_lo, icu->base + subset->offset_set_al); in mvebu_icu_init()
88 writel_relaxed(msg[1].address_hi, icu->base + subset->offset_clr_ah); in mvebu_icu_init()
89 writel_relaxed(msg[1].address_lo, icu->base + subset->offset_clr_al); in mvebu_icu_init()
113 writel_relaxed(icu_int, icu->base + ICU_INT_CFG(d->hwirq)); in mvebu_icu_write_msg()
126 icu->base + ICU_INT_CFG(ICU_SATA0_ICU_ID)); in mvebu_icu_write_msg()
128 icu->base + ICU_INT_CFG(ICU_SATA1_ICU_ID)); in mvebu_icu_write_msg()
359 icu->base = devm_platform_ioremap_resource(pdev, 0); in mvebu_icu_probe()
360 if (IS_ERR(icu->base)) in mvebu_icu_probe()
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/kernel/linux/linux-6.6/drivers/mailbox/
H A Darm_mhu_db.c39 void __iomem *base; member
78 void __iomem *base = chan_info->mhu->mlink[chan_info->pchan].rx_reg; in mhu_db_mbox_clear_irq() local
80 writel_relaxed(BIT(chan_info->doorbell), base + INTR_CLR_OFS); in mhu_db_mbox_clear_irq()
100 void __iomem *base = mhu->mlink[pchan].rx_reg; in mhu_db_mbox_irq_to_channel() local
102 bits = readl_relaxed(base + INTR_STAT_OFS); in mhu_db_mbox_irq_to_channel()
140 void __iomem *base = chan_info->mhu->mlink[chan_info->pchan].tx_reg; in mhu_db_last_tx_done() local
142 if (readl_relaxed(base + INTR_STAT_OFS) & BIT(chan_info->doorbell)) in mhu_db_last_tx_done()
151 void __iomem *base = chan_info->mhu->mlink[chan_info->pchan].tx_reg; in mhu_db_send_data() local
154 writel_relaxed(BIT(chan_info->doorbell), base + INTR_SET_OFS); in mhu_db_send_data()
279 mhu->base in mhu_db_probe()
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/kernel/linux/linux-6.6/drivers/scsi/aic7xxx/
H A Daic79xx_osm_pci.c232 ahd_linux_pci_reserve_io_regions(struct ahd_softc *ahd, resource_size_t *base, in ahd_linux_pci_reserve_io_regions() argument
235 *base = pci_resource_start(ahd->dev_softc, 0); in ahd_linux_pci_reserve_io_regions()
242 if (*base == 0 || *base2 == 0) in ahd_linux_pci_reserve_io_regions()
244 if (!request_region(*base, 256, "aic79xx")) in ahd_linux_pci_reserve_io_regions()
247 release_region(*base, 256); in ahd_linux_pci_reserve_io_regions()
293 resource_size_t base; in ahd_pci_map_registers() local
302 base = 0; in ahd_pci_map_registers()
304 error = ahd_linux_pci_reserve_mem_region(ahd, &base, &maddr); in ahd_pci_map_registers()
306 ahd->platform_data->mem_busaddr = base; in ahd_pci_map_registers()
334 (unsigned long long)base); in ahd_pci_map_registers()
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/third_party/node/deps/v8/src/heap/
H A Dgc-tracer.h9 #include "src/base/compiler-specific.h"
10 #include "src/base/macros.h"
11 #include "src/base/optional.h"
12 #include "src/base/ring-buffer.h"
116 base::Optional<WorkerThreadRuntimeCallStatsScope> runtime_call_stats_scope_;
440 static double AverageSpeed(const base::RingBuffer<BytesAndDuration>& buffer);
441 static double AverageSpeed(const base::RingBuffer<BytesAndDuration>& buffer,
541 base::RingBuffer<BytesAndDuration> recorded_minor_gcs_total_;
542 base::RingBuffer<BytesAndDuration> recorded_minor_gcs_survived_;
543 base
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/third_party/node/deps/v8/src/snapshot/
H A Dmksnapshot.cc13 #include "src/base/platform/platform.h"
14 #include "src/base/platform/wrappers.h"
15 #include "src/base/sanitizer/msan.h"
16 #include "src/base/vector.h"
42 v8::base::Vector<const i::byte> blob_vector( in WriteSnapshot()
50 const v8::base::Vector<const i::byte>& blob) const { in MaybeWriteStartupBlob()
55 v8::base::Fclose(fp); in MaybeWriteStartupBlob()
64 const v8::base::Vector<const i::byte>& blob) const { in MaybeWriteSnapshotFile()
73 v8::base::Fclose(fp); in MaybeWriteSnapshotFile()
79 fprintf(fp, "#include \"src/base/platfor in WriteSnapshotFilePrefix()
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/third_party/node/deps/v8/src/torque/
H A Dcfg.h27 base::Optional<Stack<const Type*>> input_types, in Block()
38 bool HasInputTypes() const { return input_types_ != base::nullopt; } in HasInputTypes()
78 return input_definitions_ != base::nullopt; in HasInputDefinitions()
90 base::Optional<Stack<const Type*>> input_types_;
91 base::Optional<Stack<DefinitionLocation>> input_definitions_;
103 Block* NewBlock(base::Optional<Stack<const Type*>> input_types, in NewBlock()
117 base::Optional<Block*> end() const { return end_; } in end()
143 base::Optional<Block*> end_;
144 base::Optional<TypeVector> return_type_;
164 base in NewBlock()
163 NewBlock( base::Optional<Stack<const Type*>> input_types = base::nullopt, bool is_deferred = false) NewBlock() argument
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/third_party/mesa3d/src/gallium/drivers/freedreno/a6xx/
H A Dfd6_context.c65 fd_context_cleanup_common_vbos(&fd6_ctx->base);
79 memcpy(state->base.pipe, elements, sizeof(*elements) * num_elements); in fd6_vertex_state_create()
80 state->base.num_elements = num_elements; in fd6_vertex_state_create()
211 pctx = &fd6_ctx->base.base;
214 fd6_ctx->base.flags = flags;
215 fd6_ctx->base.dev = fd_device_ref(screen->dev);
216 fd6_ctx->base.screen = fd_screen(pscreen);
217 fd6_ctx->base.last.key = &fd6_ctx->last_key;
233 setup_state_map(&fd6_ctx->base);
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/third_party/wpa_supplicant/wpa_supplicant-2.9/src/wps/
H A Dhttp_client.c317 char * http_link_update(char *url, const char *base) in http_link_update() argument
332 if (os_strncmp(base, "http://", 7) != 0) in http_link_update()
333 return url; /* unable to handle base URL */ in http_link_update()
335 len = os_strlen(url) + 1 + os_strlen(base) + 1; in http_link_update()
341 pos = os_strchr(base + 7, '/'); in http_link_update()
343 os_snprintf(n, len, "%s%s", base, url); in http_link_update()
345 os_memcpy(n, base, pos - base); in http_link_update()
346 os_memcpy(n + (pos - base), url, os_strlen(url) + 1); in http_link_update()
349 pos = os_strrchr(base in http_link_update()
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/third_party/wpa_supplicant/wpa_supplicant-2.9_standard/src/wps/
H A Dhttp_client.c317 char * http_link_update(char *url, const char *base) in http_link_update() argument
332 if (os_strncmp(base, "http://", 7) != 0) in http_link_update()
333 return url; /* unable to handle base URL */ in http_link_update()
335 len = os_strlen(url) + 1 + os_strlen(base) + 1; in http_link_update()
341 pos = os_strchr(base + 7, '/'); in http_link_update()
343 os_snprintf(n, len, "%s%s", base, url); in http_link_update()
345 os_memcpy(n, base, pos - base); in http_link_update()
346 os_memcpy(n + (pos - base), url, os_strlen(url) + 1); in http_link_update()
349 pos = os_strrchr(base in http_link_update()
[all...]
/kernel/linux/linux-5.10/drivers/dma/
H A Dk3dma.c93 void __iomem *base; member
101 void __iomem *base; member
139 val = readl_relaxed(phy->base + CX_CFG); in k3_dma_pause_dma()
141 writel_relaxed(val, phy->base + CX_CFG); in k3_dma_pause_dma()
143 val = readl_relaxed(phy->base + CX_CFG); in k3_dma_pause_dma()
145 writel_relaxed(val, phy->base + CX_CFG); in k3_dma_pause_dma()
156 writel_relaxed(val, d->base + INT_TC1_RAW); in k3_dma_terminate_chan()
157 writel_relaxed(val, d->base + INT_TC2_RAW); in k3_dma_terminate_chan()
158 writel_relaxed(val, d->base + INT_ERR1_RAW); in k3_dma_terminate_chan()
159 writel_relaxed(val, d->base in k3_dma_terminate_chan()
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/kernel/linux/linux-5.10/drivers/gpu/drm/
H A Ddrm_atomic_uapi.c91 mode->name, crtc->base.id, crtc->name, state); in drm_atomic_set_mode_for_crtc()
96 crtc->base.id, crtc->name, state); in drm_atomic_set_mode_for_crtc()
134 crtc->base.id, crtc->name, in drm_atomic_set_mode_prop_for_crtc()
143 crtc->base.id, crtc->name, in drm_atomic_set_mode_prop_for_crtc()
152 state->mode.name, crtc->base.id, crtc->name, in drm_atomic_set_mode_prop_for_crtc()
157 crtc->base.id, crtc->name, state); in drm_atomic_set_mode_prop_for_crtc()
208 plane->base.id, plane->name, plane_state, in drm_atomic_set_crtc_for_plane()
209 crtc->base.id, crtc->name); in drm_atomic_set_crtc_for_plane()
212 plane->base.id, plane->name, plane_state); in drm_atomic_set_crtc_for_plane()
236 fb->base in drm_atomic_set_fb_for_plane()
[all...]
/kernel/linux/linux-6.6/drivers/spi/
H A Dspi-geni-qcom.c110 writel(SPI_SLAVE_EN, se->base + SE_SPI_SLAVE_EN); in spi_slv_setup()
111 writel(GENI_IO_MUX_0_EN, se->base + GENI_OUTPUT_CTRL); in spi_slv_setup()
112 writel(START_TRIGGER, se->base + SE_GENI_CFG_SEQ_START); in spi_slv_setup()
158 writel(0, se->base + SE_GENI_TX_WATERMARK_REG); in handle_se_timeout()
202 writel(1, se->base + SE_DMA_TX_FSM_RST); in handle_se_timeout()
211 writel(1, se->base + SE_DMA_RX_FSM_RST); in handle_se_timeout()
268 m_irq = readl(se->base + SE_GENI_M_IRQ_STATUS); in spi_geni_is_abort_still_pending()
269 m_irq_en = readl(se->base + SE_GENI_M_IRQ_EN); in spi_geni_is_abort_still_pending()
355 writel(word_len, se->base + SE_SPI_WORD_LEN); in spi_setup_word_len()
385 writel(clk_sel, se->base in geni_spi_set_clock_and_bw()
1047 void __iomem *base; spi_geni_probe() local
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dml/dcn30/
H A Ddcn30_fpu.c40 optc1->base.ctx
728 void dcn3_fpu_build_wm_range_table(struct clk_mgr *base) in dcn3_fpu_build_wm_range_table() argument
731 double pstate_latency_us = base->ctx->dc->dml.soc.dram_clock_change_latency_us; in dcn3_fpu_build_wm_range_table()
732 double sr_exit_time_us = base->ctx->dc->dml.soc.sr_exit_time_us; in dcn3_fpu_build_wm_range_table()
733 double sr_enter_plus_exit_time_us = base->ctx->dc->dml.soc.sr_enter_plus_exit_time_us; in dcn3_fpu_build_wm_range_table()
734 uint16_t min_uclk_mhz = base->bw_params->clk_table.entries[0].memclk_mhz; in dcn3_fpu_build_wm_range_table()
739 base->bw_params->wm_table.nv_entries[WM_A].valid = true; in dcn3_fpu_build_wm_range_table()
740 base->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us = pstate_latency_us; in dcn3_fpu_build_wm_range_table()
741 base->bw_params->wm_table.nv_entries[WM_A].dml_input.sr_exit_time_us = sr_exit_time_us; in dcn3_fpu_build_wm_range_table()
742 base in dcn3_fpu_build_wm_range_table()
[all...]
/kernel/linux/linux-6.6/drivers/dma/
H A Dk3dma.c93 void __iomem *base; member
101 void __iomem *base; member
139 val = readl_relaxed(phy->base + CX_CFG); in k3_dma_pause_dma()
141 writel_relaxed(val, phy->base + CX_CFG); in k3_dma_pause_dma()
143 val = readl_relaxed(phy->base + CX_CFG); in k3_dma_pause_dma()
145 writel_relaxed(val, phy->base + CX_CFG); in k3_dma_pause_dma()
156 writel_relaxed(val, d->base + INT_TC1_RAW); in k3_dma_terminate_chan()
157 writel_relaxed(val, d->base + INT_TC2_RAW); in k3_dma_terminate_chan()
158 writel_relaxed(val, d->base + INT_ERR1_RAW); in k3_dma_terminate_chan()
159 writel_relaxed(val, d->base in k3_dma_terminate_chan()
[all...]
/third_party/mesa3d/src/gallium/drivers/nouveau/nv50/
H A Dnv50_vbo.c145 struct nouveau_pushbuf *push = nv50->base.pushbuf; in nv50_emit_vtxattr()
189 uint32_t *base, uint32_t *size) in nv50_user_vbuf_range()
194 *base = nv50->instance_off * nv50->vtxbuf[vbi].stride; in nv50_user_vbuf_range()
200 *base = nv50->vb_elt_first * nv50->vtxbuf[vbi].stride; in nv50_user_vbuf_range()
216 uint32_t base, size; in nv50_upload_user_buffers() local
220 nv50_user_vbuf_range(nv50, b, &base, &size); in nv50_upload_user_buffers()
222 limits[b] = base + size - 1; in nv50_upload_user_buffers()
223 addrs[b] = nouveau_scratch_data(&nv50->base, vb->buffer.user, base, size, in nv50_upload_user_buffers()
229 nv50->base in nv50_upload_user_buffers()
188 nv50_user_vbuf_range(struct nv50_context *nv50, unsigned vbi, uint32_t *base, uint32_t *size) nv50_user_vbuf_range() argument
244 uint32_t base, size; nv50_update_user_vbufs() local
615 const unsigned base = buf->offset & ~3; nv50_draw_elements() local
[all...]
/third_party/node/deps/v8/src/diagnostics/mips64/
H A Ddisasm-mips64.cc14 // v8::base::EmbeddedVector<char, 256> buffer;
32 #include "src/base/platform/platform.h"
33 #include "src/base/strings.h"
34 #include "src/base/vector.h"
50 v8::base::Vector<char> out_buffer) in Decoder()
168 v8::base::Vector<char> out_buffer_;
257 out_buffer_pos_ += base::SNPrintF(out_buffer_ + out_buffer_pos_, "%d", sa); in PrintSa()
263 out_buffer_pos_ += base::SNPrintF(out_buffer_ + out_buffer_pos_, "%d", sa); in PrintLsaSa()
269 out_buffer_pos_ += base::SNPrintF(out_buffer_ + out_buffer_pos_, "%d", sd); in PrintSd()
276 base in PrintSs1()
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/third_party/mesa3d/src/gallium/drivers/d3d12/
H A Dd3d12_video_enc.cpp63 debug_printf("[d3d12_video_encoder] d3d12_video_encoder_flush - Flushing pD3D12Enc->base.context and GPU sync between Video/Context queues before flushing Video Encode Queue.\n"); in d3d12_video_encoder_flush()
64 pD3D12Enc->base.context->flush(pD3D12Enc->base.context, &completion_fence, PIPE_FLUSH_ASYNC | PIPE_FLUSH_HINT_FINISH); in d3d12_video_encoder_flush()
68 pD3D12Enc->m_pD3D12Screen->base.fence_reference(&pD3D12Enc->m_pD3D12Screen->base, &completion_fence, NULL); in d3d12_video_encoder_flush()
178 enum pipe_video_format codec = u_reduce_video_profile(pD3D12Enc->base.profile); in d3d12_video_encoder_update_picparams_tracking()
398 enum pipe_video_format codec = u_reduce_video_profile(pD3D12Enc->base.profile);
428 enum pipe_video_format codec = u_reduce_video_profile(pD3D12Enc->base.profile);
452 enum pipe_video_format codec = u_reduce_video_profile(pD3D12Enc->base.profile);
523 enum pipe_video_format codec = u_reduce_video_profile(pD3D12Enc->base
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/kernel/linux/linux-5.10/drivers/crypto/stm32/
H A Dstm32-cryp.c1073 base); in stm32_cryp_prepare_cipher_req()
1082 base); in stm32_cryp_cipher_one_req()
1096 base); in stm32_cryp_prepare_aead_req()
1104 base); in stm32_cryp_aead_one_req()
1545 .base.cra_name = "ecb(aes)",
1546 .base.cra_driver_name = "stm32-ecb-aes",
1547 .base.cra_priority = 200,
1548 .base.cra_flags = CRYPTO_ALG_ASYNC,
1549 .base.cra_blocksize = AES_BLOCK_SIZE,
1550 .base
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/kernel/linux/linux-6.6/drivers/crypto/marvell/octeontx2/
H A Dotx2_cptvf_algs.c88 req = container_of(cpt_req->areq, struct aead_request, base); in validate_hmac_cipher_null()
135 sreq = container_of(areq, struct skcipher_request, base); in output_iv_copyback()
230 flags = (req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP) ? in create_ctx_hdr()
335 req->base.flags, in skcipher_do_fallback()
336 req->base.complete, in skcipher_do_fallback()
337 req->base.data); in skcipher_do_fallback()
381 req_info->areq = &req->base; in cpt_enc_dec()
1269 aead_request_set_callback(&rctx->fbk_req, req->base.flags, in aead_do_fallback()
1270 req->base.complete, req->base in aead_do_fallback()
[all...]
/third_party/mesa3d/src/gallium/drivers/panfrost/
H A Dpan_cmdstream.c53 struct pipe_rasterizer_state base; member
63 struct pipe_depth_stencil_alpha_state base; member
88 struct pipe_sampler_state base; member
95 struct pipe_sampler_view base; member
212 so->base = *cso; in panfrost_create_sampler_state()
270 if (PAN_ARCH <= 5 && zsa->base.alpha_func != PIPE_FUNC_ALWAYS) in panfrost_fs_required()
351 bool dithered = so->base.dither; in panfrost_emit_blend()
379 cfg.alpha_to_one = ctx->blend->base.alpha_to_one; in panfrost_emit_blend()
400 const struct panfrost_device *dev = pan_device(ctx->base.screen); in panfrost_emit_blend()
464 bool alpha_to_coverage = ctx->blend->base in pan_allow_forward_pixel_to_kill()
1433 panfrost_emit_ubo(void *base, unsigned index, mali_ptr address, size_t size) panfrost_emit_ubo() argument
[all...]
/kernel/linux/linux-6.6/drivers/hid/
H A Dhid-playstation.c147 struct ps_device base; member
360 struct ps_device base; member
947 struct hid_device *hdev = ds->base.hdev; in dualsense_get_calibration_data()
965 ret = ps_get_report(ds->base.hdev, DS_FEATURE_REPORT_CALIBRATION, buf, in dualsense_get_calibration_data()
968 hid_err(ds->base.hdev, "Failed to retrieve DualSense calibration info: %d\n", ret); in dualsense_get_calibration_data()
1080 ret = ps_get_report(ds->base.hdev, DS_FEATURE_REPORT_FIRMWARE_INFO, buf, in dualsense_get_firmware_info()
1083 hid_err(ds->base.hdev, "Failed to retrieve DualSense firmware info: %d\n", ret); in dualsense_get_firmware_info()
1087 ds->base.hw_version = get_unaligned_le32(&buf[24]); in dualsense_get_firmware_info()
1088 ds->base.fw_version = get_unaligned_le32(&buf[28]); in dualsense_get_firmware_info()
1113 ret = ps_get_report(ds->base in dualsense_get_mac_address()
[all...]
/kernel/linux/linux-5.10/drivers/gpio/
H A Dgpio-intel-mid.c276 u32 base, gpio, mask; in intel_mid_irq_handler() local
281 for (base = 0; base < priv->chip.ngpio; base += 32) { in intel_mid_irq_handler()
282 gedr = gpio_reg(&priv->chip, base, GEDR); in intel_mid_irq_handler()
289 base + gpio)); in intel_mid_irq_handler()
300 unsigned base; in intel_mid_irq_init_hw() local
302 for (base = 0; base < priv->chip.ngpio; base in intel_mid_irq_init_hw()
330 void __iomem *base; intel_gpio_probe() local
[all...]

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