Lines Matching refs:base
53 struct pipe_rasterizer_state base;
63 struct pipe_depth_stencil_alpha_state base;
88 struct pipe_sampler_state base;
95 struct pipe_sampler_view base;
212 so->base = *cso;
270 if (PAN_ARCH <= 5 && zsa->base.alpha_func != PIPE_FUNC_ALWAYS)
351 bool dithered = so->base.dither;
379 cfg.alpha_to_one = ctx->blend->base.alpha_to_one;
400 const struct panfrost_device *dev = pan_device(ctx->base.screen);
464 bool alpha_to_coverage = ctx->blend->base.alpha_to_coverage;
518 struct pipe_rasterizer_state *rast = &ctx->rasterizer->base;
522 bool alpha_to_coverage = ctx->blend->base.alpha_to_coverage;
541 ctx->blend->base.alpha_to_coverage,
552 ((enum mali_func) zsa->base.alpha_func == MALI_FUNC_ALWAYS);
577 cfg.stencil_mask_misc.dither_disable = !so->base.dither;
578 cfg.stencil_mask_misc.alpha_to_one = so->base.alpha_to_one;
634 bool back_enab = zsa->base.stencil[1].enabled;
640 cfg.alpha_reference = zsa->base.alpha_ref_value;
704 xfer = pan_pool_alloc_desc(&batch->pool.base, RENDERER_STATE);
708 xfer = pan_pool_alloc_desc_aggregate(&batch->pool.base,
732 const struct pipe_rasterizer_state *rast = &ctx->rasterizer->base;
774 struct panfrost_ptr T = pan_pool_alloc_desc(&batch->pool.base, VIEWPORT);
814 bool back_enab = zsa->base.stencil[1].enabled;
816 struct panfrost_ptr T = pan_pool_alloc_desc(&batch->pool.base, DEPTH_STENCIL);
826 cfg.depth_bias_enable = rast->base.offset_tri;
827 cfg.depth_units = rast->base.offset_units * 2.0f;
828 cfg.depth_factor = rast->base.offset_scale;
829 cfg.depth_bias_clamp = rast->base.offset_clamp;
847 struct panfrost_ptr T = pan_pool_alloc_desc_array(&batch->pool.base, rt_count, BLEND);
873 struct panfrost_ptr T = pan_pool_alloc_desc_array(&batch->pool.base,
907 struct panfrost_ptr T = pan_pool_alloc_desc_array(&batch->pool.base,
972 pan_pool_alloc_desc_array(&batch->pool.base, last_bit, TEXTURE);
991 .base = panfrost_pipe_image_to_sampler_view(image),
1001 if (view.base.target == PIPE_BUFFER)
1002 view.base.target = PIPE_BUFFER;
1004 view.base.target = PIPE_TEXTURE_2D_ARRAY;
1006 panfrost_update_sampler_view(&view, &ctx->base);
1032 return pan_pool_upload_aligned(&batch->pool.base,
1083 struct pipe_sampler_view *tex = &ctx->sampler_views[st][texidx]->base;
1170 util_range_add(&rsrc->base, &rsrc->valid_buffer_range,
1185 struct pipe_sampler_state *sampl = &ctx->samplers[st][samp_idx]->base;
1240 struct panfrost_device *dev = pan_device(ctx->base.screen);
1260 struct panfrost_device *dev = pan_device(ctx->base.screen);
1333 util_range_add(&rsrc->base, &rsrc->valid_buffer_range,
1433 panfrost_emit_ubo(void *base, unsigned index, mali_ptr address, size_t size)
1436 struct mali_buffer_packed *out = base;
1443 struct mali_uniform_buffer_packed *out = base;
1475 pan_pool_alloc_aligned(&batch->pool.base, sys_size, 16);
1487 ubos = pan_pool_alloc_desc_array(&batch->pool.base,
1491 ubos = pan_pool_alloc_desc_array(&batch->pool.base,
1526 pan_pool_alloc_aligned(&batch->pool.base,
1589 struct panfrost_device *dev = pan_device(ctx->base.screen);
1593 pan_pool_alloc_desc(&batch->pool.base, LOCAL_STORAGE);
1637 struct pipe_sampler_view *pview = &view->base;
1655 enum pipe_format format = so->base.format;
1661 texture = &prsrc->separate_stencil->base;
1686 so->base.target == PIPE_TEXTURE_2D ||
1687 so->base.target == PIPE_TEXTURE_2D_ARRAY);
1690 panfrost_translate_texture_dimension(so->base.target);
1692 bool is_buffer = (so->base.target == PIPE_BUFFER);
1694 unsigned first_level = is_buffer ? 0 : so->base.u.tex.first_level;
1695 unsigned last_level = is_buffer ? 0 : so->base.u.tex.last_level;
1696 unsigned first_layer = is_buffer ? 0 : so->base.u.tex.first_layer;
1697 unsigned last_layer = is_buffer ? 0 : so->base.u.tex.last_layer;
1698 unsigned buf_offset = is_buffer ? so->base.u.buf.offset : 0;
1699 unsigned buf_size = (is_buffer ? so->base.u.buf.size : 0) /
1702 if (so->base.target == PIPE_TEXTURE_3D) {
1716 so->base.swizzle_r,
1717 so->base.swizzle_g,
1718 so->base.swizzle_b,
1719 so->base.swizzle_a,
1732 struct panfrost_ptr payload = pan_pool_alloc_aligned(&pool->base, size, 64);
1749 struct panfrost_resource *rsrc = pan_resource(view->base.texture);
1753 panfrost_create_sampler_view_bo(view, pctx, &rsrc->base);
1768 pan_pool_alloc_desc_array(&batch->pool.base,
1782 struct pipe_sampler_view *pview = &view->base;
1785 panfrost_update_sampler_view(view, &ctx->base);
1804 panfrost_update_sampler_view(view, &ctx->base);
1809 return pan_pool_upload_aligned(&batch->pool.base, trampolines,
1826 pan_pool_alloc_desc_array(&batch->pool.base,
1848 struct panfrost_device *dev = pan_device(ctx->base.screen);
1900 bool is_3d = rsrc->base.target == PIPE_TEXTURE_3D;
1901 bool is_buffer = rsrc->base.target == PIPE_BUFFER;
1920 cfg.s_dimension = rsrc->base.width0 /
1931 cfg.s_dimension = u_minify(rsrc->base.width0, level);
1932 cfg.t_dimension = u_minify(rsrc->base.height0, level);
1934 u_minify(rsrc->base.depth0, level) :
1940 if (rsrc->base.target != PIPE_TEXTURE_2D) {
1967 pan_pool_alloc_desc_array(&batch->pool.base, buf_count, ATTRIBUTE_BUFFER);
1970 pan_pool_alloc_desc_array(&batch->pool.base, attr_count, ATTRIBUTE);
2023 pan_pool_alloc_desc_array(&batch->pool.base, nr_bufs,
2026 pan_pool_alloc_desc_array(&batch->pool.base, count,
2059 /* Since we advanced the base pointer, we shrink the buffer
2061 unsigned size = rsrc->base.width0 + (raw_addr - addr)
2187 * base' = base & ~63 = base - (base & 63)
2188 * offset' = offset + (base & 63)
2190 * Since base' + offset' = base + offset, these are equivalent
2191 * addressing modes and now base is 64 aligned.
2238 pan_pool_alloc_aligned(&batch->invisible_pool.base, size, 64).gpu;
2450 struct panfrost_device *dev = pool->base.dev;
2461 pan_pool_alloc_desc_array(&pool->base,
2554 point_coord_mask = ctx->rasterizer->base.sprite_coord_enable;
2578 pan_pool_alloc_desc_array(&batch->pool.base,
2644 unsigned vertex = panfrost_add_job(&batch->pool.base, &batch->scoreboard,
2650 panfrost_add_job(&batch->pool.base, &batch->scoreboard,
2659 struct panfrost_device *dev = pan_device(batch->ctx->base.screen);
2686 struct panfrost_device *dev = pan_device(batch->ctx->base.screen);
2755 pan_pool_alloc_desc(&batch->pool.base, FRAGMENT_JOB);
2901 rast->base.point_size :
2902 rast->base.line_width;
3026 struct panfrost_device *dev = pan_device(batch->ctx->base.screen);
3035 pan_pool_alloc_desc(&batch->pool.base, TILER_HEAP);
3041 t = pan_pool_alloc_desc(&batch->pool.base, TILER_CONTEXT);
3061 UNUSED struct pipe_rasterizer_state *rast = &ctx->rasterizer->base;
3145 T = pan_pool_alloc_aligned(&batch->pool.base, nr_tables * pan_size(RESOURCE), 64);
3207 struct pipe_rasterizer_state *rast = &ctx->rasterizer->base;
3266 ctx->blend->base.alpha_to_coverage,
3297 ctx->blend->base.alpha_to_coverage;
3306 cfg.alpha_to_coverage = ctx->blend->base.alpha_to_coverage;
3501 pan_pool_alloc_desc(&batch->pool.base, COMPUTE_JOB);
3569 panfrost_add_job(&batch->pool.base, &batch->scoreboard, job_type,
3620 tiler = pan_pool_alloc_desc(&batch->pool.base, MALLOC_VERTEX_JOB);
3622 tiler = pan_pool_alloc_desc(&batch->pool.base, INDEXED_VERTEX_JOB);
3627 vertex = pan_pool_alloc_desc(&batch->pool.base, COMPUTE_JOB);
3628 tiler = pan_pool_alloc_desc(&batch->pool.base, TILER_JOB);
3726 panfrost_add_job(&batch->pool.base, &batch->scoreboard,
3741 panfrost_add_job(&batch->pool.base, &batch->scoreboard,
3765 struct panfrost_device *dev = pan_device(ctx->base.screen);
3784 tiler = pan_pool_alloc_desc(&batch->pool.base, INDEXED_VERTEX_JOB);
3789 vertex = pan_pool_alloc_desc(&batch->pool.base, COMPUTE_JOB);
3790 tiler = pan_pool_alloc_desc(&batch->pool.base, TILER_JOB);
3811 /* Set the {first,base}_vertex sysvals to NULL. Will be updated if the
3902 GENX(panfrost_emit_indirect_draw)(&batch->pool.base,
3908 panfrost_add_job(&batch->pool.base, &batch->scoreboard,
3926 struct pipe_rasterizer_state *rast = &ctx->rasterizer->base;
4074 pan_pool_alloc_desc(&batch->pool.base, COMPUTE_JOB);
4155 indirect_dep = GENX(pan_indirect_dispatch_emit)(&batch->pool.base,
4161 panfrost_add_job(&batch->pool.base, &batch->scoreboard,
4174 so->base = *cso;
4330 so->base = *zsa;
4341 so->base.alpha_func = MALI_FUNC_ALWAYS;
4358 (enum mali_func) so->base.alpha_func;
4413 so->base = *template;
4414 so->base.texture = texture;
4415 so->base.reference.count = 1;
4416 so->base.context = pctx;
4456 so->base = *blend;
4532 pan_pool_alloc_desc(&pool->base, RENDERER_STATE);
4557 struct panfrost_ptr ptr = pan_pool_alloc_desc_array(&pool->base,
4629 GENX(pan_preload_fb)(&batch->pool.base, &batch->scoreboard, fb, batch->tls.gpu,
4639 pan_pool_alloc_desc(&batch->pool.base, FRAMEBUFFER);
4641 pan_pool_alloc_desc_aggregate(&batch->pool.base,
4650 batch->tls = pan_pool_alloc_desc(&batch->pool.base, LOCAL_STORAGE);
4695 struct panfrost_device *dev = pan_device(batch->ctx->base.screen);
4740 panfrost_scoreboard_initialize_tiler(&batch->pool.base,
4764 GENX(pan_blitter_init)(dev, &screen->blitter.bin_pool.base,
4765 &screen->blitter.desc_pool.base);
4768 GENX(panfrost_init_indirect_draw_shaders)(dev, &screen->indirect_draw.bin_pool.base);