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/third_party/mesa3d/src/gallium/drivers/lima/
H A Dlima_draw.c60 if (ctx->rasterizer && ctx->rasterizer->base.scissor) { in lima_clip_scissor_to_viewport()
68 cscissor->maxx = fb->base.width; in lima_clip_scissor_to_viewport()
70 cscissor->maxy = fb->base.height; in lima_clip_scissor_to_viewport()
75 viewport_right = MIN2(MAX2(ctx->viewport.right, 0), fb->base.width); in lima_clip_scissor_to_viewport()
82 viewport_top = MIN2(MAX2(ctx->viewport.top, 0), fb->base.height); in lima_clip_scissor_to_viewport()
103 float line_width = ctx->rasterizer->base.line_width; in lima_extend_viewport()
129 if (fb->base.nr_cbufs && (buffers & PIPE_CLEAR_COLOR0) && in lima_update_job_wb()
131 struct lima_resource *res = lima_resource(fb->base.cbufs[0]->texture); in lima_update_job_wb()
133 _mesa_hash_table_insert(ctx->write_jobs, &res->base, job); in lima_update_job_wb()
138 if (fb->base in lima_update_job_wb()
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/kernel/linux/linux-5.10/drivers/gpu/drm/i915/display/
H A Dintel_hdmi.c62 return hdmi_to_dig_port(intel_hdmi)->base.base.dev; in intel_hdmi_to_dev()
92 container_of(&encoder->base, struct intel_digital_port, in enc_to_intel_hdmi()
93 base.base); in enc_to_intel_hdmi()
218 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in g4x_write_infoframe()
253 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in g4x_read_infoframe()
271 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in g4x_infoframes_enabled()
290 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in ibx_write_infoframe()
328 struct drm_i915_private *dev_priv = to_i915(encoder->base in ibx_read_infoframe()
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H A Dintel_sdvo.c78 struct intel_encoder base; member
128 struct intel_connector base; member
169 /* base.base: tv.saturation/contrast/hue/brightness */
170 struct intel_digital_connector_state base; member
181 return container_of(encoder, struct intel_sdvo, base); in to_sdvo()
192 return container_of(connector, struct intel_sdvo_connector, base.base); in to_intel_sdvo_connector()
196 container_of((conn_state), struct intel_sdvo_connector_state, base.base)
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/kernel/linux/linux-6.6/drivers/gpu/drm/i915/display/
H A Dintel_sdvo.c83 struct intel_encoder base; member
130 struct intel_connector base; member
171 /* base.base: tv.saturation/contrast/hue/brightness */
172 struct intel_digital_connector_state base; member
183 return container_of(encoder, struct intel_sdvo, base); in to_sdvo()
194 return container_of(connector, struct intel_sdvo_connector, base.base); in to_intel_sdvo_connector()
198 container_of((conn_state), struct intel_sdvo_connector_state, base.base)
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/foundation/graphic/graphic_3d/lume/metaobject/include/meta/interface/
H A Dintf_clock.h23 #include <meta/base/interface_macros.h>
24 #include <meta/base/namespace.h>
25 #include <meta/base/shared_ptr.h>
26 #include <meta/base/time_span.h>
27 #include <meta/base/types.h>
/kernel/linux/linux-5.10/arch/mips/loongson2ef/common/
H A Dinit.c16 /* Loongson CPU address windows config space base address */
21 void *base; in mips_nmi_setup() local
24 base = (void *)(CAC_BASE + 0x380); in mips_nmi_setup()
25 memcpy(base, except_vec_nmi, 0x80); in mips_nmi_setup()
26 flush_icache_range((unsigned long)base, (unsigned long)base + 0x80); in mips_nmi_setup()
40 /* init base address of io space */ in prom_init()
45 /*init the uart base address */ in prom_init()
/kernel/linux/linux-6.6/arch/mips/loongson2ef/common/
H A Dinit.c16 /* Loongson CPU address windows config space base address */
21 void *base; in mips_nmi_setup() local
23 base = (void *)(CAC_BASE + 0x380); in mips_nmi_setup()
24 memcpy(base, except_vec_nmi, 0x80); in mips_nmi_setup()
25 flush_icache_range((unsigned long)base, (unsigned long)base + 0x80); in mips_nmi_setup()
39 /* init base address of io space */ in prom_init()
44 /*init the uart base address */ in prom_init()
/third_party/python/Lib/ctypes/test/
H A Dtest_repr.py5 for base in [c_byte, c_short, c_int, c_long, c_longlong,
8 class X(base):
20 base = typ.__bases__[0]
21 self.assertTrue(repr(base(42)).startswith(base.__name__))
/kernel/linux/linux-5.10/arch/sparc/crypto/
H A Dcamellia_glue.c218 .base.cra_name = "ecb(camellia)",
219 .base.cra_driver_name = "ecb-camellia-sparc64",
220 .base.cra_priority = SPARC_CR_OPCODE_PRIORITY,
221 .base.cra_blocksize = CAMELLIA_BLOCK_SIZE,
222 .base.cra_ctxsize = sizeof(struct camellia_sparc64_ctx),
223 .base.cra_alignmask = 7,
224 .base.cra_module = THIS_MODULE,
231 .base.cra_name = "cbc(camellia)",
232 .base.cra_driver_name = "cbc-camellia-sparc64",
233 .base
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/kernel/linux/linux-5.10/arch/arm/mm/
H A Dpmsa-v7.c20 phys_addr_t base; member
66 /* Region base address register */
90 /* I-side Region base address register */
126 /* Region base address register */
146 static bool __init try_split_region(phys_addr_t base, phys_addr_t size, struct region *region) in try_split_region() argument
149 phys_addr_t abase = base & ~(size - 1); in try_split_region()
150 phys_addr_t asize = base + size - abase; in try_split_region()
157 bdiff = base - abase; in try_split_region()
183 region->base = abase; in try_split_region()
189 static int __init allocate_region(phys_addr_t base, phys_addr_ argument
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/kernel/linux/linux-5.10/drivers/clk/renesas/
H A Drcar-gen2-cpg.c138 void __iomem *base) in cpg_z_clk_register()
154 zclk->reg = base + CPG_FRQCRC; in cpg_z_clk_register()
155 zclk->kick_reg = base + CPG_FRQCRB; in cpg_z_clk_register()
167 void __iomem *base) in cpg_rcan_clk_register()
186 gate->reg = base + CPG_RCANCKCR; in cpg_rcan_clk_register()
211 void __iomem *base) in cpg_adsp_clk_register()
221 div->reg = base + CPG_ADSPCKCR; in cpg_adsp_clk_register()
232 gate->reg = base + CPG_ADSPCKCR; in cpg_adsp_clk_register()
278 struct clk **clks, void __iomem *base, in rcar_gen2_cpg_clk_register()
310 u32 pll0cr = readl(base in rcar_gen2_cpg_clk_register()
136 cpg_z_clk_register(const char *name, const char *parent_name, void __iomem *base) cpg_z_clk_register() argument
165 cpg_rcan_clk_register(const char *name, const char *parent_name, void __iomem *base) cpg_rcan_clk_register() argument
209 cpg_adsp_clk_register(const char *name, const char *parent_name, void __iomem *base) cpg_adsp_clk_register() argument
276 rcar_gen2_cpg_clk_register(struct device *dev, const struct cpg_core_clk *core, const struct cpg_mssr_info *info, struct clk **clks, void __iomem *base, struct raw_notifier_head *notifiers) rcar_gen2_cpg_clk_register() argument
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/kernel/linux/linux-5.10/drivers/gpio/
H A Dgpio-vf610.c33 void __iomem *base; member
120 return pinctrl_gpio_direction_input(chip->base + gpio); in vf610_gpio_direction_input()
138 return pinctrl_gpio_direction_output(chip->base + gpio); in vf610_gpio_direction_output()
151 irq_isfr = vf610_gpio_readl(port->base + PORT_ISFR); in vf610_gpio_irq_handler()
154 vf610_gpio_writel(BIT(pin), port->base + PORT_ISFR); in vf610_gpio_irq_handler()
168 vf610_gpio_writel(BIT(gpio), port->base + PORT_ISFR); in vf610_gpio_irq_ack()
211 void __iomem *pcr_base = port->base + PORT_PCR(d->hwirq); in vf610_gpio_irq_mask()
220 void __iomem *pcr_base = port->base + PORT_PCR(d->hwirq); in vf610_gpio_irq_unmask()
260 port->base = devm_platform_ioremap_resource(pdev, 0); in vf610_gpio_probe()
261 if (IS_ERR(port->base)) in vf610_gpio_probe()
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/kernel/linux/linux-6.6/arch/arm/mm/
H A Dpmsa-v7.c20 phys_addr_t base; member
66 /* Region base address register */
90 /* I-side Region base address register */
126 /* Region base address register */
146 static bool __init try_split_region(phys_addr_t base, phys_addr_t size, struct region *region) in try_split_region() argument
149 phys_addr_t abase = base & ~(size - 1); in try_split_region()
150 phys_addr_t asize = base + size - abase; in try_split_region()
157 bdiff = base - abase; in try_split_region()
183 region->base = abase; in try_split_region()
189 static int __init allocate_region(phys_addr_t base, phys_addr_ argument
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/kernel/linux/linux-6.6/arch/sparc/crypto/
H A Dcamellia_glue.c218 .base.cra_name = "ecb(camellia)",
219 .base.cra_driver_name = "ecb-camellia-sparc64",
220 .base.cra_priority = SPARC_CR_OPCODE_PRIORITY,
221 .base.cra_blocksize = CAMELLIA_BLOCK_SIZE,
222 .base.cra_ctxsize = sizeof(struct camellia_sparc64_ctx),
223 .base.cra_alignmask = 7,
224 .base.cra_module = THIS_MODULE,
231 .base.cra_name = "cbc(camellia)",
232 .base.cra_driver_name = "cbc-camellia-sparc64",
233 .base
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/kernel/linux/linux-5.10/drivers/gpu/drm/i915/gt/
H A Dselftest_engine_cs.c255 struct i915_vma *base, *nop; in perf_mi_noop() local
261 base = create_empty_batch(ce); in perf_mi_noop()
262 if (IS_ERR(base)) { in perf_mi_noop()
263 err = PTR_ERR(base); in perf_mi_noop()
268 err = i915_vma_sync(base); in perf_mi_noop()
270 i915_vma_put(base); in perf_mi_noop()
278 i915_vma_put(base); in perf_mi_noop()
286 i915_vma_put(base); in perf_mi_noop()
305 base->node.start, 8, in perf_mi_noop()
340 i915_vma_put(base); in perf_mi_noop()
377 u32 base = info->mmio_bases[j].base; intel_mmio_bases_check() local
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/kernel/linux/linux-5.10/drivers/irqchip/
H A Dirq-tegra.c69 void __iomem *base[TEGRA_MAX_NUM_ICTLRS]; member
84 void __iomem *base = (void __iomem __force *)d->chip_data; in tegra_ictlr_write_mask() local
88 writel_relaxed(mask, base + reg); in tegra_ictlr_write_mask()
142 void __iomem *ictlr = lic->base[i]; in tegra_ictlr_suspend()
171 void __iomem *ictlr = lic->base[i]; in tegra_ictlr_resume()
260 (void __force *)info->base[ictlr]); in tegra_ictlr_domain_alloc()
306 void __iomem *base; in tegra_ictlr_init() local
308 base = of_iomap(node, i); in tegra_ictlr_init()
309 if (!base) in tegra_ictlr_init()
312 lic->base[ in tegra_ictlr_init()
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/kernel/linux/linux-5.10/drivers/mmc/host/
H A Dcavium-octeon.c110 writeq(val, host->base + MIO_EMM_INT(host)); in octeon_mmc_int_enable()
112 writeq(val, host->base + MIO_EMM_INT_EN(host)); in octeon_mmc_int_enable()
151 void __iomem *base; in octeon_mmc_probe() local
207 base = devm_platform_ioremap_resource(pdev, 0); in octeon_mmc_probe()
208 if (IS_ERR(base)) in octeon_mmc_probe()
209 return PTR_ERR(base); in octeon_mmc_probe()
210 host->base = base; in octeon_mmc_probe()
213 base = devm_platform_ioremap_resource(pdev, 1); in octeon_mmc_probe()
214 if (IS_ERR(base)) in octeon_mmc_probe()
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/kernel/linux/linux-5.10/drivers/iio/adc/
H A Dstx104.c44 static unsigned int base[max_num_isa_dev(STX104_EXTENT)]; variable
46 module_param_hw_array(base, uint, ioport, &num_stx104, 0);
47 MODULE_PARM_DESC(base, "Apex Embedded Systems STX104 base addresses");
87 * @base: base port address of the GPIO device
93 u8 __iomem *base; member
261 return !!(ioread8(stx104gpio->base) & BIT(offset)); in stx104_gpio_get()
269 *bits = ioread8(stx104gpio->base); in stx104_gpio_get_multiple()
291 iowrite8(stx104gpio->out_state, stx104gpio->base); in stx104_gpio_set()
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/kernel/linux/linux-5.10/net/rxrpc/
H A Dpeer_event.c304 time64_t base, in rxrpc_peer_keepalive_dispatch()
326 slot = keepalive_at - base; in rxrpc_peer_keepalive_dispatch()
330 if (keepalive_at <= base || in rxrpc_peer_keepalive_dispatch()
331 keepalive_at > base + RXRPC_KEEPALIVE_TIME) { in rxrpc_peer_keepalive_dispatch()
361 time64_t base, now, delay; in rxrpc_peer_keepalive_worker() local
366 base = rxnet->peer_keepalive_base; in rxrpc_peer_keepalive_worker()
368 _enter("%lld,%u", base - now, cursor); in rxrpc_peer_keepalive_worker()
384 while (base <= now && (s8)(cursor - stop) < 0) { in rxrpc_peer_keepalive_worker()
387 base++; in rxrpc_peer_keepalive_worker()
391 base in rxrpc_peer_keepalive_worker()
302 rxrpc_peer_keepalive_dispatch(struct rxrpc_net *rxnet, struct list_head *collector, time64_t base, u8 cursor) rxrpc_peer_keepalive_dispatch() argument
[all...]
/kernel/linux/linux-5.10/sound/soc/zte/
H A Dzx-spdif.c93 static int zx_spdif_chanstats(void __iomem *base, unsigned int rate) in zx_spdif_chanstats() argument
131 writel_relaxed(cstas1, base + ZX_CH_STA_1); in zx_spdif_chanstats()
193 static void zx_spdif_cfg_tx(void __iomem *base, int on) in zx_spdif_cfg_tx() argument
197 val = readl_relaxed(base + ZX_CTRL); in zx_spdif_cfg_tx()
200 writel_relaxed(val, base + ZX_CTRL); in zx_spdif_cfg_tx()
202 val = readl_relaxed(base + ZX_FIFOCTRL); in zx_spdif_cfg_tx()
206 writel_relaxed(val, base + ZX_FIFOCTRL); in zx_spdif_cfg_tx()
290 static void zx_spdif_dev_init(void __iomem *base) in zx_spdif_dev_init() argument
294 writel_relaxed(0, base + ZX_CTRL); in zx_spdif_dev_init()
295 writel_relaxed(0, base in zx_spdif_dev_init()
[all...]
/kernel/linux/linux-6.6/drivers/mmc/host/
H A Dcavium-octeon.c112 writeq(val, host->base + MIO_EMM_INT(host)); in octeon_mmc_int_enable()
114 writeq(val, host->base + MIO_EMM_INT_EN(host)); in octeon_mmc_int_enable()
153 void __iomem *base; in octeon_mmc_probe() local
209 base = devm_platform_ioremap_resource(pdev, 0); in octeon_mmc_probe()
210 if (IS_ERR(base)) in octeon_mmc_probe()
211 return PTR_ERR(base); in octeon_mmc_probe()
212 host->base = base; in octeon_mmc_probe()
215 base = devm_platform_ioremap_resource(pdev, 1); in octeon_mmc_probe()
216 if (IS_ERR(base)) in octeon_mmc_probe()
[all...]
/kernel/linux/linux-6.6/drivers/media/rc/
H A Dsunxi-cir.c91 void __iomem *base; member
108 status = readl(ir->base + SUNXI_IR_RXSTA_REG); in sunxi_ir_irq()
111 writel(status | REG_RXSTA_CLEARALL, ir->base + SUNXI_IR_RXSTA_REG); in sunxi_ir_irq()
121 dt = readb(ir->base + SUNXI_IR_RXFIFO_REG); in sunxi_ir_irq()
166 ir->base + SUNXI_IR_CIR_REG); in sunxi_ir_set_timeout()
196 writel(REG_CTL_MD, ir->base + SUNXI_IR_CTL_REG); in sunxi_ir_hw_init()
202 writel(REG_RXCTL_RPPI, ir->base + SUNXI_IR_RXCTL_REG); in sunxi_ir_hw_init()
205 writel(REG_RXSTA_CLEARALL, ir->base + SUNXI_IR_RXSTA_REG); in sunxi_ir_hw_init()
213 ir->base + SUNXI_IR_RXINT_REG); in sunxi_ir_hw_init()
216 tmp = readl(ir->base in sunxi_ir_hw_init()
[all...]
/kernel/linux/linux-6.6/drivers/gpio/
H A Dgpio-vf610.c32 void __iomem *base; member
119 return pinctrl_gpio_direction_input(chip->base + gpio); in vf610_gpio_direction_input()
137 return pinctrl_gpio_direction_output(chip->base + gpio); in vf610_gpio_direction_output()
150 irq_isfr = vf610_gpio_readl(port->base + PORT_ISFR); in vf610_gpio_irq_handler()
153 vf610_gpio_writel(BIT(pin), port->base + PORT_ISFR); in vf610_gpio_irq_handler()
167 vf610_gpio_writel(BIT(gpio), port->base + PORT_ISFR); in vf610_gpio_irq_ack()
211 void __iomem *pcr_base = port->base + PORT_PCR(gpio_num); in vf610_gpio_irq_mask()
222 void __iomem *pcr_base = port->base + PORT_PCR(gpio_num); in vf610_gpio_irq_unmask()
273 port->base = devm_platform_ioremap_resource(pdev, 0); in vf610_gpio_probe()
274 if (IS_ERR(port->base)) in vf610_gpio_probe()
[all...]
/kernel/linux/linux-6.6/drivers/clk/renesas/
H A Drcar-gen2-cpg.c138 void __iomem *base) in cpg_z_clk_register()
153 zclk->reg = base + CPG_FRQCRC; in cpg_z_clk_register()
154 zclk->kick_reg = base + CPG_FRQCRB; in cpg_z_clk_register()
166 void __iomem *base) in cpg_rcan_clk_register()
185 gate->reg = base + CPG_RCANCKCR; in cpg_rcan_clk_register()
210 void __iomem *base) in cpg_adsp_clk_register()
220 div->reg = base + CPG_ADSPCKCR; in cpg_adsp_clk_register()
231 gate->reg = base + CPG_ADSPCKCR; in cpg_adsp_clk_register()
277 struct clk **clks, void __iomem *base, in rcar_gen2_cpg_clk_register()
309 u32 pll0cr = readl(base in rcar_gen2_cpg_clk_register()
136 cpg_z_clk_register(const char *name, const char *parent_name, void __iomem *base) cpg_z_clk_register() argument
164 cpg_rcan_clk_register(const char *name, const char *parent_name, void __iomem *base) cpg_rcan_clk_register() argument
208 cpg_adsp_clk_register(const char *name, const char *parent_name, void __iomem *base) cpg_adsp_clk_register() argument
275 rcar_gen2_cpg_clk_register(struct device *dev, const struct cpg_core_clk *core, const struct cpg_mssr_info *info, struct clk **clks, void __iomem *base, struct raw_notifier_head *notifiers) rcar_gen2_cpg_clk_register() argument
[all...]
/kernel/linux/linux-6.6/drivers/phy/freescale/
H A Dphy-fsl-imx8m-pcie.c60 void __iomem *base; member
87 imx8_phy->base + PCIE_PHY_TRSV_REG5); in imx8_pcie_phy_power_on()
90 imx8_phy->base + PCIE_PHY_TRSV_REG6); in imx8_pcie_phy_power_on()
99 val = readl(imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG061); in imx8_pcie_phy_power_on()
101 imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG061); in imx8_pcie_phy_power_on()
105 imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG061); in imx8_pcie_phy_power_on()
112 imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG062); in imx8_pcie_phy_power_on()
114 imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG063); in imx8_pcie_phy_power_on()
117 imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG064); in imx8_pcie_phy_power_on()
119 imx8_phy->base in imx8_pcie_phy_power_on()
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