/kernel/linux/linux-5.10/drivers/media/rc/ |
H A D | sunxi-cir.c | 95 void __iomem *base; member 114 status = readl(ir->base + SUNXI_IR_RXSTA_REG); in sunxi_ir_irq() 117 writel(status | REG_RXSTA_CLEARALL, ir->base + SUNXI_IR_RXSTA_REG); in sunxi_ir_irq() 127 dt = readb(ir->base + SUNXI_IR_RXFIFO_REG); in sunxi_ir_irq() 202 dev_err(dev, "set ir base clock failed!\n"); in sunxi_ir_probe() 205 dev_dbg(dev, "set base clock frequency to %d Hz.\n", b_clk_freq); in sunxi_ir_probe() 221 ir->base = devm_ioremap_resource(dev, res); in sunxi_ir_probe() 222 if (IS_ERR(ir->base)) { in sunxi_ir_probe() 223 ret = PTR_ERR(ir->base); in sunxi_ir_probe() 272 writel(REG_CTL_MD, ir->base in sunxi_ir_probe() [all...] |
/kernel/linux/linux-5.10/drivers/parport/ |
H A D | parport_sunbpp.c | 53 struct bpp_regs __iomem *regs = (struct bpp_regs __iomem *)p->base; in parport_sunbpp_disable_irq() 63 struct bpp_regs __iomem *regs = (struct bpp_regs __iomem *)p->base; in parport_sunbpp_enable_irq() 73 struct bpp_regs __iomem *regs = (struct bpp_regs __iomem *)p->base; in parport_sunbpp_write_data() 81 struct bpp_regs __iomem *regs = (struct bpp_regs __iomem *)p->base; in parport_sunbpp_read_data() 88 struct bpp_regs __iomem *regs = (struct bpp_regs __iomem *)p->base; in status_sunbpp_to_pc() 111 struct bpp_regs __iomem *regs = (struct bpp_regs __iomem *)p->base; in control_sunbpp_to_pc() 139 struct bpp_regs __iomem *regs = (struct bpp_regs __iomem *)p->base; in parport_sunbpp_frob_control() 198 struct bpp_regs __iomem *regs = (struct bpp_regs __iomem *)p->base; in parport_sunbpp_data_forward() 208 struct bpp_regs __iomem *regs = (struct bpp_regs __iomem *)p->base; in parport_sunbpp_data_reverse() 275 void __iomem *base; in bpp_probe() local [all...] |
/kernel/linux/linux-6.6/drivers/watchdog/ |
H A D | realtek_otto_wdt.c | 69 void __iomem *base; member 79 v = ioread32(ctrl->base + OTTO_WDT_REG_CTRL); in otto_wdt_start() 81 iowrite32(v, ctrl->base + OTTO_WDT_REG_CTRL); in otto_wdt_start() 91 v = ioread32(ctrl->base + OTTO_WDT_REG_CTRL); in otto_wdt_stop() 93 iowrite32(v, ctrl->base + OTTO_WDT_REG_CTRL); in otto_wdt_stop() 102 iowrite32(OTTO_WDT_CNTR_PING, ctrl->base + OTTO_WDT_REG_CNTR); in otto_wdt_ping() 151 v = ioread32(ctrl->base + OTTO_WDT_REG_CTRL); in otto_wdt_determine_timeouts() 158 iowrite32(v, ctrl->base + OTTO_WDT_REG_CTRL); in otto_wdt_determine_timeouts() 202 iowrite32(v, ctrl->base + OTTO_WDT_REG_CTRL); in otto_wdt_restart() 213 iowrite32(OTTO_WDT_INTR_PHASE_1, ctrl->base in otto_wdt_phase1_isr() [all...] |
/kernel/linux/linux-6.6/drivers/soc/qcom/ |
H A D | ice.c | 38 writel((val), (engine)->base + (reg)) 41 readl((engine)->base + (reg)) 45 void __iomem *base; member 122 err = readl_poll_timeout(ice->base + QCOM_ICE_REG_BIST_STATUS, in qcom_ice_wait_bist_status() 209 void __iomem *base) in qcom_ice_create() 226 engine->base = base; in qcom_ice_create() 270 void __iomem *base; in of_qcom_ice_get() local 282 base = devm_ioremap_resource(&pdev->dev, res); in of_qcom_ice_get() 283 if (IS_ERR(base)) in of_qcom_ice_get() 208 qcom_ice_create(struct device *dev, void __iomem *base) qcom_ice_create() argument 334 void __iomem *base; qcom_ice_probe() local [all...] |
/kernel/linux/linux-6.6/drivers/clk/ |
H A D | clk-en7523.c | 46 void __iomem *base; member 153 static unsigned int en7523_get_base_rate(void __iomem *base, unsigned int i) in en7523_get_base_rate() argument 161 val = readl(base + desc->base_reg); in en7523_get_base_rate() 171 static u32 en7523_get_div(void __iomem *base, int i) in en7523_get_div() argument 180 val = readl(base + reg); in en7523_get_div() 194 return !!(readl(cg->base + REG_PCI_CONTROL) & REG_PCI_CONTROL_REFCLK_EN1); in en7523_pci_is_enabled() 200 void __iomem *np_base = cg->base; in en7523_pci_prepare() 239 void __iomem *np_base = cg->base; in en7523_pci_unprepare() 265 cg->base = np_base; in en7523_register_pcie_clk() 276 void __iomem *base, voi in en7523_register_clocks() 275 en7523_register_clocks(struct device *dev, struct clk_hw_onecell_data *clk_data, void __iomem *base, void __iomem *np_base) en7523_register_clocks() argument 308 void __iomem *base, *np_base; en7523_clk_probe() local [all...] |
/kernel/linux/linux-6.6/drivers/gpio/ |
H A D | gpio-ixp4xx.c | 46 * @base: remapped I/O-memory base 54 void __iomem *base; member 63 __raw_writel(BIT(d->hwirq), g->base + IXP4XX_REG_GPIS); in ixp4xx_gpio_irq_ack() 139 val = __raw_readl(g->base + int_reg); in ixp4xx_gpio_irq_set_type() 141 __raw_writel(val, g->base + int_reg); in ixp4xx_gpio_irq_set_type() 143 __raw_writel(BIT(line), g->base + IXP4XX_REG_GPIS); in ixp4xx_gpio_irq_set_type() 146 val = __raw_readl(g->base + int_reg); in ixp4xx_gpio_irq_set_type() 148 __raw_writel(val, g->base + int_reg); in ixp4xx_gpio_irq_set_type() 151 val = __raw_readl(g->base in ixp4xx_gpio_irq_set_type() [all...] |
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dcn20/ |
H A D | dcn20_dwb.c | 37 dwbc20->base.ctx 40 dwbc20->base.ctx->logger 64 DC_LOG_DWB("%s SUPPORTED! inst = %d", __func__, dwbc20->base.inst); in dwb2_get_caps() 67 DC_LOG_DWB("%s NOT SUPPORTED! inst = %d", __func__, dwbc20->base.inst); in dwb2_get_caps() 75 DC_LOG_DWB("%s inst = %d", __func__, dwbc20->base.inst); in dwb2_config_dwb_cnv() 107 DC_LOG_DWB("%s inst = %d, FAILED!LUMA SCALING NOT SUPPORTED", __func__, dwbc20->base.inst); in dwb2_enable() 110 DC_LOG_DWB("%s inst = %d, ENABLED", __func__, dwbc20->base.inst); in dwb2_enable() 138 DC_LOG_DWB("%s inst = %d, Disabled", __func__, dwbc20->base.inst); in dwb2_disable() 166 DC_LOG_DWB("%s inst = %d, FAILED!LUMA SCALING NOT SUPPORTED", __func__, dwbc20->base.inst); in dwb2_update() 169 DC_LOG_DWB("%s inst = %d, scaling", __func__, dwbc20->base in dwb2_update() [all...] |
/kernel/linux/linux-6.6/drivers/clocksource/ |
H A D | timer-fsl-ftm.c | 48 static inline void ftm_counter_enable(void __iomem *base) in ftm_counter_enable() argument 53 val = ftm_readl(base + FTM_SC); in ftm_counter_enable() 56 ftm_writel(val, base + FTM_SC); in ftm_counter_enable() 59 static inline void ftm_counter_disable(void __iomem *base) in ftm_counter_disable() argument 64 val = ftm_readl(base + FTM_SC); in ftm_counter_disable() 66 ftm_writel(val, base + FTM_SC); in ftm_counter_disable() 69 static inline void ftm_irq_acknowledge(void __iomem *base) in ftm_irq_acknowledge() argument 73 val = ftm_readl(base + FTM_SC); in ftm_irq_acknowledge() 75 ftm_writel(val, base + FTM_SC); in ftm_irq_acknowledge() 78 static inline void ftm_irq_enable(void __iomem *base) in ftm_irq_enable() argument 87 ftm_irq_disable(void __iomem *base) ftm_irq_disable() argument 96 ftm_reset_counter(void __iomem *base) ftm_reset_counter() argument [all...] |
/kernel/linux/linux-6.6/drivers/parport/ |
H A D | parport_sunbpp.c | 53 struct bpp_regs __iomem *regs = (struct bpp_regs __iomem *)p->base; in parport_sunbpp_disable_irq() 63 struct bpp_regs __iomem *regs = (struct bpp_regs __iomem *)p->base; in parport_sunbpp_enable_irq() 73 struct bpp_regs __iomem *regs = (struct bpp_regs __iomem *)p->base; in parport_sunbpp_write_data() 81 struct bpp_regs __iomem *regs = (struct bpp_regs __iomem *)p->base; in parport_sunbpp_read_data() 88 struct bpp_regs __iomem *regs = (struct bpp_regs __iomem *)p->base; in status_sunbpp_to_pc() 111 struct bpp_regs __iomem *regs = (struct bpp_regs __iomem *)p->base; in control_sunbpp_to_pc() 139 struct bpp_regs __iomem *regs = (struct bpp_regs __iomem *)p->base; in parport_sunbpp_frob_control() 198 struct bpp_regs __iomem *regs = (struct bpp_regs __iomem *)p->base; in parport_sunbpp_data_forward() 208 struct bpp_regs __iomem *regs = (struct bpp_regs __iomem *)p->base; in parport_sunbpp_data_reverse() 275 void __iomem *base; in bpp_probe() local [all...] |
/kernel/linux/linux-6.6/crypto/ |
H A D | aead.c | 170 aead->base.exit = crypto_aead_exit_tfm; in crypto_aead_init_tfm() 182 struct aead_alg *aead = container_of(alg, struct aead_alg, base); in crypto_aead_report() 200 struct aead_alg *aead = container_of(alg, struct aead_alg, base); in crypto_aead_show() 221 struct aead_alg *aead = container_of(alg, struct aead_alg, base); in crypto_aead_report_stat() 254 .tfmsize = offsetof(struct crypto_aead, base), 261 spawn->base.frontend = &crypto_aead_type; in crypto_grab_aead() 262 return crypto_grab_spawn(&spawn->base, inst, name, type, mask); in crypto_grab_aead() 275 struct crypto_alg *base = &alg->base; in aead_prepare_alg() local 282 alg->chunksize = base in aead_prepare_alg() 296 struct crypto_alg *base = &alg->base; crypto_register_aead() local [all...] |
/kernel/linux/linux-6.6/drivers/gpu/drm/nouveau/dispnv04/ |
H A D | disp.c | 117 nv_crtc->save(&nv_crtc->base); in nv04_display_init() 120 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.base.head) in nv04_display_init() 121 encoder->enc_save(&encoder->base.base); in nv04_display_init() 197 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.base.head) in nv04_display_destroy() 198 encoder->enc_restore(&encoder->base.base); in nv04_display_destroy() 200 list_for_each_entry(nv_crtc, &dev->mode_config.crtc_list, base in nv04_display_destroy() [all...] |
/kernel/linux/linux-6.6/drivers/gpu/drm/ttm/ |
H A D | ttm_bo_vm.c | 49 if (dma_resv_test_signaled(bo->base.resv, DMA_RESV_USAGE_KERNEL)) in ttm_bo_vm_fault_idle() 63 (void)dma_resv_wait_timeout(bo->base.resv, in ttm_bo_vm_fault_idle() 66 dma_resv_unlock(bo->base.resv); in ttm_bo_vm_fault_idle() 74 err = dma_resv_wait_timeout(bo->base.resv, DMA_RESV_USAGE_KERNEL, true, in ttm_bo_vm_fault_idle() 125 if (unlikely(!dma_resv_trylock(bo->base.resv))) { in ttm_bo_vm_reserve() 135 if (!dma_resv_lock_interruptible(bo->base.resv, in ttm_bo_vm_reserve() 137 dma_resv_unlock(bo->base.resv); in ttm_bo_vm_reserve() 144 if (dma_resv_lock_interruptible(bo->base.resv, NULL)) in ttm_bo_vm_reserve() 154 dma_resv_unlock(bo->base.resv); in ttm_bo_vm_reserve() 211 vma->vm_pgoff - drm_vma_node_start(&bo->base in ttm_bo_vm_fault_reserved() [all...] |
/third_party/mesa3d/src/egl/drivers/dri2/ |
H A D | platform_device.c | 53 dri2_surf->base.Width, in device_alloc_image() 54 dri2_surf->base.Height, in device_alloc_image() 64 dri2_egl_display(dri2_surf->base.Resource.Display); in device_free_images() 85 dri2_egl_display(dri2_surf->base.Resource.Display); in device_image_get_buffers() 137 if (!dri2_init_surface(&dri2_surf->base, disp, type, conf, attrib_list, in dri2_device_create_surface() 142 dri2_surf->base.GLColorspace); in dri2_device_create_surface() 156 return &dri2_surf->base; in dri2_device_create_surface() 210 .base = { __DRI_IMAGE_LOADER, 2 }, 217 .base = { __DRI_KOPPER_LOADER, 1 }, 223 &image_loader_extension.base, [all...] |
/third_party/mesa3d/src/freedreno/decode/scripts/ |
H A D | parse-submits.lua | 20 function push_mrt(fmt, w, h, samples, base, flag, gmem) 21 dbg("MRT: %s %ux%u 0x%x\n", fmt, w, h, base) 28 mrt.base = base 32 mrts[base] = mrt 33 allmrts[base] = mrt 38 function push_source(fmt, w, h, samples, base, flag) 39 dbg("SRC: %s %ux%u 0x%x\n", fmt, w, h, base) 46 source.base = base [all...] |
/kernel/linux/linux-5.10/drivers/gpio/ |
H A D | gpio-spear-spics.c | 35 * @base: base address 46 void __iomem *base; member 69 tmp = readl_relaxed(spics->base + spics->perip_cfg); in spics_set_value() 79 writel_relaxed(tmp, spics->base + spics->perip_cfg); in spics_set_value() 100 tmp = readl_relaxed(spics->base + spics->perip_cfg); in spics_request() 103 writel_relaxed(tmp, spics->base + spics->perip_cfg); in spics_request() 115 tmp = readl_relaxed(spics->base + spics->perip_cfg); in spics_free() 117 writel_relaxed(tmp, spics->base + spics->perip_cfg); in spics_free() 131 spics->base in spics_gpio_probe() [all...] |
/kernel/linux/linux-5.10/drivers/dma-buf/ |
H A D | dma-fence-chain.c | 98 if (!chain || chain->base.seqno < seqno) in dma_fence_chain_find_seqno() 101 dma_fence_chain_for_each(*pfence, &chain->base) { in dma_fence_chain_find_seqno() 102 if ((*pfence)->context != chain->base.context || in dma_fence_chain_find_seqno() 106 dma_fence_put(&chain->base); in dma_fence_chain_find_seqno() 129 if (!dma_fence_chain_enable_signaling(&chain->base)) in dma_fence_chain_irq_work() 131 dma_fence_signal(&chain->base); in dma_fence_chain_irq_work() 132 dma_fence_put(&chain->base); in dma_fence_chain_irq_work() 148 dma_fence_get(&head->base); in dma_fence_chain_enable_signaling() 149 dma_fence_chain_for_each(fence, &head->base) { in dma_fence_chain_enable_signaling() 160 dma_fence_put(&head->base); in dma_fence_chain_enable_signaling() [all...] |
/kernel/linux/linux-5.10/crypto/ |
H A D | geniv.c | 77 if (snprintf(inst->alg.base.cra_name, CRYPTO_MAX_ALG_NAME, in aead_geniv_alloc() 78 "%s(%s)", tmpl->name, alg->base.cra_name) >= in aead_geniv_alloc() 81 if (snprintf(inst->alg.base.cra_driver_name, CRYPTO_MAX_ALG_NAME, in aead_geniv_alloc() 82 "%s(%s)", tmpl->name, alg->base.cra_driver_name) >= in aead_geniv_alloc() 86 inst->alg.base.cra_priority = alg->base.cra_priority; in aead_geniv_alloc() 87 inst->alg.base.cra_blocksize = alg->base.cra_blocksize; in aead_geniv_alloc() 88 inst->alg.base.cra_alignmask = alg->base in aead_geniv_alloc() [all...] |
/kernel/linux/linux-5.10/drivers/clocksource/ |
H A D | timer-digicolor.c | 62 void __iomem *base; member 75 writeb(CONTROL_DISABLE, dt->base + CONTROL(dt->timer_id)); in dc_timer_disable() 81 writeb(CONTROL_ENABLE | mode, dt->base + CONTROL(dt->timer_id)); in dc_timer_enable() 88 writel(count, dt->base + COUNT(dt->timer_id)); in dc_timer_set_count() 149 return ~readl(dc_timer_dev.base + COUNT(TIMER_B)); in digicolor_timer_sched_read() 162 dc_timer_dev.base = of_iomap(node, 0); in digicolor_timer_init() 163 if (!dc_timer_dev.base) { in digicolor_timer_init() 183 writeb(CONTROL_DISABLE, dc_timer_dev.base + CONTROL(TIMER_B)); in digicolor_timer_init() 184 writel(UINT_MAX, dc_timer_dev.base + COUNT(TIMER_B)); in digicolor_timer_init() 185 writeb(CONTROL_ENABLE, dc_timer_dev.base in digicolor_timer_init() [all...] |
/kernel/linux/linux-5.10/drivers/clk/ |
H A D | clk-clps711x.c | 49 void __iomem *base; in clps711x_clk_init_dt() local 53 base = of_iomap(np, 0); in clps711x_clk_init_dt() 54 BUG_ON(!base); in clps711x_clk_init_dt() 64 tmp = readl(base + CLPS711X_PLLR) >> 24; in clps711x_clk_init_dt() 70 tmp = readl(base + CLPS711X_SYSFLG2); in clps711x_clk_init_dt() 88 if (readl(base + CLPS711X_SYSCON2) & SYSCON2_OSTB) in clps711x_clk_init_dt() 95 tmp = readl(base + CLPS711X_SYSCON1); in clps711x_clk_init_dt() 106 writel(tmp, base + CLPS711X_SYSCON1); in clps711x_clk_init_dt() 120 base + CLPS711X_SYSCON1, 5, 1, 0, in clps711x_clk_init_dt() 124 base in clps711x_clk_init_dt() [all...] |
/kernel/linux/linux-5.10/drivers/gpu/drm/omapdrm/dss/ |
H A D | hdmi_phy.c | 22 hdmi_read_reg(phy->base, r)) in hdmi_phy_dump() 119 REG_FLD_MOD(phy->base, HDMI_TXPHY_PAD_CFG_CTRL, lane_cfg_val, 26, 22); in hdmi_phy_configure_lanes() 120 REG_FLD_MOD(phy->base, HDMI_TXPHY_PAD_CFG_CTRL, pol_val, 30, 27); in hdmi_phy_configure_lanes() 132 hdmi_read_reg(phy->base, HDMI_TXPHY_TX_CTRL); in hdmi_phy_configure() 139 REG_FLD_MOD(phy->base, HDMI_TXPHY_BIST_CONTROL, 1, 11, 11); in hdmi_phy_configure() 156 REG_FLD_MOD(phy->base, HDMI_TXPHY_TX_CTRL, freqout, 31, 30); in hdmi_phy_configure() 159 hdmi_write_reg(phy->base, HDMI_TXPHY_DIGITAL_CTRL, 0xF0000000); in hdmi_phy_configure() 163 REG_FLD_MOD(phy->base, HDMI_TXPHY_POWER_CTRL, 0xB, 3, 0); in hdmi_phy_configure() 193 phy->base = devm_ioremap_resource(&pdev->dev, res); in hdmi_phy_init() 194 if (IS_ERR(phy->base)) in hdmi_phy_init() [all...] |
/kernel/linux/linux-5.10/drivers/hwspinlock/ |
H A D | qcom_hwspinlock.c | 74 u32 *base, u32 *stride) in qcom_hwspinlock_probe_syscon() 89 ret = of_property_read_u32_index(pdev->dev.of_node, "syscon", 1, base); in qcom_hwspinlock_probe_syscon() 116 void __iomem *base; in qcom_hwspinlock_probe_mmio() local 122 base = devm_platform_ioremap_resource(pdev, 0); in qcom_hwspinlock_probe_mmio() 123 if (IS_ERR(base)) in qcom_hwspinlock_probe_mmio() 124 return ERR_CAST(base); in qcom_hwspinlock_probe_mmio() 126 return devm_regmap_init_mmio(dev, base, &tcsr_mutex_config); in qcom_hwspinlock_probe_mmio() 136 u32 base; in qcom_hwspinlock_probe() local 139 regmap = qcom_hwspinlock_probe_syscon(pdev, &base, &stride); in qcom_hwspinlock_probe() 141 regmap = qcom_hwspinlock_probe_mmio(pdev, &base, in qcom_hwspinlock_probe() 73 qcom_hwspinlock_probe_syscon(struct platform_device *pdev, u32 *base, u32 *stride) qcom_hwspinlock_probe_syscon() argument [all...] |
/kernel/linux/linux-5.10/drivers/scsi/ |
H A D | fdomain_isa.c | 12 MODULE_PARM_DESC(io, "base I/O address of controller (0x140, 0x150, 0x160, 0x170)"); 89 int i, base = 0, irq = 0; in fdomain_isa_match() local 109 /* read I/O base from BIOS area */ in fdomain_isa_match() 111 base = readb(p + sig->base_offset) + in fdomain_isa_match() 114 if (base) { in fdomain_isa_match() 115 dev_info(dev, "BIOS at 0x%lx specifies I/O base 0x%x\n", in fdomain_isa_match() 116 bios_base, base); in fdomain_isa_match() 117 } else { /* no I/O base in BIOS area */ in fdomain_isa_match() 124 base = ports[ndev - ADDRESS_COUNT]; in fdomain_isa_match() 130 if (!request_region(base, FDOMAIN_REGION_SIZ in fdomain_isa_match() 181 int base = sh->io_port; fdomain_isa_remove() local [all...] |
/kernel/linux/linux-5.10/drivers/video/fbdev/omap2/omapfb/dss/ |
H A D | hdmi_phy.c | 31 hdmi_read_reg(phy->base, r)) in hdmi_phy_dump() 128 REG_FLD_MOD(phy->base, HDMI_TXPHY_PAD_CFG_CTRL, lane_cfg_val, 26, 22); in hdmi_phy_configure_lanes() 129 REG_FLD_MOD(phy->base, HDMI_TXPHY_PAD_CFG_CTRL, pol_val, 30, 27); in hdmi_phy_configure_lanes() 141 hdmi_read_reg(phy->base, HDMI_TXPHY_TX_CTRL); in hdmi_phy_configure() 148 REG_FLD_MOD(phy->base, HDMI_TXPHY_BIST_CONTROL, 1, 11, 11); in hdmi_phy_configure() 165 REG_FLD_MOD(phy->base, HDMI_TXPHY_TX_CTRL, freqout, 31, 30); in hdmi_phy_configure() 168 hdmi_write_reg(phy->base, HDMI_TXPHY_DIGITAL_CTRL, 0xF0000000); in hdmi_phy_configure() 172 REG_FLD_MOD(phy->base, HDMI_TXPHY_POWER_CTRL, 0xB, 3, 0); in hdmi_phy_configure() 222 phy->base = devm_ioremap_resource(&pdev->dev, res); in hdmi_phy_init() 223 if (IS_ERR(phy->base)) { in hdmi_phy_init() [all...] |
/kernel/linux/linux-5.10/drivers/watchdog/ |
H A D | moxart_wdt.c | 29 void __iomem *base; member 40 writel(1, moxart_wdt->base + REG_COUNT); in moxart_wdt_restart() 41 writel(0x5ab9, moxart_wdt->base + REG_MODE); in moxart_wdt_restart() 42 writel(0x03, moxart_wdt->base + REG_ENABLE); in moxart_wdt_restart() 51 writel(0, moxart_wdt->base + REG_ENABLE); in moxart_wdt_stop() 61 moxart_wdt->base + REG_COUNT); in moxart_wdt_start() 62 writel(0x5ab9, moxart_wdt->base + REG_MODE); in moxart_wdt_start() 63 writel(0x03, moxart_wdt->base + REG_ENABLE); in moxart_wdt_start() 105 moxart_wdt->base = devm_platform_ioremap_resource(pdev, 0); in moxart_wdt_probe() 106 if (IS_ERR(moxart_wdt->base)) in moxart_wdt_probe() [all...] |
H A D | menz69_wdt.c | 15 void __iomem *base; member 39 val = readw(drv->base + MEN_Z069_WTR); in men_z069_wdt_start() 41 writew(val, drv->base + MEN_Z069_WTR); in men_z069_wdt_start() 51 val = readw(drv->base + MEN_Z069_WTR); in men_z069_wdt_stop() 53 writew(val, drv->base + MEN_Z069_WTR); in men_z069_wdt_stop() 64 val = readw(drv->base + MEN_Z069_WVR); in men_z069_wdt_ping() 66 writew(val, drv->base + MEN_Z069_WVR); in men_z069_wdt_ping() 80 reg = readw(drv->base + MEN_Z069_WVR); in men_z069_wdt_set_timeout() 83 writew(reg, drv->base + MEN_Z069_WTR); in men_z069_wdt_set_timeout() 115 drv->base in men_z069_probe() [all...] |